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[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314559 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eugene Zelenko 2017-09-29 21:55:49 +00:00
parent 35bfb7ddfe
commit 9434811032
14 changed files with 290 additions and 187 deletions
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104
include/llvm/CodeGen/BasicTTIImpl.h
View File

@ -6,25 +6,63 @@
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
/// \file
/// This file provides a helper that implements much of the TTI interface in
/// terms of the target-independent code generator and TargetLowering
/// interfaces.
///
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_CODEGEN_BASICTTIIMPL_H
#define LLVM_CODEGEN_BASICTTIIMPL_H
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/Analysis/TargetLibraryInfo.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/Analysis/TargetTransformInfoImpl.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/CallSite.h"
#include "llvm/IR/Constant.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/InstrTypes.h"
#include "llvm/IR/Instruction.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/Operator.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/Value.h"
#include "llvm/MC/MCSchedule.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <limits>
#include <utility>
namespace llvm {
class Function;
class GlobalValue;
class LLVMContext;
class ScalarEvolution;
class SCEV;
class TargetMachine;
extern cl::opt<unsigned> PartialUnrollingThreshold;
/// \brief Base class which can be used to help build a TTI implementation.
@ -39,8 +77,8 @@ extern cl::opt<unsigned> PartialUnrollingThreshold;
template <typename T>
class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
private:
typedef TargetTransformInfoImplCRTPBase<T> BaseT;
typedef TargetTransformInfo TTI;
using BaseT = TargetTransformInfoImplCRTPBase<T>;
using TTI = TargetTransformInfo;
/// Estimate a cost of shuffle as a sequence of extract and insert
/// operations.
@ -235,7 +273,8 @@ public:
if (N < 2 || N < TLI->getMinimumJumpTableEntries())
return N;
uint64_t Range =
(MaxCaseVal - MinCaseVal).getLimitedValue(UINT64_MAX - 1) + 1;
(MaxCaseVal - MinCaseVal)
.getLimitedValue(std::numeric_limits<uint64_t>::max() - 1) + 1;
// Check whether a range of clusters is dense enough for a jump table
if (TLI->isSuitableForJumpTable(&SI, N, Range)) {
JumpTableSize = Range;
@ -272,17 +311,15 @@ public:
const TargetLoweringBase *TLI = getTLI();
switch (Opcode) {
default: break;
case Instruction::Trunc: {
case Instruction::Trunc:
if (TLI->isTruncateFree(OpTy, Ty))
return TargetTransformInfo::TCC_Free;
return TargetTransformInfo::TCC_Basic;
}
case Instruction::ZExt: {
case Instruction::ZExt:
if (TLI->isZExtFree(OpTy, Ty))
return TargetTransformInfo::TCC_Free;
return TargetTransformInfo::TCC_Basic;
}
}
return BaseT::getOperationCost(Opcode, Ty, OpTy);
}
@ -401,8 +438,8 @@ public:
if (A->getType()->isVectorTy()) {
VecTy = A->getType();
// If A is a vector operand, VF should be 1 or correspond to A.
assert ((VF == 1 || VF == VecTy->getVectorNumElements()) &&
"Vector argument does not match VF");
assert((VF == 1 || VF == VecTy->getVectorNumElements()) &&
"Vector argument does not match VF");
}
else
VecTy = VectorType::get(A->getType(), VF);
@ -415,7 +452,7 @@ public:
}
unsigned getScalarizationOverhead(Type *VecTy, ArrayRef<const Value *> Args) {
assert (VecTy->isVectorTy());
assert(VecTy->isVectorTy());
unsigned Cost = 0;
@ -538,7 +575,6 @@ public:
// Handle scalar conversions.
if (!Src->isVectorTy() && !Dst->isVectorTy()) {
// Scalar bitcasts are usually free.
if (Opcode == Instruction::BitCast)
return 0;
@ -554,7 +590,6 @@ public:
// Check vector-to-vector casts.
if (Dst->isVectorTy() && Src->isVectorTy()) {
// If the cast is between same-sized registers, then the check is simple.
if (SrcLT.first == DstLT.first &&
SrcLT.second.getSizeInBits() == DstLT.second.getSizeInBits()) {
@ -750,7 +785,6 @@ public:
// We only scale the cost of loads since interleaved store groups aren't
// allowed to have gaps.
if (Opcode == Instruction::Load && VecTySize > VecTyLTSize) {
// The number of loads of a legal type it will take to represent a load
// of the unlegalized vector type.
unsigned NumLegalInsts = ceil(VecTySize, VecTyLTSize);
@ -828,7 +862,7 @@ public:
ArrayRef<Value *> Args, FastMathFlags FMF,
unsigned VF = 1) {
unsigned RetVF = (RetTy->isVectorTy() ? RetTy->getVectorNumElements() : 1);
assert ((RetVF == 1 || VF == 1) && "VF > 1 and RetVF is a vector type");
assert((RetVF == 1 || VF == 1) && "VF > 1 and RetVF is a vector type");
switch (IID) {
default: {
@ -836,7 +870,7 @@ public:
SmallVector<Type *, 4> Types;
for (Value *Op : Args) {
Type *OpTy = Op->getType();
assert (VF == 1 || !OpTy->isVectorTy());
assert(VF == 1 || !OpTy->isVectorTy());
Types.push_back(VF == 1 ? OpTy : VectorType::get(OpTy, VF));
}
@ -846,7 +880,7 @@ public:
// Compute the scalarization overhead based on Args for a vector
// intrinsic. A vectorizer will pass a scalar RetTy and VF > 1, while
// CostModel will pass a vector RetTy and VF is 1.
unsigned ScalarizationCost = UINT_MAX;
unsigned ScalarizationCost = std::numeric_limits<unsigned>::max();
if (RetVF > 1 || VF > 1) {
ScalarizationCost = 0;
if (!RetTy->isVoidTy())
@ -858,7 +892,7 @@ public:
getIntrinsicInstrCost(IID, RetTy, Types, FMF, ScalarizationCost);
}
case Intrinsic::masked_scatter: {
assert (VF == 1 && "Can't vectorize types here.");
assert(VF == 1 && "Can't vectorize types here.");
Value *Mask = Args[3];
bool VarMask = !isa<Constant>(Mask);
unsigned Alignment = cast<ConstantInt>(Args[2])->getZExtValue();
@ -869,7 +903,7 @@ public:
Alignment);
}
case Intrinsic::masked_gather: {
assert (VF == 1 && "Can't vectorize types here.");
assert(VF == 1 && "Can't vectorize types here.");
Value *Mask = Args[2];
bool VarMask = !isa<Constant>(Mask);
unsigned Alignment = cast<ConstantInt>(Args[1])->getZExtValue();
@ -882,11 +916,12 @@ public:
}
/// Get intrinsic cost based on argument types.
/// If ScalarizationCostPassed is UINT_MAX, the cost of scalarizing the
/// arguments and the return value will be computed based on types.
unsigned getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy,
ArrayRef<Type *> Tys, FastMathFlags FMF,
unsigned ScalarizationCostPassed = UINT_MAX) {
/// If ScalarizationCostPassed is std::numeric_limits<unsigned>::max(), the
/// cost of scalarizing the arguments and the return value will be computed
/// based on types.
unsigned getIntrinsicInstrCost(
Intrinsic::ID IID, Type *RetTy, ArrayRef<Type *> Tys, FastMathFlags FMF,
unsigned ScalarizationCostPassed = std::numeric_limits<unsigned>::max()) {
SmallVector<unsigned, 2> ISDs;
unsigned SingleCallCost = 10; // Library call cost. Make it expensive.
switch (IID) {
@ -896,7 +931,7 @@ public:
unsigned ScalarCalls = 1;
Type *ScalarRetTy = RetTy;
if (RetTy->isVectorTy()) {
if (ScalarizationCostPassed == UINT_MAX)
if (ScalarizationCostPassed == std::numeric_limits<unsigned>::max())
ScalarizationCost = getScalarizationOverhead(RetTy, true, false);
ScalarCalls = std::max(ScalarCalls, RetTy->getVectorNumElements());
ScalarRetTy = RetTy->getScalarType();
@ -905,7 +940,7 @@ public:
for (unsigned i = 0, ie = Tys.size(); i != ie; ++i) {
Type *Ty = Tys[i];
if (Ty->isVectorTy()) {
if (ScalarizationCostPassed == UINT_MAX)
if (ScalarizationCostPassed == std::numeric_limits<unsigned>::max())
ScalarizationCost += getScalarizationOverhead(Ty, false, true);
ScalarCalls = std::max(ScalarCalls, Ty->getVectorNumElements());
Ty = Ty->getScalarType();
@ -1054,8 +1089,10 @@ public:
// this will emit a costly libcall, adding call overhead and spills. Make it
// very expensive.
if (RetTy->isVectorTy()) {
unsigned ScalarizationCost = ((ScalarizationCostPassed != UINT_MAX) ?
ScalarizationCostPassed : getScalarizationOverhead(RetTy, true, false));
unsigned ScalarizationCost =
((ScalarizationCostPassed != std::numeric_limits<unsigned>::max())
? ScalarizationCostPassed
: getScalarizationOverhead(RetTy, true, false));
unsigned ScalarCalls = RetTy->getVectorNumElements();
SmallVector<Type *, 4> ScalarTys;
for (unsigned i = 0, ie = Tys.size(); i != ie; ++i) {
@ -1068,7 +1105,7 @@ public:
IID, RetTy->getScalarType(), ScalarTys, FMF);
for (unsigned i = 0, ie = Tys.size(); i != ie; ++i) {
if (Tys[i]->isVectorTy()) {
if (ScalarizationCostPassed == UINT_MAX)
if (ScalarizationCostPassed == std::numeric_limits<unsigned>::max())
ScalarizationCost += getScalarizationOverhead(Tys[i], false, true);
ScalarCalls = std::max(ScalarCalls, Tys[i]->getVectorNumElements());
}
@ -1245,7 +1282,8 @@ public:
/// \brief Concrete BasicTTIImpl that can be used if no further customization
/// is needed.
class BasicTTIImpl : public BasicTTIImplBase<BasicTTIImpl> {
typedef BasicTTIImplBase<BasicTTIImpl> BaseT;
using BaseT = BasicTTIImplBase<BasicTTIImpl>;
friend class BasicTTIImplBase<BasicTTIImpl>;
const TargetSubtargetInfo *ST;
@ -1258,6 +1296,6 @@ public:
explicit BasicTTIImpl(const TargetMachine *ST, const Function &F);
};
}
} // end namespace llvm
#endif
#endif // LLVM_CODEGEN_BASICTTIIMPL_H

20
include/llvm/CodeGen/CalcSpillWeights.h
View File

@ -1,4 +1,4 @@
//===---------------- lib/CodeGen/CalcSpillWeights.h ------------*- C++ -*-===//
//===- lib/CodeGen/CalcSpillWeights.h ---------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -7,7 +7,6 @@
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_CODEGEN_CALCSPILLWEIGHTS_H
#define LLVM_CODEGEN_CALCSPILLWEIGHTS_H
@ -16,11 +15,12 @@
namespace llvm {
class LiveInterval;
class LiveIntervals;
class MachineBlockFrequencyInfo;
class MachineLoopInfo;
class VirtRegMap;
class LiveInterval;
class LiveIntervals;
class MachineBlockFrequencyInfo;
class MachineFunction;
class MachineLoopInfo;
class VirtRegMap;
/// \brief Normalize the spill weight of a live interval
///
@ -32,7 +32,6 @@ namespace llvm {
/// per function call. Derived from block frequencies.
/// @param Size Size of live interval as returnexd by getSize()
/// @param NumInstr Number of instructions using this live interval
///
static inline float normalizeSpillWeight(float UseDefFreq, unsigned Size,
unsigned NumInstr) {
// The constant 25 instructions is added to avoid depending too much on
@ -47,7 +46,7 @@ namespace llvm {
/// spill weight and allocation hint.
class VirtRegAuxInfo {
public:
typedef float (*NormalizingFn)(float, unsigned, unsigned);
using NormalizingFn = float (*)(float, unsigned, unsigned);
private:
MachineFunction &MF;
@ -77,6 +76,7 @@ namespace llvm {
const MachineBlockFrequencyInfo &MBFI,
VirtRegAuxInfo::NormalizingFn norm =
normalizeSpillWeight);
}
} // end namespace llvm
#endif // LLVM_CODEGEN_CALCSPILLWEIGHTS_H

9
include/llvm/CodeGen/CallingConvLower.h
View File

@ -1,4 +1,4 @@
//===-- llvm/CallingConvLower.h - Calling Conventions -----------*- C++ -*-===//
//===- llvm/CallingConvLower.h - Calling Conventions ------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -23,6 +23,7 @@
#include "llvm/Target/TargetCallingConv.h"
namespace llvm {
class CCState;
class MVT;
class TargetMachine;
@ -503,7 +504,7 @@ public:
}
// Get list of pending assignments
SmallVectorImpl<llvm::CCValAssign> &getPendingLocs() {
SmallVectorImpl<CCValAssign> &getPendingLocs() {
return PendingLocs;
}
@ -564,8 +565,6 @@ private:
void MarkAllocated(unsigned Reg);
};
} // end namespace llvm
#endif
#endif // LLVM_CODEGEN_CALLINGCONVLOWER_H

3
include/llvm/CodeGen/GlobalISel/InstructionSelector.h
View File

@ -226,7 +226,7 @@ enum {
/// Provides the logic to select generic machine instructions.
class InstructionSelector {
public:
typedef bool(*ImmediatePredicateFn)(int64_t);
using ImmediatePredicateFn = bool (*)(int64_t);
virtual ~InstructionSelector() = default;
@ -240,7 +240,6 @@ public:
/// if returns true:
/// for I in all mutated/inserted instructions:
/// !isPreISelGenericOpcode(I.getOpcode())
///
virtual bool select(MachineInstr &I) const = 0;
protected:

54
lib/CodeGen/AggressiveAntiDepBreaker.cpp
View File

@ -1,4 +1,4 @@
//===----- AggressiveAntiDepBreaker.cpp - Anti-dep breaker ----------------===//
//===- AggressiveAntiDepBreaker.cpp - Anti-dep breaker --------------------===//
//
// The LLVM Compiler Infrastructure
//
@ -15,16 +15,33 @@
//===----------------------------------------------------------------------===//
#include "AggressiveAntiDepBreaker.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/iterator_range.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <map>
#include <set>
#include <utility>
#include <vector>
using namespace llvm;
#define DEBUG_TYPE "post-RA-sched"
@ -34,18 +51,17 @@ static cl::opt<int>
DebugDiv("agg-antidep-debugdiv",
cl::desc("Debug control for aggressive anti-dep breaker"),
cl::init(0), cl::Hidden);
static cl::opt<int>
DebugMod("agg-antidep-debugmod",
cl::desc("Debug control for aggressive anti-dep breaker"),
cl::init(0), cl::Hidden);
AggressiveAntiDepState::AggressiveAntiDepState(const unsigned TargetRegs,
MachineBasicBlock *BB) :
NumTargetRegs(TargetRegs), GroupNodes(TargetRegs, 0),
GroupNodeIndices(TargetRegs, 0),
KillIndices(TargetRegs, 0),
DefIndices(TargetRegs, 0)
{
MachineBasicBlock *BB)
: NumTargetRegs(TargetRegs), GroupNodes(TargetRegs, 0),
GroupNodeIndices(TargetRegs, 0), KillIndices(TargetRegs, 0),
DefIndices(TargetRegs, 0) {
const unsigned BBSize = BB->size();
for (unsigned i = 0; i < NumTargetRegs; ++i) {
// Initialize all registers to be in their own group. Initially we
@ -76,8 +92,7 @@ void AggressiveAntiDepState::GetGroupRegs(
}
}
unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2)
{
unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) {
assert(GroupNodes[0] == 0 && "GroupNode 0 not parent!");
assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
@ -92,8 +107,7 @@ unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2)
return Parent;
}
unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg)
{
unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) {
// Create a new GroupNode for Reg. Reg's existing GroupNode must
// stay as is because there could be other GroupNodes referring to
// it.
@ -103,8 +117,7 @@ unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg)
return idx;
}
bool AggressiveAntiDepState::IsLive(unsigned Reg)
{
bool AggressiveAntiDepState::IsLive(unsigned Reg) {
// KillIndex must be defined and DefIndex not defined for a register
// to be live.
return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u));
@ -115,8 +128,7 @@ AggressiveAntiDepBreaker::AggressiveAntiDepBreaker(
TargetSubtargetInfo::RegClassVector &CriticalPathRCs)
: AntiDepBreaker(), MF(MFi), MRI(MF.getRegInfo()),
TII(MF.getSubtarget().getInstrInfo()),
TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI),
State(nullptr) {
TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI) {
/* Collect a bitset of all registers that are only broken if they
are on the critical path. */
for (unsigned i = 0, e = CriticalPathRCs.size(); i < e; ++i) {
@ -250,7 +262,7 @@ void AggressiveAntiDepBreaker::GetPassthruRegs(
/// AntiDepEdges - Return in Edges the anti- and output- dependencies
/// in SU that we want to consider for breaking.
static void AntiDepEdges(const SUnit *SU, std::vector<const SDep*>& Edges) {
static void AntiDepEdges(const SUnit *SU, std::vector<const SDep *> &Edges) {
SmallSet<unsigned, 4> RegSet;
for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
P != PE; ++P) {
@ -544,8 +556,8 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
// break the anti-dependence.
std::vector<unsigned> Regs;
State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs);
assert(Regs.size() > 0 && "Empty register group!");
if (Regs.size() == 0)
assert(!Regs.empty() && "Empty register group!");
if (Regs.empty())
return false;
// Find the "superest" register in the group. At the same time,
@ -732,14 +744,12 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
/// BreakAntiDependencies - Identifiy anti-dependencies within the
/// ScheduleDAG and break them by renaming registers.
///
unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
const std::vector<SUnit>& SUnits,
const std::vector<SUnit> &SUnits,
MachineBasicBlock::iterator Begin,
MachineBasicBlock::iterator End,
unsigned InsertPosIndex,
DbgValueVector &DbgValues) {
std::vector<unsigned> &KillIndices = State->GetKillIndices();
std::vector<unsigned> &DefIndices = State->GetDefIndices();
std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&

43
lib/CodeGen/AggressiveAntiDepBreaker.h
View File

@ -1,4 +1,4 @@
//=- llvm/CodeGen/AggressiveAntiDepBreaker.h - Anti-Dep Support -*- C++ -*-=//
//==- llvm/CodeGen/AggressiveAntiDepBreaker.h - Anti-Dep Support -*- C++ -*-==//
//
// The LLVM Compiler Infrastructure
//
@ -19,29 +19,35 @@
#include "AntiDepBreaker.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <map>
#include <set>
#include <vector>
namespace llvm {
class MachineBasicBlock;
class MachineFunction;
class MachineInstr;
class MachineOperand;
class MachineRegisterInfo;
class RegisterClassInfo;
class TargetInstrInfo;
class TargetRegisterClass;
class TargetRegisterInfo;
/// Contains all the state necessary for anti-dep breaking.
class LLVM_LIBRARY_VISIBILITY AggressiveAntiDepState {
public:
/// Information about a register reference within a liverange
typedef struct {
struct RegisterReference {
/// The registers operand
MachineOperand *Operand;
/// The register class
const TargetRegisterClass *RC;
} RegisterReference;
};
private:
/// Number of non-virtual target registers (i.e. TRI->getNumRegs()).
@ -110,7 +116,7 @@ class LLVM_LIBRARY_VISIBILITY AggressiveAntiDepState {
class LLVM_LIBRARY_VISIBILITY AggressiveAntiDepBreaker
: public AntiDepBreaker {
MachineFunction& MF;
MachineFunction &MF;
MachineRegisterInfo &MRI;
const TargetInstrInfo *TII;
const TargetRegisterInfo *TRI;
@ -121,10 +127,10 @@ class LLVM_LIBRARY_VISIBILITY AggressiveAntiDepState {
BitVector CriticalPathSet;
/// The state used to identify and rename anti-dependence registers.
AggressiveAntiDepState *State;
AggressiveAntiDepState *State = nullptr;
public:
AggressiveAntiDepBreaker(MachineFunction& MFi,
AggressiveAntiDepBreaker(MachineFunction &MFi,
const RegisterClassInfo &RCI,
TargetSubtargetInfo::RegClassVector& CriticalPathRCs);
~AggressiveAntiDepBreaker() override;
@ -134,8 +140,7 @@ class LLVM_LIBRARY_VISIBILITY AggressiveAntiDepState {
/// Identifiy anti-dependencies along the critical path
/// of the ScheduleDAG and break them by renaming registers.
///
unsigned BreakAntiDependencies(const std::vector<SUnit>& SUnits,
unsigned BreakAntiDependencies(const std::vector<SUnit> &SUnits,
MachineBasicBlock::iterator Begin,
MachineBasicBlock::iterator End,
unsigned InsertPosIndex,
@ -143,7 +148,6 @@ class LLVM_LIBRARY_VISIBILITY AggressiveAntiDepState {
/// Update liveness information to account for the current
/// instruction, which will not be scheduled.
///
void Observe(MachineInstr &MI, unsigned Count,
unsigned InsertPosIndex) override;
@ -152,7 +156,7 @@ class LLVM_LIBRARY_VISIBILITY AggressiveAntiDepState {
private:
/// Keep track of a position in the allocation order for each regclass.
typedef std::map<const TargetRegisterClass *, unsigned> RenameOrderType;
using RenameOrderType = std::map<const TargetRegisterClass *, unsigned>;
/// Return true if MO represents a register
/// that is both implicitly used and defined in MI
@ -174,6 +178,7 @@ class LLVM_LIBRARY_VISIBILITY AggressiveAntiDepState {
RenameOrderType& RenameOrder,
std::map<unsigned, unsigned> &RenameMap);
};
}
#endif
} // end namespace llvm
#endif // LLVM_LIB_CODEGEN_AGGRESSIVEANTIDEPBREAKER_H

26
lib/CodeGen/AntiDepBreaker.h
View File

@ -1,4 +1,4 @@
//=- llvm/CodeGen/AntiDepBreaker.h - Anti-Dependence Breaking -*- C++ -*-=//
//===- llvm/CodeGen/AntiDepBreaker.h - Anti-Dependence Breaking -*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -15,12 +15,14 @@
#ifndef LLVM_LIB_CODEGEN_ANTIDEPBREAKER_H
#define LLVM_LIB_CODEGEN_ANTIDEPBREAKER_H
#include "llvm/ADT/iterator_range.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Support/Compiler.h"
#include <cassert>
#include <utility>
#include <vector>
namespace llvm {
@ -29,17 +31,17 @@ namespace llvm {
/// registers to break register anti-dependencies (WAR hazards).
class LLVM_LIBRARY_VISIBILITY AntiDepBreaker {
public:
typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
DbgValueVector;
using DbgValueVector =
std::vector<std::pair<MachineInstr *, MachineInstr *>>;
virtual ~AntiDepBreaker();
/// Initialize anti-dep breaking for a new basic block.
virtual void StartBlock(MachineBasicBlock *BB) =0;
virtual void StartBlock(MachineBasicBlock *BB) = 0;
/// Identifiy anti-dependencies within a basic-block region and break them by
/// renaming registers. Return the number of anti-dependencies broken.
virtual unsigned BreakAntiDependencies(const std::vector<SUnit>& SUnits,
virtual unsigned BreakAntiDependencies(const std::vector<SUnit> &SUnits,
MachineBasicBlock::iterator Begin,
MachineBasicBlock::iterator End,
unsigned InsertPosIndex,
@ -51,7 +53,7 @@ public:
unsigned InsertPosIndex) = 0;
/// Finish anti-dep breaking for a basic block.
virtual void FinishBlock() =0;
virtual void FinishBlock() = 0;
/// Update DBG_VALUE if dependency breaker is updating
/// other machine instruction to use NewReg.
@ -81,6 +83,6 @@ public:
}
};
}
} // end namespace llvm
#endif
#endif // LLVM_LIB_CODEGEN_ANTIDEPBREAKER_H

15
lib/CodeGen/BasicTargetTransformInfo.cpp
View File

@ -15,21 +15,20 @@
///
//===----------------------------------------------------------------------===//
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/Analysis/TargetTransformInfoImpl.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/IR/Function.h"
#include "llvm/Support/CommandLine.h"
#include <utility>
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
// This flag is used by the template base class for BasicTTIImpl, and here to
// provide a definition.
cl::opt<unsigned>
llvm::PartialUnrollingThreshold("partial-unrolling-threshold", cl::init(0),
cl::desc("Threshold for partial unrolling"),
cl::Hidden);
llvm::PartialUnrollingThreshold("partial-unrolling-threshold", cl::init(0),
cl::desc("Threshold for partial unrolling"),
cl::Hidden);
BasicTTIImpl::BasicTTIImpl(const TargetMachine *TM, const Function &F)
: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),

10
lib/CodeGen/CalcSpillWeights.cpp
View File

@ -1,4 +1,4 @@
//===------------------------ CalcSpillWeights.cpp ------------------------===//
//===- CalcSpillWeights.cpp -----------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@ -8,10 +8,13 @@
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/CalcSpillWeights.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/Support/Debug.h"
@ -19,6 +22,9 @@
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <tuple>
using namespace llvm;
#define DEBUG_TYPE "calcspillweights"

32
lib/CodeGen/CriticalAntiDepBreaker.cpp
View File

@ -1,4 +1,4 @@
//===----- CriticalAntiDepBreaker.cpp - Anti-dep breaker -------- ---------===//
//===- CriticalAntiDepBreaker.cpp - Anti-dep breaker ----------------------===//
//
// The LLVM Compiler Infrastructure
//
@ -14,14 +14,29 @@
//===----------------------------------------------------------------------===//
#include "CriticalAntiDepBreaker.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <map>
#include <utility>
#include <vector>
using namespace llvm;
@ -35,8 +50,7 @@ CriticalAntiDepBreaker::CriticalAntiDepBreaker(MachineFunction &MFi,
Classes(TRI->getNumRegs(), nullptr), KillIndices(TRI->getNumRegs(), 0),
DefIndices(TRI->getNumRegs(), 0), KeepRegs(TRI->getNumRegs(), false) {}
CriticalAntiDepBreaker::~CriticalAntiDepBreaker() {
}
CriticalAntiDepBreaker::~CriticalAntiDepBreaker() = default;
void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
const unsigned BBSize = BB->size();
@ -333,8 +347,7 @@ void CriticalAntiDepBreaker::ScanInstruction(MachineInstr &MI, unsigned Count) {
bool
CriticalAntiDepBreaker::isNewRegClobberedByRefs(RegRefIter RegRefBegin,
RegRefIter RegRefEnd,
unsigned NewReg)
{
unsigned NewReg) {
for (RegRefIter I = RegRefBegin; I != RegRefEnd; ++I ) {
MachineOperand *RefOper = I->second;
@ -381,8 +394,7 @@ findSuitableFreeRegister(RegRefIter RegRefBegin,
unsigned AntiDepReg,
unsigned LastNewReg,
const TargetRegisterClass *RC,
SmallVectorImpl<unsigned> &Forbid)
{
SmallVectorImpl<unsigned> &Forbid) {
ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC);
for (unsigned i = 0; i != Order.size(); ++i) {
unsigned NewReg = Order[i];
@ -423,7 +435,7 @@ findSuitableFreeRegister(RegRefIter RegRefBegin,
}
unsigned CriticalAntiDepBreaker::
BreakAntiDependencies(const std::vector<SUnit>& SUnits,
BreakAntiDependencies(const std::vector<SUnit> &SUnits,
MachineBasicBlock::iterator Begin,
MachineBasicBlock::iterator End,
unsigned InsertPosIndex,
@ -436,7 +448,7 @@ BreakAntiDependencies(const std::vector<SUnit>& SUnits,
// This is used for updating debug information.
//
// FIXME: Replace this with the existing map in ScheduleDAGInstrs::MISUnitMap
DenseMap<MachineInstr*,const SUnit*> MISUnitMap;
DenseMap<MachineInstr *, const SUnit *> MISUnitMap;
// Find the node at the bottom of the critical path.
const SUnit *Max = nullptr;

33
lib/CodeGen/CriticalAntiDepBreaker.h
View File

@ -1,4 +1,4 @@
//=- llvm/CodeGen/CriticalAntiDepBreaker.h - Anti-Dep Support -*- C++ -*-=//
//===- llvm/CodeGen/CriticalAntiDepBreaker.h - Anti-Dep Support -*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -18,16 +18,21 @@
#include "AntiDepBreaker.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/Support/Compiler.h"
#include <map>
#include <vector>
namespace llvm {
class MachineBasicBlock;
class MachineFunction;
class MachineInstr;
class MachineOperand;
class MachineRegisterInfo;
class RegisterClassInfo;
class TargetInstrInfo;
class TargetRegisterClass;
class TargetRegisterInfo;
class MachineFunction;
class LLVM_LIBRARY_VISIBILITY CriticalAntiDepBreaker : public AntiDepBreaker {
MachineFunction& MF;
@ -46,12 +51,13 @@ class LLVM_LIBRARY_VISIBILITY CriticalAntiDepBreaker : public AntiDepBreaker {
/// corresponding value is null. If the register is live but used in
/// multiple register classes, the corresponding value is -1 casted to a
/// pointer.
std::vector<const TargetRegisterClass*> Classes;
std::vector<const TargetRegisterClass *> Classes;
/// Map registers to all their references within a live range.
std::multimap<unsigned, MachineOperand *> RegRefs;
typedef std::multimap<unsigned, MachineOperand *>::const_iterator
RegRefIter;
using RegRefIter =
std::multimap<unsigned, MachineOperand *>::const_iterator;
/// The index of the most recent kill (proceeding bottom-up),
/// or ~0u if the register is not live.
@ -66,7 +72,7 @@ class LLVM_LIBRARY_VISIBILITY CriticalAntiDepBreaker : public AntiDepBreaker {
BitVector KeepRegs;
public:
CriticalAntiDepBreaker(MachineFunction& MFi, const RegisterClassInfo&);
CriticalAntiDepBreaker(MachineFunction& MFi, const RegisterClassInfo &RCI);
~CriticalAntiDepBreaker() override;
/// Initialize anti-dep breaking for a new basic block.
@ -74,7 +80,7 @@ class LLVM_LIBRARY_VISIBILITY CriticalAntiDepBreaker : public AntiDepBreaker {
/// Identifiy anti-dependencies along the critical path
/// of the ScheduleDAG and break them by renaming registers.
unsigned BreakAntiDependencies(const std::vector<SUnit>& SUnits,
unsigned BreakAntiDependencies(const std::vector<SUnit> &SUnits,
MachineBasicBlock::iterator Begin,
MachineBasicBlock::iterator End,
unsigned InsertPosIndex,
@ -101,6 +107,7 @@ class LLVM_LIBRARY_VISIBILITY CriticalAntiDepBreaker : public AntiDepBreaker {
const TargetRegisterClass *RC,
SmallVectorImpl<unsigned> &Forbid);
};
}
#endif
} // end namespace llvm
#endif // LLVM_LIB_CODEGEN_CRITICALANTIDEPBREAKER_H

6
lib/CodeGen/GlobalISel/InstructionSelector.cpp
View File

@ -6,8 +6,10 @@
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
/// \file
/// This file implements the InstructionSelector class.
//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
@ -16,11 +18,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/IR/Constants.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetRegisterInfo.h"

77
lib/CodeGen/StackColoring.cpp
View File

@ -1,4 +1,4 @@
//===-- StackColoring.cpp -------------------------------------------------===//
//===- StackColoring.cpp --------------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@ -22,35 +22,44 @@
//===----------------------------------------------------------------------===//
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/DepthFirstIterator.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/StackProtector.h"
#include "llvm/CodeGen/WinEHFuncInfo.h"
#include "llvm/IR/DebugInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/Metadata.h"
#include "llvm/IR/Use.h"
#include "llvm/IR/Value.h"
#include "llvm/Pass.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetOpcodes.h"
#include <algorithm>
#include <cassert>
#include <limits>
#include <memory>
#include <utility>
using namespace llvm;
@ -366,6 +375,7 @@ STATISTIC(EscapedAllocas, "Number of allocas that escaped the lifetime region");
//
namespace {
/// StackColoring - A machine pass for merging disjoint stack allocations,
/// marked by the LIFETIME_START and LIFETIME_END pseudo instructions.
class StackColoring : public MachineFunctionPass {
@ -378,32 +388,40 @@ class StackColoring : public MachineFunctionPass {
struct BlockLifetimeInfo {
/// Which slots BEGINs in each basic block.
BitVector Begin;
/// Which slots ENDs in each basic block.
BitVector End;
/// Which slots are marked as LIVE_IN, coming into each basic block.
BitVector LiveIn;
/// Which slots are marked as LIVE_OUT, coming out of each basic block.
BitVector LiveOut;
};
/// Maps active slots (per bit) for each basic block.
typedef DenseMap<const MachineBasicBlock*, BlockLifetimeInfo> LivenessMap;
using LivenessMap = DenseMap<const MachineBasicBlock *, BlockLifetimeInfo>;
LivenessMap BlockLiveness;
/// Maps serial numbers to basic blocks.
DenseMap<const MachineBasicBlock*, int> BasicBlocks;
DenseMap<const MachineBasicBlock *, int> BasicBlocks;
/// Maps basic blocks to a serial number.
SmallVector<const MachineBasicBlock*, 8> BasicBlockNumbering;
SmallVector<const MachineBasicBlock *, 8> BasicBlockNumbering;
/// Maps slots to their use interval. Outside of this interval, slots
/// values are either dead or `undef` and they will not be written to.
SmallVector<std::unique_ptr<LiveInterval>, 16> Intervals;
/// Maps slots to the points where they can become in-use.
SmallVector<SmallVector<SlotIndex, 4>, 16> LiveStarts;
/// VNInfo is used for the construction of LiveIntervals.
VNInfo::Allocator VNInfoAllocator;
/// SlotIndex analysis object.
SlotIndexes *Indexes;
/// The stack protector object.
StackProtector *SP;
@ -424,13 +442,18 @@ class StackColoring : public MachineFunctionPass {
public:
static char ID;
StackColoring() : MachineFunctionPass(ID) {
initializeStackColoringPass(*PassRegistry::getPassRegistry());
}
void getAnalysisUsage(AnalysisUsage &AU) const override;
bool runOnMachineFunction(MachineFunction &MF) override;
private:
/// Used in collectMarkers
using BlockBitVecMap = DenseMap<const MachineBasicBlock *, BitVector>;
/// Debug.
void dump() const;
void dumpIntervals() const;
@ -489,13 +512,12 @@ private:
/// Map entries which point to other entries to their destination.
/// A->B->C becomes A->C.
void expungeSlotMap(DenseMap<int, int> &SlotRemap, unsigned NumSlots);
/// Used in collectMarkers
typedef DenseMap<const MachineBasicBlock*, BitVector> BlockBitVecMap;
};
} // end anonymous namespace
char StackColoring::ID = 0;
char &llvm::StackColoringID = StackColoring::ID;
INITIALIZE_PASS_BEGIN(StackColoring, DEBUG_TYPE,
@ -559,16 +581,13 @@ static inline int getStartOrEndSlot(const MachineInstr &MI)
return -1;
}
//
// At the moment the only way to end a variable lifetime is with
// a VARIABLE_LIFETIME op (which can't contain a start). If things
// change and the IR allows for a single inst that both begins
// and ends lifetime(s), this interface will need to be reworked.
//
bool StackColoring::isLifetimeStartOrEnd(const MachineInstr &MI,
SmallVector<int, 4> &slots,
bool &isStart)
{
bool &isStart) {
if (MI.getOpcode() == TargetOpcode::LIFETIME_START ||
MI.getOpcode() == TargetOpcode::LIFETIME_END) {
int Slot = getStartOrEndSlot(MI);
@ -608,8 +627,7 @@ bool StackColoring::isLifetimeStartOrEnd(const MachineInstr &MI,
return false;
}
unsigned StackColoring::collectMarkers(unsigned NumSlot)
{
unsigned StackColoring::collectMarkers(unsigned NumSlot) {
unsigned MarkersFound = 0;
BlockBitVecMap SeenStartMap;
InterestingSlots.clear();
@ -624,7 +642,6 @@ unsigned StackColoring::collectMarkers(unsigned NumSlot)
// Step 1: collect markers and populate the "InterestingSlots"
// and "ConservativeSlots" sets.
for (MachineBasicBlock *MBB : depth_first(MF)) {
// Compute the set of slots for which we've seen a START marker but have
// not yet seen an END marker at this point in the walk (e.g. on entry
// to this bb).
@ -697,7 +714,6 @@ unsigned StackColoring::collectMarkers(unsigned NumSlot)
// NOTE: We use a depth-first iteration to ensure that we obtain a
// deterministic numbering.
for (MachineBasicBlock *MBB : depth_first(MF)) {
// Assign a serial number to this basic block.
BasicBlocks[MBB] = BasicBlockNumbering.size();
BasicBlockNumbering.push_back(MBB);
@ -745,8 +761,7 @@ unsigned StackColoring::collectMarkers(unsigned NumSlot)
return MarkersFound;
}
void StackColoring::calculateLocalLiveness()
{
void StackColoring::calculateLocalLiveness() {
unsigned NumIters = 0;
bool changed = true;
while (changed) {
@ -754,7 +769,6 @@ void StackColoring::calculateLocalLiveness()
++NumIters;
for (const MachineBasicBlock *BB : BasicBlockNumbering) {
// Use an iterator to avoid repeated lookups.
LivenessMap::iterator BI = BlockLiveness.find(BB);
assert(BI != BlockLiveness.end() && "Block not found");
@ -792,7 +806,7 @@ void StackColoring::calculateLocalLiveness()
BlockInfo.LiveOut |= LocalLiveOut;
}
}
}// while changed.
} // while changed.
NumIterations = NumIters;
}
@ -818,7 +832,6 @@ void StackColoring::calculateLiveIntervals(unsigned NumSlots) {
// Create the interval for the basic blocks containing lifetime begin/end.
for (const MachineInstr &MI : MBB) {
SmallVector<int, 4> slots;
bool IsStart = false;
if (!isLifetimeStartOrEnd(MI, slots, IsStart))
@ -1047,7 +1060,7 @@ void StackColoring::remapInstructions(DenseMap<int, int> &SlotRemap) {
if (WinEHFuncInfo *EHInfo = MF->getWinEHFuncInfo())
for (WinEHTryBlockMapEntry &TBME : EHInfo->TryBlockMap)
for (WinEHHandlerType &H : TBME.HandlerArray)
if (H.CatchObj.FrameIndex != INT_MAX &&
if (H.CatchObj.FrameIndex != std::numeric_limits<int>::max() &&
SlotRemap.count(H.CatchObj.FrameIndex))
H.CatchObj.FrameIndex = SlotRemap[H.CatchObj.FrameIndex];
@ -1231,7 +1244,7 @@ bool StackColoring::runOnMachineFunction(MachineFunction &Func) {
LiveInterval *Second = &*Intervals[SecondSlot];
auto &FirstS = LiveStarts[FirstSlot];
auto &SecondS = LiveStarts[SecondSlot];
assert (!First->empty() && !Second->empty() && "Found an empty range");
assert(!First->empty() && !Second->empty() && "Found an empty range");
// Merge disjoint slots. This is a little bit tricky - see the
// Implementation Notes section for an explanation.

45
lib/CodeGen/TwoAddressInstructionPass.cpp
View File

@ -1,4 +1,4 @@
//===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
//===- TwoAddressInstructionPass.cpp - Two-Address instruction pass -------===//
//
// The LLVM Compiler Infrastructure
//
@ -28,27 +28,40 @@
//===----------------------------------------------------------------------===//
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/iterator_range.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/IR/Function.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/Pass.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <iterator>
#include <utility>
using namespace llvm;
@ -76,6 +89,7 @@ static cl::opt<unsigned> MaxDataFlowEdge(
"the benefit of commuting operands"));
namespace {
class TwoAddressInstructionPass : public MachineFunctionPass {
MachineFunction *MF;
const TargetInstrInfo *TII;
@ -148,14 +162,16 @@ class TwoAddressInstructionPass : public MachineFunctionPass {
void processCopy(MachineInstr *MI);
typedef SmallVector<std::pair<unsigned, unsigned>, 4> TiedPairList;
typedef SmallDenseMap<unsigned, TiedPairList> TiedOperandMap;
using TiedPairList = SmallVector<std::pair<unsigned, unsigned>, 4>;
using TiedOperandMap = SmallDenseMap<unsigned, TiedPairList>;
bool collectTiedOperands(MachineInstr *MI, TiedOperandMap&);
void processTiedPairs(MachineInstr *MI, TiedPairList&, unsigned &Dist);
void eliminateRegSequence(MachineBasicBlock::iterator&);
public:
static char ID; // Pass identification, replacement for typeid
TwoAddressInstructionPass() : MachineFunctionPass(ID) {
initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry());
}
@ -175,17 +191,19 @@ public:
/// Pass entry point.
bool runOnMachineFunction(MachineFunction&) override;
};
} // end anonymous namespace
char TwoAddressInstructionPass::ID = 0;
char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID;
INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, DEBUG_TYPE,
"Two-Address instruction pass", false, false)
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
INITIALIZE_PASS_END(TwoAddressInstructionPass, DEBUG_TYPE,
"Two-Address instruction pass", false, false)
char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID;
static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS);
/// A two-address instruction has been converted to a three-address instruction
@ -267,7 +285,7 @@ sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg,
++KillPos;
unsigned NumVisited = 0;
for (MachineInstr &OtherMI : llvm::make_range(std::next(OldPos), KillPos)) {
for (MachineInstr &OtherMI : make_range(std::next(OldPos), KillPos)) {
// DBG_VALUE cannot be counted against the limit.
if (OtherMI.isDebugValue())
continue;
@ -452,7 +470,7 @@ static bool isKilled(MachineInstr &MI, unsigned Reg,
LiveIntervals *LIS,
bool allowFalsePositives) {
MachineInstr *DefMI = &MI;
for (;;) {
while (true) {
// All uses of physical registers are likely to be kills.
if (TargetRegisterInfo::isPhysicalRegister(Reg) &&
(allowFalsePositives || MRI->hasOneUse(Reg)))
@ -904,7 +922,6 @@ rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
// Move the copies connected to MI down as well.
MachineBasicBlock::iterator Begin = MI;
MachineBasicBlock::iterator AfterMI = std::next(Begin);
MachineBasicBlock::iterator End = AfterMI;
while (End->isCopy() &&
regOverlapsSet(Defs, End->getOperand(1).getReg(), TRI)) {
@ -916,7 +933,7 @@ rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
unsigned NumVisited = 0;
MachineBasicBlock::iterator KillPos = KillMI;
++KillPos;
for (MachineInstr &OtherMI : llvm::make_range(End, KillPos)) {
for (MachineInstr &OtherMI : make_range(End, KillPos)) {
// DBG_VALUE cannot be counted against the limit.
if (OtherMI.isDebugValue())
continue;
@ -1090,7 +1107,7 @@ rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
// Check if the reschedule will not break depedencies.
unsigned NumVisited = 0;
for (MachineInstr &OtherMI :
llvm::make_range(mi, MachineBasicBlock::iterator(KillMI))) {
make_range(mi, MachineBasicBlock::iterator(KillMI))) {
// DBG_VALUE cannot be counted against the limit.
if (OtherMI.isDebugValue())
continue;
@ -1609,7 +1626,6 @@ TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI,
if (I->end == UseIdx)
LI.removeSegment(LastCopyIdx, UseIdx);
}
} else if (RemovedKillFlag) {
// Some tied uses of regB matched their destination registers, so
// regB is still used in this instruction, but a kill flag was
@ -1690,7 +1706,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
// transformations that may either eliminate the tied operands or
// improve the opportunities for coalescing away the register copy.
if (TiedOperands.size() == 1) {
SmallVectorImpl<std::pair<unsigned, unsigned> > &TiedPairs
SmallVectorImpl<std::pair<unsigned, unsigned>> &TiedPairs
= TiedOperands.begin()->second;
if (TiedPairs.size() == 1) {
unsigned SrcIdx = TiedPairs[0].first;
@ -1751,7 +1767,6 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
///
/// %dst:ssub0<def,undef> = COPY %v1
/// %dst:ssub1<def> = COPY %v2
///
void TwoAddressInstructionPass::
eliminateRegSequence(MachineBasicBlock::iterator &MBBI) {
MachineInstr &MI = *MBBI;