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Allow CP10/CP11 operations on ARMv5/v6

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Those registers are VFP/NEON and vector instructions should be used instead,
but old cores rely on those co-processors to enable VFP unwinding. This change
was prompted by the libc++abi's unwinding routine and is also present in many
legacy low-level bare-metal code that we ought to compile/assemble.

Fixing bug PR20025 and allowing PR20529 to proceed with a fix in libc++abi.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214802 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Renato Golin 2014-08-04 23:21:56 +00:00
parent 84fef1f55d
commit 94a1af55ba
1 changed files with 7 additions and 3 deletions
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10
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -3118,9 +3118,10 @@ static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
return -1;
switch (Name[1]) {
default: return -1;
// p10 and p11 are invalid for coproc instructions (reserved for FP/NEON)
case '0': return CoprocOp == 'p'? -1: 10;
case '1': return CoprocOp == 'p'? -1: 11;
// CP10 and CP11 are VFP/NEON and so vector instructions should be used.
// However, old cores (v5/v6) did use them in that way.
case '0': return 10;
case '1': return 11;
case '2': return 12;
case '3': return 13;
case '4': return 14;
@ -3177,6 +3178,9 @@ ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
if (Num == -1)
return MatchOperand_NoMatch;
// ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions
if ((hasV7Ops() || hasV8Ops()) && (Num == 10 || Num == 11))
return MatchOperand_NoMatch;
Parser.Lex(); // Eat identifier token.
Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));