mirror of
https://github.com/RPCS3/llvm.git
synced 2024-12-16 00:17:32 +00:00
- Clean up interface to Sparc register handling a bit:
- Eliminate Sparc*Order classes, moving contents to Sparc*Class classes
- get register name methods now return const char * const pointers instead
of std::string's.
- Added file header comments to SparcRegClassInfo.(cpp|h)
- Moved BIG constant arrays out of SparcRegClassInfo.h, into
SparcRegInfo.cpp. This should allow a LOT of std::string constructors to
not have to be called.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3295 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
6ef3369321
commit
9568568b75
@ -419,7 +419,7 @@ public:
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// Returns the assembly-language name of the specified machine register.
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//
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virtual const std::string getUnifiedRegName(int reg) const;
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virtual const char * const getUnifiedRegName(int reg) const;
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// returns the # of bytes of stack space allocated for each register
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@ -89,7 +89,7 @@ void InsertPrologEpilogCode::InsertPrologCode(Function &F)
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int32_t C = - (int) staticStackSize;
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int uregNum = Target.getRegInfo().getUnifiedRegNum(
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Target.getRegInfo().getRegClassIDOfType(Type::IntTy),
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SparcIntRegOrder::l0);
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SparcIntRegClass::l0);
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M = new MachineInstr(SETHI);
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M->SetMachineOperandConst(0, MachineOperand::MO_SignExtendedImmed, C);
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@ -1,8 +1,13 @@
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//===-- SparcRegClassInfo.cpp - Register class def'ns for Sparc -----------===//
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//
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// This file defines the register classes used by the Sparc target description.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcRegClassInfo.h"
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#include "llvm/CodeGen/RegAllocCommon.h"
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#include "llvm/Target/Sparc.h"
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#include "llvm/Type.h"
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#include <iostream>
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using std::cerr;
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using std::vector;
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@ -61,17 +66,17 @@ void SparcIntRegClass::colorIGNode(IGNode * Node, vector<bool> &IsColorUsedArr)
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if( ! LR->isCallInterference() ) {
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// start with volatiles (we can allocate volatiles safely)
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SearchStart = SparcIntRegOrder::StartOfAllRegs;
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SearchStart = SparcIntRegClass::StartOfAllRegs;
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}
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else {
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// start with non volatiles (no non-volatiles)
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SearchStart = SparcIntRegOrder::StartOfNonVolatileRegs;
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SearchStart = SparcIntRegClass::StartOfNonVolatileRegs;
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}
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unsigned c=0; // color
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// find first unused color
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for( c=SearchStart; c < SparcIntRegOrder::NumOfAvailRegs; c++) {
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for( c=SearchStart; c < SparcIntRegClass::NumOfAvailRegs; c++) {
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if(!IsColorUsedArr[c] ) { ColorFound = true; break; }
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}
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@ -86,10 +91,10 @@ void SparcIntRegClass::colorIGNode(IGNode * Node, vector<bool> &IsColorUsedArr)
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else if( LR->isCallInterference() )
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{
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// start from 0 - try to find even a volatile this time
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SearchStart = SparcIntRegOrder::StartOfAllRegs;
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SearchStart = SparcIntRegClass::StartOfAllRegs;
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// find first unused volatile color
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for(c=SearchStart; c < SparcIntRegOrder::StartOfNonVolatileRegs; c++) {
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for(c=SearchStart; c < SparcIntRegClass::StartOfNonVolatileRegs; c++) {
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if( ! IsColorUsedArr[ c ] ) { ColorFound = true; break; }
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}
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@ -200,11 +205,11 @@ void SparcFloatRegClass::colorIGNode(IGNode * Node,
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//if this Node is between calls (i.e., no call interferences )
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if( ! isCallInterf ) {
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// start with volatiles (we can allocate volatiles safely)
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SearchStart = SparcFloatRegOrder::StartOfAllRegs;
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SearchStart = SparcFloatRegClass::StartOfAllRegs;
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}
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else {
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// start with non volatiles (no non-volatiles)
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SearchStart = SparcFloatRegOrder::StartOfNonVolatileRegs;
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SearchStart = SparcFloatRegClass::StartOfNonVolatileRegs;
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}
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ColorFound = findFloatColor( LR, SearchStart, 32, IsColorUsedArr );
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@ -222,8 +227,8 @@ void SparcFloatRegClass::colorIGNode(IGNode * Node,
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// color could be found.
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// Now try to allocate even a volatile color
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ColorFound = findFloatColor( LR, SparcFloatRegOrder::StartOfAllRegs,
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SparcFloatRegOrder::StartOfNonVolatileRegs,
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ColorFound = findFloatColor( LR, SparcFloatRegClass::StartOfAllRegs,
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SparcFloatRegClass::StartOfNonVolatileRegs,
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IsColorUsedArr);
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}
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@ -1,12 +1,11 @@
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/* Title: SparcRegClassInfo.h -*- C++ -*-
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Author: Ruchira Sasanka
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Date: Aug 20, 01
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Purpose: Contains the description of integer register class of Sparc
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*/
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//===-- SparcRegClassInfo.h - Register class def'ns for Sparc ----*- C++ -*--=//
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//
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// This file defines the register classes used by the Sparc target description.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SPARC_REG_INFO_CLASS_H
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#define SPARC_REG_INFO_CLASS_H
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#ifndef SPARC_REG_CLASS_INFO_H
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#define SPARC_REG_CLASS_INFO_H
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#include "llvm/Target/MachineRegInfo.h"
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#include "llvm/CodeGen/IGNode.h"
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@ -15,21 +14,18 @@
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// Integer Register Class
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//-----------------------------------------------------------------------------
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// Int register names in same order as enum in class SparcIntRegOrder
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static const std::string IntRegNames[] = {
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"o0", "o1", "o2", "o3", "o4", "o5", "o7",
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"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
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"i0", "i1", "i2", "i3", "i4", "i5",
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"i6", "i7",
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"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
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"o6"
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};
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struct SparcIntRegClass : public MachineRegClassInfo {
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SparcIntRegClass(unsigned ID)
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: MachineRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) { }
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void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const;
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inline bool isRegVolatile(int Reg) const {
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return (Reg < (int)StartOfNonVolatileRegs);
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}
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struct SparcIntRegOrder {
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enum RegsInPrefOrder { // colors possible for a LR (in preferred order)
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enum { // colors possible for a LR (in preferred order)
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// --- following colors are volatile across function calls
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// %g0 can't be used for coloring - always 0
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o0, o1, o2, o3, o4, o5, o7, // %o0-%o5,
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@ -49,7 +45,9 @@ struct SparcIntRegOrder {
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// --- following colors are not available for allocation within this phase
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// --- but can appear for pre-colored ranges
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i6, i7, g0, g1, g2, g3, g4, g5, g6, g7, o6
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i6, i7, g0, g1, g2, g3, g4, g5, g6, g7, o6,
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NumOfAllRegs, // Must be first AFTER registers...
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//*** NOTE: If we decide to use some %g regs, they are volatile
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// (see sparc64ABI)
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@ -57,36 +55,15 @@ struct SparcIntRegOrder {
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// enumeration of %o0 (change StartOfAllRegs below)
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// change isRegVloatile method below
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// Also change IntRegNames above.
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// max # of colors reg coloring can allocate
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NumOfAvailRegs = i6,
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StartOfNonVolatileRegs = l0,
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StartOfAllRegs = o0,
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};
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// max # of colors reg coloring can allocate
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static unsigned int const NumOfAvailRegs = i6;
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static unsigned int const StartOfNonVolatileRegs = l0;
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static unsigned int const StartOfAllRegs = o0;
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static unsigned int const NumOfAllRegs = o6 + 1;
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static const std::string getRegName(unsigned reg) {
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assert( reg < NumOfAllRegs );
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return IntRegNames[reg];
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}
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};
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struct SparcIntRegClass : public MachineRegClassInfo {
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SparcIntRegClass(unsigned ID)
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: MachineRegClassInfo(ID,
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SparcIntRegOrder::NumOfAvailRegs,
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SparcIntRegOrder::NumOfAllRegs) { }
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void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const;
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inline bool isRegVolatile(int Reg) const {
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return (Reg < (int) SparcIntRegOrder::StartOfNonVolatileRegs);
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}
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static const char * const getRegName(unsigned reg);
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};
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@ -96,65 +73,38 @@ struct SparcIntRegClass : public MachineRegClassInfo {
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// Float Register Class
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//-----------------------------------------------------------------------------
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static const std::string FloatRegNames[] =
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{
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"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
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"f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
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"f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
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"f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
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"f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49",
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"f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59",
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"f60", "f61", "f62", "f63"
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};
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class SparcFloatRegClass : public MachineRegClassInfo {
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int findFloatColor(const LiveRange *LR, unsigned Start,
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unsigned End, std::vector<bool> &IsColorUsedArr) const;
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public:
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SparcFloatRegClass(unsigned ID)
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: MachineRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) {}
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void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const;
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class SparcFloatRegOrder{
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public:
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enum RegsInPrefOrder {
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// according to Sparc 64 ABI, all %fp regs are volatile
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inline bool isRegVolatile(int Reg) const { return true; }
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enum {
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f0, f1, f2, f3, f4, f5, f6, f7, f8, f9,
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f10, f11, f12, f13, f14, f15, f16, f17, f18, f19,
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f20, f21, f22, f23, f24, f25, f26, f27, f28, f29,
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f30, f31, f32, f33, f34, f35, f36, f37, f38, f39,
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f40, f41, f42, f43, f44, f45, f46, f47, f48, f49,
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f50, f51, f52, f53, f54, f55, f56, f57, f58, f59,
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f60, f61, f62, f63
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f60, f61, f62, f63,
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// there are 64 regs alltogether but only 32 regs can be allocated at
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// a time.
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//
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NumOfAvailRegs = 32,
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NumOfAllRegs = 64,
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StartOfNonVolatileRegs = f32,
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StartOfAllRegs = f0,
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};
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// there are 64 regs alltogether but only 32 regs can be allocated at
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// a time.
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static unsigned int const NumOfAvailRegs = 32;
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static unsigned int const NumOfAllRegs = 64;
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static unsigned int const StartOfNonVolatileRegs = f32;
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static unsigned int const StartOfAllRegs = f0;
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static const std::string getRegName(unsigned reg) {
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assert (reg < NumOfAllRegs);
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return FloatRegNames[reg];
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}
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};
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class SparcFloatRegClass : public MachineRegClassInfo {
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int findFloatColor(const LiveRange *LR, unsigned Start,
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unsigned End, std::vector<bool> &IsColorUsedArr) const;
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public:
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SparcFloatRegClass(unsigned ID)
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: MachineRegClassInfo(ID,
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SparcFloatRegOrder::NumOfAvailRegs,
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SparcFloatRegOrder::NumOfAllRegs) {}
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void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const;
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// according to Sparc 64 ABI, all %fp regs are volatile
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inline bool isRegVolatile(int Reg) const { return true; }
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static const char * const getRegName(unsigned reg);
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};
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@ -169,25 +119,6 @@ public:
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// allocated for two names.
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//-----------------------------------------------------------------------------
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static const std::string IntCCRegNames[] = {
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"xcc", "ccr"
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};
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struct SparcIntCCRegOrder {
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enum RegsInPrefOrder {
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xcc, ccr // only one is available - see the note above
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};
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static const std::string getRegName(unsigned reg) {
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assert(reg < 2);
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return IntCCRegNames[reg];
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}
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};
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struct SparcIntCCRegClass : public MachineRegClassInfo {
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SparcIntCCRegClass(unsigned ID)
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: MachineRegClassInfo(ID, 1, 2) { }
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@ -202,6 +133,12 @@ struct SparcIntCCRegClass : public MachineRegClassInfo {
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// according to Sparc 64 ABI, %ccr is volatile
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//
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inline bool isRegVolatile(int Reg) const { return true; }
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enum {
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xcc, ccr // only one is available - see the note above
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};
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static const char * const getRegName(unsigned reg);
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};
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@ -212,21 +149,6 @@ struct SparcIntCCRegClass : public MachineRegClassInfo {
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// Only 4 Float CC registers are available
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//-----------------------------------------------------------------------------
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static const std::string FloatCCRegNames[] = {
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"fcc0", "fcc1", "fcc2", "fcc3"
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};
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struct SparcFloatCCRegOrder{
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enum RegsInPrefOrder {
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fcc0, fcc1, fcc2, fcc3
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};
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static const std::string getRegName(unsigned reg) {
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assert (reg < 4);
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return FloatCCRegNames[reg];
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}
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};
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struct SparcFloatCCRegClass : public MachineRegClassInfo {
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SparcFloatCCRegClass(unsigned ID)
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: MachineRegClassInfo(ID, 4, 4) { }
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@ -244,6 +166,12 @@ struct SparcFloatCCRegClass : public MachineRegClassInfo {
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// according to Sparc 64 ABI, all %fp CC regs are volatile
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//
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inline bool isRegVolatile(int Reg) const { return true; }
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enum {
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fcc0, fcc1, fcc2, fcc3
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};
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static const char * const getRegName(unsigned reg);
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};
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#endif
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@ -34,7 +34,7 @@ UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
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MachineRegClassArr.push_back(new SparcIntCCRegClass(IntCCRegClassID));
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MachineRegClassArr.push_back(new SparcFloatCCRegClass(FloatCCRegClassID));
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assert(SparcFloatRegOrder::StartOfNonVolatileRegs == 32 &&
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assert(SparcFloatRegClass::StartOfNonVolatileRegs == 32 &&
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"32 Float regs are used for float arg passing");
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}
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@ -43,16 +43,16 @@ UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
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// this is the unified register number
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//
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int UltraSparcRegInfo::getZeroRegNum() const {
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return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
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SparcIntRegOrder::g0);
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return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
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SparcIntRegClass::g0);
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}
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// getCallAddressReg - returns the reg used for pushing the address when a
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// method is called. This can be used for other purposes between calls
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//
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unsigned UltraSparcRegInfo::getCallAddressReg() const {
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return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
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SparcIntRegOrder::o7);
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return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
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SparcIntRegClass::o7);
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}
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// Returns the register containing the return address.
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@ -60,22 +60,73 @@ unsigned UltraSparcRegInfo::getCallAddressReg() const {
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// value when a return instruction is reached.
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//
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unsigned UltraSparcRegInfo::getReturnAddressReg() const {
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return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
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SparcIntRegOrder::i7);
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return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
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SparcIntRegClass::i7);
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}
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// Register get name implementations...
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// Int register names in same order as enum in class SparcIntRegClass
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static const char * const IntRegNames[] = {
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"o0", "o1", "o2", "o3", "o4", "o5", "o7",
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"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
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"i0", "i1", "i2", "i3", "i4", "i5",
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"i6", "i7",
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"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
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"o6"
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};
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const char * const SparcIntRegClass::getRegName(unsigned reg) {
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assert(reg < NumOfAllRegs);
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return IntRegNames[reg];
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}
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static const char * const FloatRegNames[] = {
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"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
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"f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
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"f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
|
||||
"f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
|
||||
"f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49",
|
||||
"f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59",
|
||||
"f60", "f61", "f62", "f63"
|
||||
};
|
||||
|
||||
const char * const SparcFloatRegClass::getRegName(unsigned reg) {
|
||||
assert (reg < NumOfAllRegs);
|
||||
return FloatRegNames[reg];
|
||||
}
|
||||
|
||||
|
||||
static const char * const IntCCRegNames[] = {
|
||||
"xcc", "ccr"
|
||||
};
|
||||
|
||||
const char * const SparcIntCCRegClass::getRegName(unsigned reg) {
|
||||
assert(reg < 2);
|
||||
return IntCCRegNames[reg];
|
||||
}
|
||||
|
||||
static const char * const FloatCCRegNames[] = {
|
||||
"fcc0", "fcc1", "fcc2", "fcc3"
|
||||
};
|
||||
|
||||
const char * const SparcFloatCCRegClass::getRegName(unsigned reg) {
|
||||
assert (reg < 4);
|
||||
return FloatCCRegNames[reg];
|
||||
}
|
||||
|
||||
// given the unified register number, this gives the name
|
||||
// for generating assembly code or debugging.
|
||||
//
|
||||
const std::string UltraSparcRegInfo::getUnifiedRegName(int reg) const {
|
||||
const char * const UltraSparcRegInfo::getUnifiedRegName(int reg) const {
|
||||
if( reg < 32 )
|
||||
return SparcIntRegOrder::getRegName(reg);
|
||||
return SparcIntRegClass::getRegName(reg);
|
||||
else if ( reg < (64 + 32) )
|
||||
return SparcFloatRegOrder::getRegName( reg - 32);
|
||||
return SparcFloatRegClass::getRegName( reg - 32);
|
||||
else if( reg < (64+32+4) )
|
||||
return SparcFloatCCRegOrder::getRegName( reg -32 - 64);
|
||||
return SparcFloatCCRegClass::getRegName( reg -32 - 64);
|
||||
else if( reg < (64+32+4+2) ) // two names: %xcc and %ccr
|
||||
return SparcIntCCRegOrder::getRegName( reg -32 - 64 - 4);
|
||||
return SparcIntCCRegClass::getRegName( reg -32 - 64 - 4);
|
||||
else if (reg== InvalidRegNum) //****** TODO: Remove */
|
||||
return "<*NoReg*>";
|
||||
else
|
||||
@ -85,14 +136,14 @@ const std::string UltraSparcRegInfo::getUnifiedRegName(int reg) const {
|
||||
|
||||
// Get unified reg number for frame pointer
|
||||
unsigned UltraSparcRegInfo::getFramePointer() const {
|
||||
return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
|
||||
SparcIntRegOrder::i6);
|
||||
return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
|
||||
SparcIntRegClass::i6);
|
||||
}
|
||||
|
||||
// Get unified reg number for stack pointer
|
||||
unsigned UltraSparcRegInfo::getStackPointer() const {
|
||||
return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
|
||||
SparcIntRegOrder::o6);
|
||||
return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
|
||||
SparcIntRegClass::o6);
|
||||
}
|
||||
|
||||
|
||||
@ -135,7 +186,7 @@ UltraSparcRegInfo::regNumForIntArg(bool inCallee, bool isVarArgsCall,
|
||||
if (argNo >= NumOfIntArgRegs)
|
||||
return InvalidRegNum;
|
||||
else
|
||||
return argNo + (inCallee? SparcIntRegOrder::i0 : SparcIntRegOrder::o0);
|
||||
return argNo + (inCallee? SparcIntRegClass::i0 : SparcIntRegClass::o0);
|
||||
}
|
||||
|
||||
// Get the register number for the specified FP arg#,
|
||||
@ -162,10 +213,10 @@ UltraSparcRegInfo::regNumForFPArg(unsigned regType,
|
||||
regClassId = FloatRegClassID;
|
||||
if (regType == FPSingleRegType)
|
||||
return (argNo*2+1 >= NumOfFloatArgRegs)?
|
||||
InvalidRegNum : SparcFloatRegOrder::f0 + (argNo * 2 + 1);
|
||||
InvalidRegNum : SparcFloatRegClass::f0 + (argNo * 2 + 1);
|
||||
else if (regType == FPDoubleRegType)
|
||||
return (argNo*2 >= NumOfFloatArgRegs)?
|
||||
InvalidRegNum : SparcFloatRegOrder::f0 + (argNo * 2);
|
||||
InvalidRegNum : SparcFloatRegClass::f0 + (argNo * 2);
|
||||
else
|
||||
assert(0 && "Illegal FP register type");
|
||||
return 0;
|
||||
@ -279,7 +330,7 @@ void UltraSparcRegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
|
||||
|
||||
// return address is always mapped to i7 so set it immediately
|
||||
RetMI->SetRegForOperand(0, getUnifiedRegNum(IntRegClassID,
|
||||
SparcIntRegOrder::i7));
|
||||
SparcIntRegClass::i7));
|
||||
|
||||
// Possible Optimization:
|
||||
// Instead of setting the color, we can suggest one. In that case,
|
||||
@ -312,7 +363,7 @@ void UltraSparcRegInfo::suggestReg4CallAddr(MachineInstr * CallMI,
|
||||
RetAddrLR->insert( RetAddrVal );
|
||||
unsigned RegClassID = getRegClassIDOfValue( RetAddrVal );
|
||||
RetAddrLR->setRegClass( RCList[RegClassID] );
|
||||
RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID,SparcIntRegOrder::o7));
|
||||
RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID,SparcIntRegClass::o7));
|
||||
LRI.addLRToMap( RetAddrVal, RetAddrLR);
|
||||
|
||||
}
|
||||
@ -548,9 +599,9 @@ void UltraSparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
|
||||
// now suggest a register depending on the register class of ret arg
|
||||
|
||||
if( RegClassID == IntRegClassID )
|
||||
RetValLR->setSuggestedColor(SparcIntRegOrder::o0);
|
||||
RetValLR->setSuggestedColor(SparcIntRegClass::o0);
|
||||
else if (RegClassID == FloatRegClassID )
|
||||
RetValLR->setSuggestedColor(SparcFloatRegOrder::f0 );
|
||||
RetValLR->setSuggestedColor(SparcFloatRegClass::f0 );
|
||||
else assert( 0 && "Unknown reg class for return value of call\n");
|
||||
}
|
||||
|
||||
@ -748,16 +799,16 @@ void UltraSparcRegInfo::colorCallArgs(MachineInstr *CallMI,
|
||||
unsigned UniRetReg; // unified number for CorrectCol
|
||||
|
||||
if(RegClassID == IntRegClassID)
|
||||
CorrectCol = SparcIntRegOrder::o0;
|
||||
CorrectCol = SparcIntRegClass::o0;
|
||||
else if(RegClassID == FloatRegClassID)
|
||||
CorrectCol = SparcFloatRegOrder::f0;
|
||||
CorrectCol = SparcFloatRegClass::f0;
|
||||
else {
|
||||
assert( 0 && "Unknown RegClass");
|
||||
return;
|
||||
}
|
||||
|
||||
// convert to unified number
|
||||
UniRetReg = this->getUnifiedRegNum( RegClassID, CorrectCol);
|
||||
UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol);
|
||||
|
||||
// Mark the register as used by this instruction
|
||||
CallMI->getRegsUsed().insert(UniRetReg);
|
||||
@ -947,9 +998,9 @@ void UltraSparcRegInfo::suggestReg4RetValue(MachineInstr *RetMI,
|
||||
unsigned RegClassID = (LR->getRegClass())->getID();
|
||||
|
||||
if (RegClassID == IntRegClassID)
|
||||
LR->setSuggestedColor(SparcIntRegOrder::i0);
|
||||
LR->setSuggestedColor(SparcIntRegClass::i0);
|
||||
else if (RegClassID == FloatRegClassID)
|
||||
LR->setSuggestedColor(SparcFloatRegOrder::f0);
|
||||
LR->setSuggestedColor(SparcFloatRegClass::f0);
|
||||
}
|
||||
}
|
||||
|
||||
@ -986,16 +1037,16 @@ void UltraSparcRegInfo::colorRetValue(MachineInstr *RetMI,
|
||||
|
||||
unsigned CorrectCol;
|
||||
if(RegClassID == IntRegClassID)
|
||||
CorrectCol = SparcIntRegOrder::i0;
|
||||
CorrectCol = SparcIntRegClass::i0;
|
||||
else if(RegClassID == FloatRegClassID)
|
||||
CorrectCol = SparcFloatRegOrder::f0;
|
||||
CorrectCol = SparcFloatRegClass::f0;
|
||||
else {
|
||||
assert (0 && "Unknown RegClass");
|
||||
return;
|
||||
}
|
||||
|
||||
// convert to unified number
|
||||
unsigned UniRetReg = this->getUnifiedRegNum(RegClassID, CorrectCol);
|
||||
unsigned UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol);
|
||||
|
||||
// Mark the register as used by this instruction
|
||||
RetMI->getRegsUsed().insert(UniRetReg);
|
||||
@ -1067,7 +1118,7 @@ UltraSparcRegInfo::cpReg2RegMI(vector<MachineInstr*>& mvec,
|
||||
switch( RegType ) {
|
||||
|
||||
case IntCCRegType:
|
||||
if (this->getRegType(DestReg) == IntRegType)
|
||||
if (getRegType(DestReg) == IntRegType)
|
||||
{ // copy intCC reg to int reg
|
||||
// Use SrcReg+1 to get the name "%ccr" instead of "%xcc" for RDCCR
|
||||
MI = Create2OperandInstr_Reg(RDCCR, SrcReg+1, DestReg);
|
||||
@ -1075,7 +1126,7 @@ UltraSparcRegInfo::cpReg2RegMI(vector<MachineInstr*>& mvec,
|
||||
else
|
||||
{ // copy int reg to intCC reg
|
||||
// Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR
|
||||
assert(this->getRegType(SrcReg) == IntRegType
|
||||
assert(getRegType(SrcReg) == IntRegType
|
||||
&& "Can only copy CC reg to/from integer reg");
|
||||
MI = Create2OperandInstr_Reg(WRCCR, SrcReg, DestReg+1);
|
||||
}
|
||||
@ -1086,7 +1137,7 @@ UltraSparcRegInfo::cpReg2RegMI(vector<MachineInstr*>& mvec,
|
||||
break;
|
||||
|
||||
case IntRegType:
|
||||
MI = Create3OperandInstr_Reg(ADD, SrcReg, this->getZeroRegNum(), DestReg);
|
||||
MI = Create3OperandInstr_Reg(ADD, SrcReg, getZeroRegNum(), DestReg);
|
||||
break;
|
||||
|
||||
case FPSingleRegType:
|
||||
@ -1149,13 +1200,13 @@ UltraSparcRegInfo::cpReg2MemMI(vector<MachineInstr*>& mvec,
|
||||
|
||||
case IntCCRegType:
|
||||
assert(scratchReg >= 0 && "Need scratch reg to store %ccr to memory");
|
||||
assert(this->getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
|
||||
assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
|
||||
|
||||
// Use SrcReg+1 to get the name "%ccr" instead of "%xcc" for RDCCR
|
||||
MI = Create2OperandInstr_Reg(RDCCR, SrcReg+1, scratchReg);
|
||||
mvec.push_back(MI);
|
||||
|
||||
this->cpReg2MemMI(mvec, scratchReg, DestPtrReg, Offset, IntRegType);
|
||||
cpReg2MemMI(mvec, scratchReg, DestPtrReg, Offset, IntRegType);
|
||||
break;
|
||||
|
||||
case FloatCCRegType:
|
||||
@ -1218,8 +1269,8 @@ UltraSparcRegInfo::cpMem2RegMI(vector<MachineInstr*>& mvec,
|
||||
|
||||
case IntCCRegType:
|
||||
assert(scratchReg >= 0 && "Need scratch reg to load %ccr from memory");
|
||||
assert(this->getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
|
||||
this->cpMem2RegMI(mvec, SrcPtrReg, Offset, scratchReg, IntRegType);
|
||||
assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
|
||||
cpMem2RegMI(mvec, SrcPtrReg, Offset, scratchReg, IntRegType);
|
||||
|
||||
// Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR
|
||||
MI = Create2OperandInstr_Reg(WRCCR, scratchReg, DestReg+1);
|
||||
@ -1263,7 +1314,7 @@ UltraSparcRegInfo::cpValue2Value(Value *Src,
|
||||
case IntRegType:
|
||||
MI = new MachineInstr(ADD, 3);
|
||||
MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
|
||||
MI->SetMachineOperandReg(1, this->getZeroRegNum(), false);
|
||||
MI->SetMachineOperandReg(1, getZeroRegNum(), false);
|
||||
MI->SetMachineOperandVal(2, MachineOperand:: MO_VirtualRegister, Dest, true);
|
||||
break;
|
||||
|
||||
@ -1390,13 +1441,13 @@ UltraSparcRegInfo::insertCallerSavingCode(vector<MachineInstr*>& instrnsBefore,
|
||||
// the save code.
|
||||
int scratchRegType = -1;
|
||||
int scratchReg = -1;
|
||||
if (this->regTypeNeedsScratchReg(RegType, scratchRegType))
|
||||
if (regTypeNeedsScratchReg(RegType, scratchRegType))
|
||||
{ // Find a register not live in the LVSet before CallMI
|
||||
const ValueSet &LVSetBef =
|
||||
PRA.LVI->getLiveVarSetBeforeMInst(CallMI, BB);
|
||||
scratchReg = PRA.getUsableUniRegAtMI(scratchRegType, &LVSetBef,
|
||||
CallMI, AdIBef, AdIAft);
|
||||
assert(scratchReg != this->getInvalidRegNum());
|
||||
assert(scratchReg != getInvalidRegNum());
|
||||
CallMI->getRegsUsed().insert(scratchReg);
|
||||
}
|
||||
|
||||
@ -1420,11 +1471,11 @@ UltraSparcRegInfo::insertCallerSavingCode(vector<MachineInstr*>& instrnsBefore,
|
||||
//
|
||||
scratchRegType = -1;
|
||||
scratchReg = -1;
|
||||
if (this->regTypeNeedsScratchReg(RegType, scratchRegType))
|
||||
if (regTypeNeedsScratchReg(RegType, scratchRegType))
|
||||
{ // Find a register not live in the LVSet after CallMI
|
||||
scratchReg = PRA.getUsableUniRegAtMI(scratchRegType, &LVSetAft,
|
||||
CallMI, AdIBef, AdIAft);
|
||||
assert(scratchReg != this->getInvalidRegNum());
|
||||
assert(scratchReg != getInvalidRegNum());
|
||||
CallMI->getRegsUsed().insert(scratchReg);
|
||||
}
|
||||
|
||||
@ -1480,12 +1531,12 @@ void UltraSparcRegInfo::printReg(const LiveRange *LR) {
|
||||
cerr << " colored with color "<< LR->getColor();
|
||||
|
||||
if (RegClassID == IntRegClassID) {
|
||||
cerr<< " [" << SparcIntRegOrder::getRegName(LR->getColor()) << "]\n";
|
||||
cerr<< " [" << SparcIntRegClass::getRegName(LR->getColor()) << "]\n";
|
||||
|
||||
} else if (RegClassID == FloatRegClassID) {
|
||||
cerr << "[" << SparcFloatRegOrder::getRegName(LR->getColor());
|
||||
cerr << "[" << SparcFloatRegClass::getRegName(LR->getColor());
|
||||
if( LR->getType() == Type::DoubleTy)
|
||||
cerr << "+" << SparcFloatRegOrder::getRegName(LR->getColor()+1);
|
||||
cerr << "+" << SparcFloatRegClass::getRegName(LR->getColor()+1);
|
||||
cerr << "]\n";
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user