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Assertion when using a 1-element vector for an add operation. Get the
real vector type in this case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36402 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -308,19 +308,22 @@ unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
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const VectorType *PTy = cast<VectorType>(V->getType());
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unsigned NumElts = PTy->getNumElements();
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MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
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MVT::ValueType VecTy = getVectorType(EltTy, NumElts);
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// Divide the input until we get to a supported size. This will always
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// end with a scalar if the target doesn't support vectors.
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while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
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while (NumElts > 1 && !TLI.isTypeLegal(VecTy)) {
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NumElts >>= 1;
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NumVectorRegs <<= 1;
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}
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if (NumElts == 1)
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// Check that VecTy isn't a 1-element vector.
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if (NumElts == 1 && VecTy == MVT::Other)
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VT = EltTy;
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else
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VT = getVectorType(EltTy, NumElts);
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VT = VecTy;
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}
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// The common case is that we will only create one register for this
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// value. If we have that case, create and return the virtual register.
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unsigned NV = TLI.getNumElements(VT);
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