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Assertion when using a 1-element vector for an add operation. Get the

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real vector type in this case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36402 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2007-04-24 21:13:23 +00:00
parent 93675f4cdd
commit 95b3955034
1 changed files with 7 additions and 4 deletions
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9
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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@ -308,17 +308,20 @@ unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
const VectorType *PTy = cast<VectorType>(V->getType());
unsigned NumElts = PTy->getNumElements();
MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
MVT::ValueType VecTy = getVectorType(EltTy, NumElts);
// Divide the input until we get to a supported size. This will always
// end with a scalar if the target doesn't support vectors.
while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
while (NumElts > 1 && !TLI.isTypeLegal(VecTy)) {
NumElts >>= 1;
NumVectorRegs <<= 1;
}
if (NumElts == 1)
// Check that VecTy isn't a 1-element vector.
if (NumElts == 1 && VecTy == MVT::Other)
VT = EltTy;
else
VT = getVectorType(EltTy, NumElts);
VT = VecTy;
}
// The common case is that we will only create one register for this