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Generate the dispatch table for ARM mode.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141327 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2011-10-06 22:53:00 +00:00
parent e29fa1df55
commit 95ce2e9c52
1 changed files with 70 additions and 28 deletions
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98
lib/Target/ARM/ARMISelLowering.cpp
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@ -5685,42 +5685,84 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
// context.
SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI);
// Grab constant pool and fixed stack memory operands.
MachineMemOperand *FIMMOLd =
MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
MachineMemOperand::MOLoad, 4, 4);
unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
.addFrameIndex(FI)
.addImm(4)
.addMemOperand(FIMMOLd));
AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
.addReg(NewVReg1)
.addImm(LPadList.size()));
BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
.addMBB(TrapBB)
.addImm(ARMCC::HI)
.addReg(ARM::CPSR);
if (Subtarget->isThumb2()) {
unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
.addFrameIndex(FI)
.addImm(4)
.addMemOperand(FIMMOLd));
AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
.addReg(NewVReg1)
.addImm(LPadList.size()));
BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
.addMBB(TrapBB)
.addImm(ARMCC::HI)
.addReg(ARM::CPSR);
unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT), NewVReg2)
.addJumpTableIndex(MJTI)
.addImm(UId));
unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg2)
.addJumpTableIndex(MJTI)
.addImm(UId));
unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
AddDefaultCC(
AddDefaultPred(
BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg3)
.addReg(NewVReg2, RegState::Kill)
unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
AddDefaultCC(
AddDefaultPred(
BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg3)
.addReg(NewVReg2, RegState::Kill)
.addReg(NewVReg1)
.addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
.addReg(NewVReg3, RegState::Kill)
.addReg(NewVReg1)
.addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
.addJumpTableIndex(MJTI)
.addImm(UId);
} else if (Subtarget->isThumb()) {
} else {
unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
.addFrameIndex(FI)
.addImm(4)
.addMemOperand(FIMMOLd));
AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
.addReg(NewVReg1)
.addImm(LPadList.size()));
BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
.addMBB(TrapBB)
.addImm(ARMCC::HI)
.addReg(ARM::CPSR);
BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
.addReg(NewVReg3, RegState::Kill)
.addReg(NewVReg1)
.addJumpTableIndex(MJTI)
.addImm(UId);
unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
AddDefaultCC(
AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg2)
.addReg(NewVReg1)
.addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg3)
.addJumpTableIndex(MJTI)
.addImm(UId));
MachineMemOperand *JTMMOLd =
MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
MachineMemOperand::MOLoad, 4, 4);
unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
AddDefaultPred(
BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg4)
.addReg(NewVReg2, RegState::Kill)
.addReg(NewVReg3)
.addImm(0)
.addMemOperand(JTMMOLd));
BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
.addReg(NewVReg4, RegState::Kill)
.addReg(NewVReg3)
.addJumpTableIndex(MJTI)
.addImm(UId);
}
// Add the jump table entries as successors to the MBB.
for (std::vector<MachineBasicBlock*>::iterator