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[GlobalISel][AArch64] Make G_EXTRACT_VECTOR_ELT legal for v8s16s

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This case was missing before, so we couldn't legalize it.

Add it to AArch64LegalizerInfo.cpp and update select-extract-vector-elt.mir.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359231 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jessica Paquette 2019-04-25 20:00:57 +00:00
parent 85656d2bc3
commit 9629553b79
2 changed files with 25 additions and 2 deletions
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4
lib/Target/AArch64/AArch64LegalizerInfo.cpp
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@ -517,8 +517,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
.minScalar(2, s64)
.legalIf([=](const LegalityQuery &Query) {
const LLT &VecTy = Query.Types[1];
return VecTy == v2s16 || VecTy == v4s16 || VecTy == v4s32 ||
VecTy == v2s64 || VecTy == v2s32;
return VecTy == v2s16 || VecTy == v4s16 || VecTy == v8s16 ||
VecTy == v4s32 || VecTy == v2s64 || VecTy == v2s32;
});
getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT)

23
test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir
View File

@ -115,3 +115,26 @@ body: |
RET_ReallyLR implicit $h0
...
---
name: v8s16_fpr
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v8s16_fpr
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1
; CHECK: $h0 = COPY [[CPYi16_]]
; CHECK: RET_ReallyLR implicit $h0
%0:fpr(<8 x s16>) = COPY $q0
%2:gpr(s64) = G_CONSTANT i64 1
%3:fpr(s64) = COPY %2(s64)
%1:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)
$h0 = COPY %1(s16)
RET_ReallyLR implicit $h0
...