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AMDGPU: Remove dead code
getCFGStructurizerRegClass is not used for SI, so move it into R600 specific stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248087 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -37,10 +37,6 @@ struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
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assert(!"Unimplemented"); return BitVector();
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}
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virtual const TargetRegisterClass* getCFGStructurizerRegClass(MVT VT) const {
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assert(!"Unimplemented"); return nullptr;
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}
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virtual unsigned getHWRegIndex(unsigned Reg) const {
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assert(!"Unimplemented"); return 0;
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}
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@ -185,7 +185,7 @@ protected:
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MachinePostDominatorTree *PDT;
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MachineLoopInfo *MLI;
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const R600InstrInfo *TII;
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const AMDGPURegisterInfo *TRI;
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const R600RegisterInfo *TRI;
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// PRINT FUNCTIONS
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/// Print the ordered Blocks.
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@ -35,7 +35,7 @@ struct R600RegisterInfo : public AMDGPURegisterInfo {
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/// \brief get the register class of the specified type to use in the
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/// CFGStructurizer
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const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const override;
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const TargetRegisterClass *getCFGStructurizerRegClass(MVT VT) const;
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const RegClassWeight &
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getRegClassWeight(const TargetRegisterClass *RC) const override;
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@ -323,14 +323,6 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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}
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}
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const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass(
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MVT VT) const {
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switch(VT.SimpleTy) {
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default:
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case MVT::i32: return &AMDGPU::VGPR_32RegClass;
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}
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}
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unsigned SIRegisterInfo::getHWRegIndex(unsigned Reg) const {
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return getEncodingValue(Reg) & 0xff;
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}
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@ -40,10 +40,6 @@ public:
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unsigned FIOperandNum,
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RegScavenger *RS) const override;
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/// \brief get the register class of the specified type to use in the
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/// CFGStructurizer
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const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const override;
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unsigned getHWRegIndex(unsigned Reg) const override;
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/// \brief Return the 'base' register class for this register.
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