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Added preliminary x86 subtarget support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25645 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
b0636041c8
commit
97c7fc351e
@ -13,7 +13,8 @@ TARGET = X86
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BUILT_SOURCES = X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
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X86GenRegisterInfo.inc X86GenInstrNames.inc \
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X86GenInstrInfo.inc X86GenAsmWriter.inc \
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X86GenAsmWriter1.inc X86GenDAGISel.inc
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X86GenAsmWriter1.inc X86GenDAGISel.inc \
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X86GenSubtarget.inc
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include $(LEVEL)/Makefile.common
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@ -26,7 +26,7 @@ class IntrinsicLowering;
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class MachineCodeEmitter;
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enum X86VectorEnum {
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NoSSE, SSE, SSE2, SSE3
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AutoDetect, NoSSE, SSE, SSE2, SSE3
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};
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extern X86VectorEnum X86Vector;
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@ -16,6 +16,75 @@
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//
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include "../Target.td"
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//===----------------------------------------------------------------------===//
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// X86 Subtarget features.
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//
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def Feature64Bit : SubtargetFeature<"64bit", "bool", "Is64Bit",
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"Enable 64-bit instructions">;
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def FeatureMMX : SubtargetFeature<"mmx", "bool", "HasMMX",
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"Enable MMX instructions">;
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def FeatureSSE : SubtargetFeature<"sse", "bool", "HasSSE",
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"Enable SSE instructions">;
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def FeatureSSE2 : SubtargetFeature<"sse2", "bool", "HasSSE2",
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"Enable SSE2 instructions">;
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def FeatureSSE3 : SubtargetFeature<"sse3", "bool", "HasSSE3",
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"Enable SSE3 instructions">;
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def Feature3DNow : SubtargetFeature<"3dnow", "bool", "Has3DNow",
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"Enable 3DNow! instructions">;
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def Feature3DNowA : SubtargetFeature<"3dnowa", "bool", "Has3DNowA",
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"Enable 3DNow! Athlon instructions">;
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//===----------------------------------------------------------------------===//
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// X86 processors supported.
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//===----------------------------------------------------------------------===//
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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def : Proc<"generic", []>;
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def : Proc<"i386", []>;
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def : Proc<"i486", []>;
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def : Proc<"i586", []>;
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def : Proc<"pentium", []>;
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def : Proc<"pentium-mmx", [FeatureMMX]>;
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def : Proc<"i686", []>;
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def : Proc<"pentiumpro", []>;
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def : Proc<"pentium2", [FeatureMMX]>;
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def : Proc<"celeron", [FeatureMMX]>;
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def : Proc<"pentium3", [FeatureMMX, FeatureSSE]>;
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def : Proc<"pentium3m", [FeatureMMX, FeatureSSE]>;
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def : Proc<"pentium-m", [FeatureMMX, FeatureSSE, FeatureSSE2]>;
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def : Proc<"pentium4", [FeatureMMX, FeatureSSE, FeatureSSE2]>;
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def : Proc<"pentium4m", [FeatureMMX, FeatureSSE, FeatureSSE2]>;
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def : Proc<"prescott", [FeatureMMX, FeatureSSE, FeatureSSE2,
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FeatureSSE3]>;
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def : Proc<"x86-64", [FeatureMMX, FeatureSSE, FeatureSSE2, Feature64Bit]>;
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def : Proc<"nocona", [FeatureMMX, FeatureSSE, FeatureSSE2,
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FeatureSSE3, Feature64Bit]>;
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def : Proc<"k6", [FeatureMMX]>;
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def : Proc<"k6-2", [FeatureMMX, Feature3DNow]>;
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def : Proc<"k6-3", [FeatureMMX, Feature3DNow]>;
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def : Proc<"athlon", [FeatureMMX, Feature3DNow, Feature3DNowA]>;
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def : Proc<"athlon-tbird", [FeatureMMX, Feature3DNow, Feature3DNowA]>;
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def : Proc<"athlon-4", [FeatureMMX, FeatureSSE, Feature3DNow, Feature3DNowA]>;
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def : Proc<"athlon-xp", [FeatureMMX, FeatureSSE, Feature3DNow, Feature3DNowA]>;
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def : Proc<"athlon-mp", [FeatureMMX, FeatureSSE, Feature3DNow, Feature3DNowA]>;
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def : Proc<"k8", [FeatureMMX, FeatureSSE, FeatureSSE2, Feature3DNow,
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Feature3DNowA, Feature64Bit]>;
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def : Proc<"opteron", [FeatureMMX, FeatureSSE, FeatureSSE2, Feature3DNow,
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Feature3DNowA, Feature64Bit]>;
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def : Proc<"athlon64", [FeatureMMX, FeatureSSE, FeatureSSE2, Feature3DNow,
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Feature3DNowA, Feature64Bit]>;
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def : Proc<"athlon-fx", [FeatureMMX, FeatureSSE, FeatureSSE2, Feature3DNow,
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Feature3DNowA, Feature64Bit]>;
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def : Proc<"winchip-c6", [FeatureMMX]>;
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def : Proc<"winchip2", [FeatureMMX, Feature3DNow]>;
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def : Proc<"c3", [FeatureMMX, Feature3DNow]>;
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def : Proc<"c3-2", [FeatureMMX, FeatureSSE]>;
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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@ -13,11 +13,64 @@
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#include "X86Subtarget.h"
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#include "llvm/Module.h"
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#include "X86GenSubtarget.inc"
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using namespace llvm;
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#if defined(__APPLE__)
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#include <mach/mach.h>
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#include <mach/mach_host.h>
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#include <mach/host_info.h>
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#include <mach/machine.h>
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/// GetCurrentX86CPU - Returns the current CPUs features.
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static const char *GetCurrentX86CPU() {
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host_basic_info_data_t hostInfo;
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mach_msg_type_number_t infoCount;
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infoCount = HOST_BASIC_INFO_COUNT;
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host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo,
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&infoCount);
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if (hostInfo.cpu_type != CPU_TYPE_I386) return "generic";
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switch(hostInfo.cpu_subtype) {
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case CPU_SUBTYPE_386: return "i386";
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case CPU_SUBTYPE_486:
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case CPU_SUBTYPE_486SX: return "i486";
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case CPU_SUBTYPE_PENT: return "pentium";
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case CPU_SUBTYPE_PENTPRO: return "pentiumpro";
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case CPU_SUBTYPE_PENTII_M3: return "pentium2";
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case CPU_SUBTYPE_PENTII_M5: return "pentium2";
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case CPU_SUBTYPE_CELERON:
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case CPU_SUBTYPE_CELERON_MOBILE: return "celeron";
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case CPU_SUBTYPE_PENTIUM_3: return "pentium3";
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case CPU_SUBTYPE_PENTIUM_3_M: return "pentium3m";
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case CPU_SUBTYPE_PENTIUM_3_XEON: return "pentium3"; // FIXME: not sure.
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case CPU_SUBTYPE_PENTIUM_M: return "pentium-m";
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case CPU_SUBTYPE_PENTIUM_4: return "pentium4";
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case CPU_SUBTYPE_PENTIUM_4_M: return "pentium4m";
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// FIXME: prescott, yonah? Check CPU_THREADTYPE_INTEL_HTT?
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case CPU_SUBTYPE_XEON:
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case CPU_SUBTYPE_XEON_MP: return "nocona";
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default: ;
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}
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return "generic";
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}
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#endif
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X86Subtarget::X86Subtarget(const Module &M, const std::string &FS)
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: stackAlignment(8), indirectExternAndWeakGlobals(false) {
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// Determine default and user specified characteristics
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std::string CPU = "generic";
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#if defined(__APPLE__)
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CPU = GetCurrentX86CPU();
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#endif
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// Parse features string.
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ParseSubtargetFeatures(FS, CPU);
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// Default to ELF unless otherwise specified.
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TargetType = isELF;
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@ -30,6 +30,14 @@ protected:
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/// Used by instruction selector
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bool indirectExternAndWeakGlobals;
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/// Arch. features used by isel.
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bool Is64Bit;
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bool HasMMX;
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bool HasSSE;
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bool HasSSE2;
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bool HasSSE3;
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bool Has3DNow;
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bool Has3DNowA;
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public:
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enum {
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isELF, isCygwin, isDarwin, isWindows
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@ -51,6 +59,19 @@ public:
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bool getIndirectExternAndWeakGlobals() const {
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return indirectExternAndWeakGlobals;
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}
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/// ParseSubtargetFeatures - Parses features string setting specified
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/// subtarget options. Definition of function is auto generated by tblgen.
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void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
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bool is64Bit() const { return Is64Bit; }
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bool hasMMX() const { return HasMMX; }
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bool hasSSE() const { return HasSSE; }
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bool hasSSE2() const { return HasSSE2; }
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bool hasSSE3() const { return HasSSE3; }
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bool has3DNow() const { return Has3DNow; }
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bool has3DNowA() const { return Has3DNowA; }
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};
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} // End llvm namespace
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@ -26,7 +26,7 @@
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#include <iostream>
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using namespace llvm;
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X86VectorEnum llvm::X86Vector = NoSSE;
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X86VectorEnum llvm::X86Vector = AutoDetect;
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bool llvm::X86ScalarSSE = false;
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bool llvm::X86DAGIsel = false;
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@ -61,7 +61,7 @@ namespace {
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clEnumValN(SSE2, "sse2", " Enable SSE and SSE2 support"),
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clEnumValN(SSE3, "sse3", " Enable SSE, SSE2, and SSE3 support"),
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clEnumValEnd),
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cl::location(X86Vector), cl::init(NoSSE));
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cl::location(X86Vector), cl::init(AutoDetect));
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// Register the target.
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RegisterTarget<X86TargetMachine> X("x86", " IA-32 (Pentium and above)");
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@ -102,6 +102,16 @@ X86TargetMachine::X86TargetMachine(const Module &M,
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FrameInfo(TargetFrameInfo::StackGrowsDown,
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Subtarget.getStackAlignment(), -4),
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JITInfo(*this) {
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if (X86Vector == AutoDetect) {
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X86Vector = NoSSE;
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if (Subtarget.hasSSE())
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X86Vector = SSE;
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if (Subtarget.hasSSE2())
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X86Vector = SSE2;
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if (Subtarget.hasSSE3())
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X86Vector = SSE3;
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}
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// Scalar SSE FP requires at least SSE2
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X86ScalarSSE &= X86Vector >= SSE2;
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