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Janitorial services: "Don’t duplicate function or class name at the beginning of the comment."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216674 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sanjay Patel
parent
e43c262106
commit
98491c0ff9
@ -113,22 +113,19 @@ namespace {
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// AA - Used for DAG load/store alias analysis.
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AliasAnalysis &AA;
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/// AddUsersToWorklist - When an instruction is simplified, add all users of
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/// the instruction to the work lists because they might get more simplified
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/// now.
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///
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/// When an instruction is simplified, add all users of the instruction to
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/// the work lists because they might get more simplified now.
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void AddUsersToWorklist(SDNode *N) {
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for (SDNode *Node : N->uses())
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AddToWorklist(Node);
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}
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/// visit - call the node-specific routine that knows how to fold each
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/// particular type of node.
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/// Call the node-specific routine that folds each particular type of node.
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SDValue visit(SDNode *N);
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public:
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/// AddToWorklist - Add to the work list making sure its instance is at the
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/// back (next to be processed.)
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/// Add to the worklist making sure its instance is at the back (next to be
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/// processed.)
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void AddToWorklist(SDNode *N) {
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// Skip handle nodes as they can't usefully be combined and confuse the
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// zero-use deletion strategy.
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@ -139,8 +136,7 @@ namespace {
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Worklist.push_back(N);
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}
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/// removeFromWorklist - remove all instances of N from the worklist.
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///
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/// Remove all instances of N from the worklist.
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void removeFromWorklist(SDNode *N) {
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CombinedNodes.erase(N);
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@ -173,9 +169,9 @@ namespace {
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private:
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/// SimplifyDemandedBits - Check the specified integer node value to see if
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/// it can be simplified or if things it uses can be simplified by bit
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/// propagation. If so, return true.
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/// Check the specified integer node value to see if it can be simplified or
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/// if things it uses can be simplified by bit propagation.
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/// If so, return true.
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bool SimplifyDemandedBits(SDValue Op) {
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unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
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APInt Demanded = APInt::getAllOnesValue(BitWidth);
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@ -211,7 +207,7 @@ namespace {
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SDValue Trunc, SDValue ExtLoad, SDLoc DL,
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ISD::NodeType ExtType);
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/// combine - call the node-specific routine that knows how to fold each
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/// Call the node-specific routine that knows how to fold each
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/// particular type of node. If that doesn't do anything, try the
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/// target-specific DAG combines.
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SDValue combine(SDNode *N);
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@ -341,17 +337,16 @@ namespace {
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SDValue GetDemandedBits(SDValue V, const APInt &Mask);
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/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
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/// Walk up chain skipping non-aliasing memory nodes,
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/// looking for aliasing nodes and adding them to the Aliases vector.
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void GatherAllAliases(SDNode *N, SDValue OriginalChain,
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SmallVectorImpl<SDValue> &Aliases);
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/// isAlias - Return true if there is any possibility that the two addresses
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/// overlap.
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/// Return true if there is any possibility that the two addresses overlap.
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bool isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) const;
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/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
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/// looking for a better chain (aliasing node.)
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/// Walk up chain skipping non-aliasing memory nodes, looking for a better
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/// chain (aliasing node.)
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SDValue FindBetterChain(SDNode *N, SDValue Chain);
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/// Merge consecutive store operations into a wide store.
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@ -379,13 +374,13 @@ namespace {
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FnAttrs.hasAttribute(AttributeSet::FunctionIndex, Attribute::MinSize);
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}
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/// Run - runs the dag combiner on all nodes in the work list
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/// Runs the dag combiner on all nodes in the work list
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void Run(CombineLevel AtLevel);
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SelectionDAG &getDAG() const { return DAG; }
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/// getShiftAmountTy - Returns a type large enough to hold any valid
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/// shift amount - before type legalization these can be huge.
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/// Returns a type large enough to hold any valid shift amount - before type
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/// legalization these can be huge.
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EVT getShiftAmountTy(EVT LHSTy) {
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assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
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if (LHSTy.isVector())
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@ -394,15 +389,14 @@ namespace {
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: TLI.getPointerTy();
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}
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/// isTypeLegal - This method returns true if we are running before type
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/// legalization or if the specified VT is legal.
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/// This method returns true if we are running before type legalization or
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/// if the specified VT is legal.
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bool isTypeLegal(const EVT &VT) {
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if (!LegalTypes) return true;
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return TLI.isTypeLegal(VT);
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}
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/// getSetCCResultType - Convenience wrapper around
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/// TargetLowering::getSetCCResultType
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/// Convenience wrapper around TargetLowering::getSetCCResultType
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EVT getSetCCResultType(EVT VT) const {
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return TLI.getSetCCResultType(*DAG.getContext(), VT);
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}
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@ -411,7 +405,7 @@ namespace {
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namespace {
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/// WorklistRemover - This class is a DAGUpdateListener that removes any deleted
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/// This class is a DAGUpdateListener that removes any deleted
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/// nodes from the worklist.
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class WorklistRemover : public SelectionDAG::DAGUpdateListener {
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DAGCombiner &DC;
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@ -474,9 +468,9 @@ void DAGCombiner::deleteAndRecombine(SDNode *N) {
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DAG.DeleteNode(N);
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}
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/// isNegatibleForFree - Return 1 if we can compute the negated form of the
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/// specified expression for the same cost as the expression itself, or 2 if we
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/// can compute the negated form more cheaply than the expression itself.
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/// Return 1 if we can compute the negated form of the specified expression for
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/// the same cost as the expression itself, or 2 if we can compute the negated
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/// form more cheaply than the expression itself.
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static char isNegatibleForFree(SDValue Op, bool LegalOperations,
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const TargetLowering &TLI,
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const TargetOptions *Options,
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@ -539,8 +533,7 @@ static char isNegatibleForFree(SDValue Op, bool LegalOperations,
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}
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}
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/// GetNegatedExpression - If isNegatibleForFree returns true, this function
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/// returns the newly negated expression.
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/// If isNegatibleForFree returns true, return the newly negated expression.
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static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
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bool LegalOperations, unsigned Depth = 0) {
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const TargetOptions &Options = DAG.getTarget().Options;
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@ -643,9 +636,9 @@ bool DAGCombiner::isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
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return true;
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}
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// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
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// one use. If this is true, it allows the users to invert the operation for
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// free when it is profitable to do so.
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/// Return true if this is a SetCC-equivalent operation with only one use.
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/// If this is true, it allows the users to invert the operation for free when
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/// it is profitable to do so.
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bool DAGCombiner::isOneUseSetCC(SDValue N) const {
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SDValue N0, N1, N2;
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if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
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@ -653,7 +646,7 @@ bool DAGCombiner::isOneUseSetCC(SDValue N) const {
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return false;
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}
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/// isConstantSplatVector - Returns true if N is a BUILD_VECTOR node whose
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/// Returns true if N is a BUILD_VECTOR node whose
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/// elements are all the same constant or undefined.
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static bool isConstantSplatVector(SDNode *N, APInt& SplatValue) {
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BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(N);
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@ -820,9 +813,8 @@ CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
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deleteAndRecombine(TLO.Old.getNode());
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}
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/// SimplifyDemandedBits - Check the specified integer node value to see if
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/// it can be simplified or if things it uses can be simplified by bit
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/// propagation. If so, return true.
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/// Check the specified integer node value to see if it can be simplified or if
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/// things it uses can be simplified by bit propagation. If so, return true.
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bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
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TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
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APInt KnownZero, KnownOne;
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@ -930,9 +922,9 @@ SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
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return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
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}
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/// PromoteIntBinOp - Promote the specified integer binary operation if the
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/// target indicates it is beneficial. e.g. On x86, it's usually better to
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/// promote i16 operations to i32 since i16 instructions are longer.
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/// Promote the specified integer binary operation if the target indicates it is
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/// beneficial. e.g. On x86, it's usually better to promote i16 operations to
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/// i32 since i16 instructions are longer.
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SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
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if (!LegalOperations)
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return SDValue();
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@ -988,9 +980,9 @@ SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
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return SDValue();
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}
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/// PromoteIntShiftOp - Promote the specified integer shift operation if the
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/// target indicates it is beneficial. e.g. On x86, it's usually better to
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/// promote i16 operations to i32 since i16 instructions are longer.
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/// Promote the specified integer shift operation if the target indicates it is
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/// beneficial. e.g. On x86, it's usually better to promote i16 operations to
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/// i32 since i16 instructions are longer.
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SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
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if (!LegalOperations)
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return SDValue();
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@ -1413,8 +1405,8 @@ SDValue DAGCombiner::combine(SDNode *N) {
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return RV;
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}
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/// getInputChainForNode - Given a node, return its input chain if it has one,
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/// otherwise return a null sd operand.
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/// Given a node, return its input chain if it has one, otherwise return a null
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/// sd operand.
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static SDValue getInputChainForNode(SDNode *N) {
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if (unsigned NumOps = N->getNumOperands()) {
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if (N->getOperand(0).getValueType() == MVT::Other)
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@ -2356,10 +2348,9 @@ SDValue DAGCombiner::visitMULHU(SDNode *N) {
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return SDValue();
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}
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/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
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/// compute two values. LoOp and HiOp give the opcodes for the two computations
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/// that are being performed. Return true if a simplification was made.
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///
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/// Perform optimizations common to nodes that compute two values. LoOp and HiOp
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/// give the opcodes for the two computations that are being performed. Return
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/// true if a simplification was made.
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SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
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unsigned HiOp) {
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// If the high half is not needed, just compute the low half.
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@ -2502,8 +2493,8 @@ SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
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return SDValue();
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}
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/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
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/// two operands of the same opcode, try to simplify it.
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/// If this is a binary operator with two operands of the same opcode, try to
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/// simplify it.
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SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
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SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
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EVT VT = N0.getValueType();
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@ -3042,8 +3033,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
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return SDValue();
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}
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/// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16
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///
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/// Match (a >> 8) | (a << 8) as (bswap a) >> 16.
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SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
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bool DemandHighBits) {
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if (!LegalOperations)
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@ -3148,9 +3138,12 @@ SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
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return Res;
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}
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/// isBSwapHWordElement - Return true if the specified node is an element
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/// that makes up a 32-bit packed halfword byteswap. i.e.
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/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
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/// Return true if the specified node is an element that makes up a 32-bit
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/// packed halfword byteswap.
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/// ((x & 0x000000ff) << 8) |
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/// ((x & 0x0000ff00) >> 8) |
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/// ((x & 0x00ff0000) << 8) |
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/// ((x & 0xff000000) >> 8)
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static bool isBSwapHWordElement(SDValue N, SmallVectorImpl<SDNode *> &Parts) {
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if (!N.getNode()->hasOneUse())
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return false;
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@ -3218,8 +3211,11 @@ static bool isBSwapHWordElement(SDValue N, SmallVectorImpl<SDNode *> &Parts) {
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return true;
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}
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/// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is
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/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
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/// Match a 32-bit packed halfword bswap. That is
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/// ((x & 0x000000ff) << 8) |
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/// ((x & 0x0000ff00) >> 8) |
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/// ((x & 0x00ff0000) << 8) |
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/// ((x & 0xff000000) >> 8)
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/// => (rotl (bswap x), 16)
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SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
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if (!LegalOperations)
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@ -3506,7 +3502,7 @@ SDValue DAGCombiner::visitOR(SDNode *N) {
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return SDValue();
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}
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/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
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/// Match "(X shl/srl V1) & V2" where V2 may not be present.
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static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
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if (Op.getOpcode() == ISD::AND) {
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if (isa<ConstantSDNode>(Op.getOperand(1))) {
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@ -3896,8 +3892,8 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
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return SDValue();
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}
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/// visitShiftByConstant - Handle transforms common to the three shifts, when
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/// the shift amount is a constant.
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/// Handle transforms common to the three shifts, when the shift amount is a
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/// constant.
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SDValue DAGCombiner::visitShiftByConstant(SDNode *N, ConstantSDNode *Amt) {
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// We can't and shouldn't fold opaque constants.
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if (Amt->isOpaque())
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@ -5686,9 +5682,9 @@ SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
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return SDValue();
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}
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/// GetDemandedBits - See if the specified operand can be simplified with the
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/// knowledge that only the bits specified by Mask are used. If so, return the
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/// simpler operand, otherwise return a null SDValue.
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/// See if the specified operand can be simplified with the knowledge that only
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/// the bits specified by Mask are used. If so, return the simpler operand,
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/// otherwise return a null SDValue.
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SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
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switch (V.getOpcode()) {
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default: break;
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@ -5729,11 +5725,11 @@ SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
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return SDValue();
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}
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/// ReduceLoadWidth - If the result of a wider load is shifted to right of N
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/// bits and then truncated to a narrower type and where N is a multiple
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/// of number of bits of the narrower type, transform it to a narrower load
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/// from address + N / num of bits of new type. If the result is to be
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/// extended, also fold the extension to form a extending load.
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/// If the result of a wider load is shifted to right of N bits and then
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/// truncated to a narrower type and where N is a multiple of number of bits of
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/// the narrower type, transform it to a narrower load from address + N / num of
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/// bits of new type. If the result is to be extended, also fold the extension
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/// to form a extending load.
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SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
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unsigned Opc = N->getOpcode();
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@ -6228,7 +6224,7 @@ static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
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return Elt.getOperand(Elt.getResNo()).getNode();
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}
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/// CombineConsecutiveLoads - build_pair (load, load) -> load
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/// build_pair (load, load) -> load
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/// if load locations are consecutive.
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SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
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assert(N->getOpcode() == ISD::BUILD_PAIR);
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@ -6409,9 +6405,8 @@ SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
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return CombineConsecutiveLoads(N, VT);
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}
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/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector
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/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
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/// destination element value type.
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/// We know that BV is a build_vector node with Constant, ConstantFP or Undef
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/// operands. DstEltVT indicates the destination element value type.
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SDValue DAGCombiner::
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ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
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EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
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@ -7631,9 +7626,8 @@ SDValue DAGCombiner::visitBR_CC(SDNode *N) {
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return SDValue();
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}
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/// canFoldInAddressingMode - Return true if 'Use' is a load or a store that
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/// uses N as its base pointer and that N may be folded in the load / store
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/// addressing mode.
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/// Return true if 'Use' is a load or a store that uses N as its base pointer
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/// and that N may be folded in the load / store addressing mode.
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static bool canFoldInAddressingMode(SDNode *N, SDNode *Use,
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SelectionDAG &DAG,
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const TargetLowering &TLI) {
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@ -7672,12 +7666,11 @@ static bool canFoldInAddressingMode(SDNode *N, SDNode *Use,
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return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext()));
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}
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/// CombineToPreIndexedLoadStore - Try turning a load / store into a
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/// pre-indexed load / store when the base pointer is an add or subtract
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/// and it has other uses besides the load / store. After the
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/// transformation, the new indexed load / store has effectively folded
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/// the add / subtract in and all of its other uses are redirected to the
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/// new load / store.
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/// Try turning a load/store into a pre-indexed load/store when the base
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/// pointer is an add or subtract and it has other uses besides the load/store.
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/// After the transformation, the new indexed load/store has effectively folded
|
||||
/// the add/subtract in and all of its other uses are redirected to the
|
||||
/// new load/store.
|
||||
bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
|
||||
if (Level < AfterLegalizeDAG)
|
||||
return false;
|
||||
@ -7898,11 +7891,10 @@ bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
|
||||
return true;
|
||||
}
|
||||
|
||||
/// CombineToPostIndexedLoadStore - Try to combine a load / store with a
|
||||
/// add / sub of the base pointer node into a post-indexed load / store.
|
||||
/// The transformation folded the add / subtract into the new indexed
|
||||
/// load / store effectively and all of its uses are redirected to the
|
||||
/// new load / store.
|
||||
/// Try to combine a load/store with a add/sub of the base pointer node into a
|
||||
/// post-indexed load/store. The transformation folded the add/subtract into the
|
||||
/// new indexed load/store effectively and all of its uses are redirected to the
|
||||
/// new load/store.
|
||||
bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
|
||||
if (Level < AfterLegalizeDAG)
|
||||
return false;
|
||||
@ -8697,9 +8689,9 @@ bool DAGCombiner::SliceUpLoad(SDNode *N) {
|
||||
return true;
|
||||
}
|
||||
|
||||
/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the
|
||||
/// load is having specific bytes cleared out. If so, return the byte size
|
||||
/// being masked out and the shift amount.
|
||||
/// Check to see if V is (and load (ptr), imm), where the load is having
|
||||
/// specific bytes cleared out. If so, return the byte size being masked out
|
||||
/// and the shift amount.
|
||||
static std::pair<unsigned, unsigned>
|
||||
CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
|
||||
std::pair<unsigned, unsigned> Result(0, 0);
|
||||
@ -8772,9 +8764,9 @@ CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
|
||||
}
|
||||
|
||||
|
||||
/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that
|
||||
/// provides a value as specified by MaskInfo. If so, replace the specified
|
||||
/// store with a narrower store of truncated IVal.
|
||||
/// Check to see if IVal is something that provides a value as specified by
|
||||
/// MaskInfo. If so, replace the specified store with a narrower store of
|
||||
/// truncated IVal.
|
||||
static SDNode *
|
||||
ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
|
||||
SDValue IVal, StoreSDNode *St,
|
||||
@ -8829,10 +8821,10 @@ ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
|
||||
}
|
||||
|
||||
|
||||
/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
|
||||
/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
|
||||
/// of the loaded bits, try narrowing the load and store if it would end up
|
||||
/// being a win for performance or code size.
|
||||
/// Look for sequence of load / op / store where op is one of 'or', 'xor', and
|
||||
/// 'and' of immediates. If 'op' is only touching some of the loaded bits, try
|
||||
/// narrowing the load and store if it would end up being a win for performance
|
||||
/// or code size.
|
||||
SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
|
||||
StoreSDNode *ST = cast<StoreSDNode>(N);
|
||||
if (ST->isVolatile())
|
||||
@ -8953,10 +8945,9 @@ SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
/// TransformFPLoadStorePair - For a given floating point load / store pair,
|
||||
/// if the load value isn't used by any other operations, then consider
|
||||
/// transforming the pair to integer load / store operations if the target
|
||||
/// deems the transformation profitable.
|
||||
/// For a given floating point load / store pair, if the load value isn't used
|
||||
/// by any other operations, then consider transforming the pair to integer
|
||||
/// load / store operations if the target deems the transformation profitable.
|
||||
SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
|
||||
StoreSDNode *ST = cast<StoreSDNode>(N);
|
||||
SDValue Chain = ST->getChain();
|
||||
@ -10997,8 +10988,8 @@ SDValue DAGCombiner::visitINSERT_SUBVECTOR(SDNode *N) {
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
|
||||
/// an AND to a vector_shuffle with the destination vector and a zero vector.
|
||||
/// Returns a vector_shuffle if it able to transform an AND to a vector_shuffle
|
||||
/// with the destination vector and a zero vector.
|
||||
/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
|
||||
/// vector_shuffle V, Zero, <0, 4, 2, 4>
|
||||
SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
|
||||
@ -11044,7 +11035,7 @@ SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
/// SimplifyVBinOp - Visit a binary vector operation, like ADD.
|
||||
/// Visit a binary vector operation, like ADD.
|
||||
SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
|
||||
assert(N->getValueType(0).isVector() &&
|
||||
"SimplifyVBinOp only works on vectors!");
|
||||
@ -11130,7 +11121,7 @@ SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
/// SimplifyVUnaryOp - Visit a binary vector operation, like FABS/FNEG.
|
||||
/// Visit a binary vector operation, like FABS/FNEG.
|
||||
SDValue DAGCombiner::SimplifyVUnaryOp(SDNode *N) {
|
||||
assert(N->getValueType(0).isVector() &&
|
||||
"SimplifyVUnaryOp only works on vectors!");
|
||||
@ -11190,12 +11181,11 @@ SDValue DAGCombiner::SimplifySelect(SDLoc DL, SDValue N0,
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
|
||||
/// are the two values being selected between, see if we can simplify the
|
||||
/// select. Callers of this should assume that TheSelect is deleted if this
|
||||
/// returns true. As such, they should return the appropriate thing (e.g. the
|
||||
/// node) back to the top-level of the DAG combiner loop to avoid it being
|
||||
/// looked at.
|
||||
/// Given a SELECT or a SELECT_CC node, where LHS and RHS are the two values
|
||||
/// being selected between, see if we can simplify the select. Callers of this
|
||||
/// should assume that TheSelect is deleted if this returns true. As such, they
|
||||
/// should return the appropriate thing (e.g. the node) back to the top-level of
|
||||
/// the DAG combiner loop to avoid it being looked at.
|
||||
bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
|
||||
SDValue RHS) {
|
||||
|
||||
@ -11310,7 +11300,7 @@ bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
|
||||
return false;
|
||||
}
|
||||
|
||||
/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
|
||||
/// Simplify an expression of the form (N0 cond N1) ? N2 : N3
|
||||
/// where 'cond' is the comparison specified by CC.
|
||||
SDValue DAGCombiner::SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1,
|
||||
SDValue N2, SDValue N3,
|
||||
@ -11602,7 +11592,7 @@ SDValue DAGCombiner::SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1,
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
|
||||
/// This is a stub for TargetLowering::SimplifySetCC.
|
||||
SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
|
||||
SDValue N1, ISD::CondCode Cond,
|
||||
SDLoc DL, bool foldBooleans) {
|
||||
@ -11611,7 +11601,7 @@ SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
|
||||
return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
|
||||
}
|
||||
|
||||
/// BuildSDIV - Given an ISD::SDIV node expressing a divide by constant, return
|
||||
/// Given an ISD::SDIV node expressing a divide by constant, return
|
||||
/// a DAG expression to select that will generate the same value by multiplying
|
||||
/// by a magic number. See:
|
||||
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
|
||||
@ -11633,9 +11623,8 @@ SDValue DAGCombiner::BuildSDIV(SDNode *N) {
|
||||
return S;
|
||||
}
|
||||
|
||||
/// BuildSDIVPow2 - Given an ISD::SDIV node expressing a divide by constant
|
||||
/// power of 2, return a DAG expression to select that will generate the same
|
||||
/// value by right shifting.
|
||||
/// Given an ISD::SDIV node expressing a divide by constant power of 2, return a
|
||||
/// DAG expression that will generate the same value by right shifting.
|
||||
SDValue DAGCombiner::BuildSDIVPow2(SDNode *N) {
|
||||
ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
|
||||
if (!C)
|
||||
@ -11653,9 +11642,9 @@ SDValue DAGCombiner::BuildSDIVPow2(SDNode *N) {
|
||||
return S;
|
||||
}
|
||||
|
||||
/// BuildUDIV - Given an ISD::UDIV node expressing a divide by constant,
|
||||
/// return a DAG expression to select that will generate the same value by
|
||||
/// multiplying by a magic number. See:
|
||||
/// Given an ISD::UDIV node expressing a divide by constant, return a DAG
|
||||
/// expression that will generate the same value by multiplying by a magic
|
||||
/// number. See:
|
||||
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
|
||||
SDValue DAGCombiner::BuildUDIV(SDNode *N) {
|
||||
ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
|
||||
@ -11675,9 +11664,8 @@ SDValue DAGCombiner::BuildUDIV(SDNode *N) {
|
||||
return S;
|
||||
}
|
||||
|
||||
/// FindBaseOffset - Return true if base is a frame index, which is known not
|
||||
// to alias with anything but itself. Provides base object and offset as
|
||||
// results.
|
||||
/// Return true if base is a frame index, which is known not to alias with
|
||||
/// anything but itself. Provides base object and offset as results.
|
||||
static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
|
||||
const GlobalValue *&GV, const void *&CV) {
|
||||
// Assume it is a primitive operation.
|
||||
@ -11713,8 +11701,7 @@ static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
|
||||
return isa<FrameIndexSDNode>(Base);
|
||||
}
|
||||
|
||||
/// isAlias - Return true if there is any possibility that the two addresses
|
||||
/// overlap.
|
||||
/// Return true if there is any possibility that the two addresses overlap.
|
||||
bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) const {
|
||||
// If they are the same then they must be aliases.
|
||||
if (Op0->getBasePtr() == Op1->getBasePtr()) return true;
|
||||
@ -11804,7 +11791,7 @@ bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) const {
|
||||
return true;
|
||||
}
|
||||
|
||||
/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
|
||||
/// Walk up chain skipping non-aliasing memory nodes,
|
||||
/// looking for aliasing nodes and adding them to the Aliases vector.
|
||||
void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
|
||||
SmallVectorImpl<SDValue> &Aliases) {
|
||||
@ -11944,8 +11931,8 @@ void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
|
||||
}
|
||||
}
|
||||
|
||||
/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
|
||||
/// for a better chain (aliasing node.)
|
||||
/// Walk up chain skipping non-aliasing memory nodes, looking for a better chain
|
||||
/// (aliasing node.)
|
||||
SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
|
||||
SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
|
||||
|
||||
@ -11964,11 +11951,9 @@ SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
|
||||
return DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, Aliases);
|
||||
}
|
||||
|
||||
// SelectionDAG::Combine - This is the entry point for the file.
|
||||
//
|
||||
/// This is the entry point for the file.
|
||||
void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
|
||||
CodeGenOpt::Level OptLevel) {
|
||||
/// run - This is the main entry point to this class.
|
||||
///
|
||||
/// This is the main entry point to this class.
|
||||
DAGCombiner(*this, AA, OptLevel).Run(Level);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user