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Instead of passing in an unsigned value for the optimization level, use an enum,

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which better identifies what the optimization is doing. And is more flexible for
future uses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70440 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2009-04-29 23:29:43 +00:00
parent b587f9662a
commit 98a366d547
81 changed files with 377 additions and 251 deletions
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7
include/llvm/CodeGen/AsmPrinter.h
View File

@ -16,9 +16,10 @@
#ifndef LLVM_CODEGEN_ASMPRINTER_H
#define LLVM_CODEGEN_ASMPRINTER_H
#include "llvm/ADT/DenseMap.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/Support/DataTypes.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/Target/TargetMachine.h"
#include <set>
namespace llvm {
@ -66,7 +67,7 @@ namespace llvm {
std::set<const GlobalValue*> ExtWeakSymbols;
/// OptLevel - Generating code at a specific optimization level.
unsigned OptLevel;
CodeGenOpt::Level OptLevel;
public:
/// Output stream on which we're printing assembly code.
///
@ -111,7 +112,7 @@ namespace llvm {
protected:
explicit AsmPrinter(raw_ostream &o, TargetMachine &TM,
const TargetAsmInfo *T, unsigned OL, bool V);
const TargetAsmInfo *T, CodeGenOpt::Level OL, bool V);
public:
virtual ~AsmPrinter();

3
include/llvm/CodeGen/DwarfWriter.h
View File

@ -21,6 +21,7 @@
#define LLVM_CODEGEN_DWARFWRITER_H
#include "llvm/Pass.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
@ -81,7 +82,7 @@ public:
void EndFunction(MachineFunction *MF);
/// ValidDebugInfo - Return true if V represents valid debug info value.
bool ValidDebugInfo(Value *V, unsigned OptLevel);
bool ValidDebugInfo(Value *V, CodeGenOpt::Level OptLevel);
/// RecordSourceLine - Register a source line with debug info. Returns a
/// unique label ID used to generate a label and provide correspondence to

11
include/llvm/CodeGen/LinkAllCodegenComponents.h
View File

@ -18,6 +18,7 @@
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/CodeGen/GCs.h"
#include "llvm/Target/TargetMachine.h"
namespace {
struct ForceCodegenLinking {
@ -42,11 +43,11 @@ namespace {
llvm::linkOcamlGC();
llvm::linkShadowStackGC();
(void) llvm::createBURRListDAGScheduler(NULL, 3);
(void) llvm::createTDRRListDAGScheduler(NULL, 3);
(void) llvm::createTDListDAGScheduler(NULL, 3);
(void) llvm::createFastDAGScheduler(NULL, 3);
(void) llvm::createDefaultScheduler(NULL, 3);
(void) llvm::createBURRListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
(void) llvm::createTDRRListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
(void) llvm::createTDListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
(void) llvm::createFastDAGScheduler(NULL, llvm::CodeGenOpt::Default);
(void) llvm::createDefaultScheduler(NULL, llvm::CodeGenOpt::Default);
}
} ForceCodegenLinking; // Force link by creating a global definition.

14
include/llvm/CodeGen/SchedulerRegistry.h
View File

@ -16,6 +16,7 @@
#define LLVM_CODEGENSCHEDULERREGISTRY_H
#include "llvm/CodeGen/MachinePassRegistry.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
@ -32,7 +33,8 @@ class MachineBasicBlock;
class RegisterScheduler : public MachinePassRegistryNode {
public:
typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, unsigned);
typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*,
CodeGenOpt::Level);
static MachinePassRegistry Registry;
@ -64,27 +66,27 @@ public:
/// createBURRListDAGScheduler - This creates a bottom up register usage
/// reduction list scheduler.
ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
unsigned OptLevel);
CodeGenOpt::Level OptLevel);
/// createTDRRListDAGScheduler - This creates a top down register usage
/// reduction list scheduler.
ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS,
unsigned OptLevel);
CodeGenOpt::Level OptLevel);
/// createTDListDAGScheduler - This creates a top-down list scheduler with
/// a hazard recognizer.
ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,
unsigned OptLevel);
CodeGenOpt::Level OptLevel);
/// createFastDAGScheduler - This creates a "fast" scheduler.
///
ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
unsigned OptLevel);
CodeGenOpt::Level OptLevel);
/// createDefaultScheduler - This creates an instruction scheduler appropriate
/// for the target.
ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
unsigned OptLevel);
CodeGenOpt::Level OptLevel);
} // end namespace llvm

8
include/llvm/CodeGen/SelectionDAG.h
View File

@ -20,7 +20,7 @@
#include "llvm/ADT/FoldingSet.h"
#include "llvm/ADT/StringMap.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/Target/TargetMachine.h"
#include <cassert>
#include <vector>
#include <map>
@ -30,7 +30,6 @@ namespace llvm {
class AliasAnalysis;
class TargetLowering;
class TargetMachine;
class MachineModuleInfo;
class DwarfWriter;
class MachineFunction;
@ -202,7 +201,8 @@ public:
/// certain types of nodes together, or eliminating superfluous nodes. The
/// Level argument controls whether Combine is allowed to produce nodes and
/// types that are illegal on the target.
void Combine(CombineLevel Level, AliasAnalysis &AA, unsigned OptLevel);
void Combine(CombineLevel Level, AliasAnalysis &AA,
CodeGenOpt::Level OptLevel);
/// LegalizeTypes - This transforms the SelectionDAG into a SelectionDAG that
/// only uses types natively supported by the target. Returns "true" if it
@ -218,7 +218,7 @@ public:
///
/// Note that this is an involved process that may invalidate pointers into
/// the graph.
void Legalize(bool TypesNeedLegalizing, unsigned OptLevel);
void Legalize(bool TypesNeedLegalizing, CodeGenOpt::Level OptLevel);
/// RemoveDeadNodes - This method deletes all unreachable nodes in the
/// SelectionDAG.

5
include/llvm/CodeGen/SelectionDAGISel.h
View File

@ -51,10 +51,11 @@ public:
MachineBasicBlock *BB;
AliasAnalysis *AA;
GCFunctionInfo *GFI;
unsigned OptLevel;
CodeGenOpt::Level OptLevel;
static char ID;
explicit SelectionDAGISel(TargetMachine &tm, unsigned OL = 3);
explicit SelectionDAGISel(TargetMachine &tm,
CodeGenOpt::Level OL = CodeGenOpt::Default);
virtual ~SelectionDAGISel();
TargetLowering &getTargetLowering() { return TLI; }

15
include/llvm/ExecutionEngine/ExecutionEngine.h
View File

@ -18,8 +18,9 @@
#include <vector>
#include <map>
#include <string>
#include "llvm/System/Mutex.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/System/Mutex.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
@ -84,7 +85,7 @@ protected:
// libraries, the JIT and Interpreter set these functions to ctor pointers
// at startup time if they are linked in.
typedef ExecutionEngine *(*EECtorFn)(ModuleProvider*, std::string*,
unsigned OptLevel);
CodeGenOpt::Level OptLevel);
static EECtorFn JITCtor, InterpCtor;
/// LazyFunctionCreator - If an unknown function is needed, this function
@ -114,7 +115,8 @@ public:
static ExecutionEngine *create(ModuleProvider *MP,
bool ForceInterpreter = false,
std::string *ErrorStr = 0,
unsigned OptLevel = 3);
CodeGenOpt::Level OptLevel =
CodeGenOpt::Default);
/// create - This is the factory method for creating an execution engine which
/// is appropriate for the current machine. This takes ownership of the
@ -127,10 +129,9 @@ public:
static ExecutionEngine *createJIT(ModuleProvider *MP,
std::string *ErrorStr = 0,
JITMemoryManager *JMM = 0,
unsigned OptLevel = 3);
CodeGenOpt::Level OptLevel =
CodeGenOpt::Default);
/// addModuleProvider - Add a ModuleProvider to the list of modules that we
/// can JIT from. Note that this takes ownership of the ModuleProvider: when
/// the ExecutionEngine is destroyed, it destroys the MP as well.

45
include/llvm/Target/TargetMachine.h
View File

@ -68,6 +68,19 @@ namespace FileModel {
};
}
// Code generation optimization level.
namespace CodeGenOpt {
enum Level {
Default,
None,
One,
Two,
Size,
Aggressive,
LTO
};
}
//===----------------------------------------------------------------------===//
///
/// TargetMachine - Primary interface to the complete machine description for
@ -213,7 +226,7 @@ public:
virtual FileModel::Model addPassesToEmitFile(PassManagerBase &,
raw_ostream &,
CodeGenFileType,
unsigned /* OptLevel */) {
CodeGenOpt::Level) {
return FileModel::None;
}
@ -223,7 +236,7 @@ public:
///
virtual bool addPassesToEmitFileFinish(PassManagerBase &,
MachineCodeEmitter *,
unsigned /* OptLevel */) {
CodeGenOpt::Level) {
return true;
}
@ -235,7 +248,7 @@ public:
///
virtual bool addPassesToEmitMachineCode(PassManagerBase &,
MachineCodeEmitter &,
unsigned /* OptLevel */) {
CodeGenOpt::Level) {
return true;
}
@ -245,7 +258,7 @@ public:
virtual bool WantsWholeFile() const { return false; }
virtual bool addPassesToEmitWholeFile(PassManager &, raw_ostream &,
CodeGenFileType,
unsigned /* OptLevel */) {
CodeGenOpt::Level) {
return true;
}
};
@ -260,13 +273,13 @@ protected: // Can only create subclasses.
/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
/// both emitting to assembly files or machine code output.
///
bool addCommonCodeGenPasses(PassManagerBase &, unsigned /* OptLevel */);
bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level);
public:
/// addPassesToEmitFile - Add passes to the specified pass manager to get the
/// specified file emitted. Typically this will involve several steps of code
/// generation. If OptLevel is 0, the code generator should emit code as fast
/// generation. If OptLevel is None, the code generator should emit code as fast
/// as possible, though the generated code may be less efficient. This method
/// should return FileModel::Error if emission of this file type is not
/// supported.
@ -278,7 +291,7 @@ public:
virtual FileModel::Model addPassesToEmitFile(PassManagerBase &PM,
raw_ostream &Out,
CodeGenFileType FileType,
unsigned OptLevel);
CodeGenOpt::Level);
/// addPassesToEmitFileFinish - If the passes to emit the specified file had
/// to be split up (e.g., to add an object writer pass), this method can be
@ -286,7 +299,7 @@ public:
///
virtual bool addPassesToEmitFileFinish(PassManagerBase &PM,
MachineCodeEmitter *MCE,
unsigned OptLevel);
CodeGenOpt::Level);
/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
/// get machine code emitted. This uses a MachineCodeEmitter object to handle
@ -296,21 +309,21 @@ public:
///
virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
MachineCodeEmitter &MCE,
unsigned OptLevel);
CodeGenOpt::Level);
/// Target-Independent Code Generator Pass Configuration Options.
/// addInstSelector - This method should add any "last minute" LLVM->LLVM
/// passes, then install an instruction selector pass, which converts from
/// LLVM code to machine instructions.
virtual bool addInstSelector(PassManagerBase &, unsigned /* OptLevel */) {
virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
return true;
}
/// addPreRegAllocPasses - This method may be implemented by targets that want
/// to run passes immediately before register allocation. This should return
/// true if -print-machineinstrs should print after these passes.
virtual bool addPreRegAlloc(PassManagerBase &, unsigned /* OptLevel */) {
virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
return false;
}
@ -318,14 +331,14 @@ public:
/// want to run passes after register allocation but before prolog-epilog
/// insertion. This should return true if -print-machineinstrs should print
/// after these passes.
virtual bool addPostRegAlloc(PassManagerBase &, unsigned /* OptLevel */) {
virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
return false;
}
/// addPreEmitPass - This pass may be implemented by targets that want to run
/// passes immediately before machine code is emitted. This should return
/// true if -print-machineinstrs should print out the code after the passes.
virtual bool addPreEmitPass(PassManagerBase &, unsigned /* OptLevel */) {
virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
return false;
}
@ -333,7 +346,7 @@ public:
/// addAssemblyEmitter - This pass should be overridden by the target to add
/// the asmprinter, if asm emission is supported. If this is not supported,
/// 'true' should be returned.
virtual bool addAssemblyEmitter(PassManagerBase &, unsigned /* OptLevel */,
virtual bool addAssemblyEmitter(PassManagerBase &, CodeGenOpt::Level,
bool /* VerboseAsmDefault */, raw_ostream &) {
return true;
}
@ -341,7 +354,7 @@ public:
/// addCodeEmitter - This pass should be overridden by the target to add a
/// code emitter, if supported. If this is not supported, 'true' should be
/// returned. If DumpAsm is true, the generated assembly is printed to cerr.
virtual bool addCodeEmitter(PassManagerBase &, unsigned /* OptLevel */,
virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
bool /*DumpAsm*/, MachineCodeEmitter &) {
return true;
}
@ -350,7 +363,7 @@ public:
/// a code emitter (without setting flags), if supported. If this is not
/// supported, 'true' should be returned. If DumpAsm is true, the generated
/// assembly is printed to cerr.
virtual bool addSimpleCodeEmitter(PassManagerBase &, unsigned /* OptLevel */,
virtual bool addSimpleCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
bool /*DumpAsm*/, MachineCodeEmitter &) {
return true;
}

3
lib/CodeGen/AsmPrinter/AsmPrinter.cpp
View File

@ -27,7 +27,6 @@
#include "llvm/Target/TargetAsmInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/ADT/SmallPtrSet.h"
@ -42,7 +41,7 @@ AsmVerbose("asm-verbose", cl::desc("Add comments to directives."),
char AsmPrinter::ID = 0;
AsmPrinter::AsmPrinter(raw_ostream &o, TargetMachine &tm,
const TargetAsmInfo *T, unsigned OL, bool VDef)
const TargetAsmInfo *T, CodeGenOpt::Level OL, bool VDef)
: MachineFunctionPass(&ID), FunctionNumber(0), OptLevel(OL), O(o),
TM(tm), TAI(T), TRI(tm.getRegisterInfo()),
IsInTextSection(false)

6
lib/CodeGen/AsmPrinter/DwarfWriter.cpp
View File

@ -3351,7 +3351,7 @@ public:
}
/// ValidDebugInfo - Return true if V represents valid debug info value.
bool ValidDebugInfo(Value *V, unsigned OptLevel) {
bool ValidDebugInfo(Value *V, CodeGenOpt::Level OptLevel) {
if (!V)
return false;
@ -3393,7 +3393,7 @@ public:
case DW_TAG_lexical_block:
/// FIXME. This interfers with the qualitfy of generated code when
/// during optimization.
if (OptLevel != 0)
if (OptLevel != CodeGenOpt::None)
return false;
default:
break;
@ -4731,7 +4731,7 @@ void DwarfWriter::EndFunction(MachineFunction *MF) {
}
/// ValidDebugInfo - Return true if V represents valid debug info value.
bool DwarfWriter::ValidDebugInfo(Value *V, unsigned OptLevel) {
bool DwarfWriter::ValidDebugInfo(Value *V, CodeGenOpt::Level OptLevel) {
return DD && DD->ValidDebugInfo(V, OptLevel);
}

28
lib/CodeGen/LLVMTargetMachine.cpp
View File

@ -55,7 +55,7 @@ FileModel::Model
LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
raw_ostream &Out,
CodeGenFileType FileType,
unsigned OptLevel) {
CodeGenOpt::Level OptLevel) {
// Add common CodeGen passes.
if (addCommonCodeGenPasses(PM, OptLevel))
return FileModel::Error;
@ -69,7 +69,7 @@ LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
if (OptLevel != 0)
if (OptLevel != CodeGenOpt::None)
PM.add(createLoopAlignerPass());
switch (FileType) {
@ -94,7 +94,7 @@ LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
/// finish up adding passes to emit the file, if necessary.
bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
MachineCodeEmitter *MCE,
unsigned OptLevel) {
CodeGenOpt::Level OptLevel) {
if (MCE)
addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE);
@ -114,7 +114,7 @@ bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
///
bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
MachineCodeEmitter &MCE,
unsigned OptLevel) {
CodeGenOpt::Level OptLevel) {
// Add common CodeGen passes.
if (addCommonCodeGenPasses(PM, OptLevel))
return true;
@ -132,15 +132,15 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
return false; // success!
}
/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
/// both emitting to assembly files or machine code output.
/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
/// emitting to assembly files or machine code output.
///
bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
unsigned OptLevel) {
CodeGenOpt::Level OptLevel) {
// Standard LLVM-Level Passes.
// Run loop strength reduction before anything else.
if (OptLevel != 0) {
if (OptLevel != CodeGenOpt::None) {
PM.add(createLoopStrengthReducePass(getTargetLowering()));
if (PrintLSR)
PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
@ -154,7 +154,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
// Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass());
if (OptLevel != 0)
if (OptLevel != CodeGenOpt::None)
PM.add(createCodeGenPreparePass(getTargetLowering()));
PM.add(createStackProtectorPass(getTargetLowering()));
@ -168,7 +168,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
// Enable FastISel with -fast, but allow that to be overridden.
if (EnableFastISelOption == cl::BOU_TRUE ||
(OptLevel == 0 && EnableFastISelOption != cl::BOU_FALSE))
(OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
EnableFastISel = true;
// Ask the target for an isel.
@ -179,7 +179,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
if (PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
if (OptLevel != 0) {
if (OptLevel != CodeGenOpt::None) {
PM.add(createMachineLICMPass());
PM.add(createMachineSinkingPass());
}
@ -192,7 +192,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
PM.add(createRegisterAllocator());
// Perform stack slot coloring.
if (OptLevel != 0)
if (OptLevel != CodeGenOpt::None)
PM.add(createStackSlotColoringPass());
if (PrintMachineCode) // Print the register-allocated code
@ -217,7 +217,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
PM.add(createMachineFunctionPrinterPass(cerr));
// Second pass scheduler.
if (OptLevel != 0 && !DisablePostRAScheduler) {
if (OptLevel != CodeGenOpt::None && !DisablePostRAScheduler) {
PM.add(createPostRAScheduler());
if (PrintMachineCode)
@ -225,7 +225,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
}
// Branch folding must be run after regalloc and prolog/epilog insertion.
if (OptLevel != 0)
if (OptLevel != CodeGenOpt::None)
PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
if (PrintMachineCode)

10
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -57,7 +57,7 @@ namespace {
SelectionDAG &DAG;
const TargetLowering &TLI;
CombineLevel Level;
unsigned OptLevel;
CodeGenOpt::Level OptLevel;
bool LegalOperations;
bool LegalTypes;
@ -254,7 +254,7 @@ namespace {
}
public:
DAGCombiner(SelectionDAG &D, AliasAnalysis &A, unsigned OL)
DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
: DAG(D),
TLI(D.getTargetLoweringInfo()),
Level(Unrestricted),
@ -4784,7 +4784,7 @@ SDValue DAGCombiner::visitLOAD(SDNode *N) {
SDValue Ptr = LD->getBasePtr();
// Try to infer better alignment information than the load already has.
if (OptLevel != 0 && LD->isUnindexed()) {
if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
if (unsigned Align = InferAlignment(Ptr, DAG)) {
if (Align > LD->getAlignment())
return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
@ -4904,7 +4904,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
SDValue Ptr = ST->getBasePtr();
// Try to infer better alignment information than the store already has.
if (OptLevel != 0 && ST->isUnindexed()) {
if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
if (unsigned Align = InferAlignment(Ptr, DAG)) {
if (Align > ST->getAlignment())
return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
@ -6093,7 +6093,7 @@ SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
// SelectionDAG::Combine - This is the entry point for the file.
//
void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
unsigned OptLevel) {
CodeGenOpt::Level OptLevel) {
/// run - This is the main entry point to this class.
///
DAGCombiner(*this, AA, OptLevel).Run(Level);

10
lib/CodeGen/SelectionDAG/FastISel.cpp
View File

@ -327,7 +327,7 @@ bool FastISel::SelectCall(User *I) {
default: break;
case Intrinsic::dbg_stoppoint: {
DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
if (DW && DW->ValidDebugInfo(SPI->getContext(), 0)) {
if (DW && DW->ValidDebugInfo(SPI->getContext(), CodeGenOpt::None)) {
DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
std::string Dir, FN;
unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
@ -344,7 +344,7 @@ bool FastISel::SelectCall(User *I) {
}
case Intrinsic::dbg_region_start: {
DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
if (DW && DW->ValidDebugInfo(RSI->getContext(), 0)) {
if (DW && DW->ValidDebugInfo(RSI->getContext(), CodeGenOpt::None)) {
unsigned ID =
DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext()));
const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
@ -354,7 +354,7 @@ bool FastISel::SelectCall(User *I) {
}
case Intrinsic::dbg_region_end: {
DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
if (DW && DW->ValidDebugInfo(REI->getContext(), 0)) {
if (DW && DW->ValidDebugInfo(REI->getContext(), CodeGenOpt::None)) {
unsigned ID = 0;
DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext()));
if (!Subprogram.isNull() && !Subprogram.describes(MF.getFunction())) {
@ -380,7 +380,7 @@ bool FastISel::SelectCall(User *I) {
DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
Value *SP = FSI->getSubprogram();
if (DW->ValidDebugInfo(SP, 0)) {
if (DW->ValidDebugInfo(SP, CodeGenOpt::None)) {
// llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
// (most?) gdb expects.
DebugLoc PrevLoc = DL;
@ -425,7 +425,7 @@ bool FastISel::SelectCall(User *I) {
case Intrinsic::dbg_declare: {
DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
Value *Variable = DI->getVariable();
if (DW && DW->ValidDebugInfo(Variable, 0)) {
if (DW && DW->ValidDebugInfo(Variable, CodeGenOpt::None)) {
// Determine the address of the declared object.
Value *Address = DI->getAddress();
if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))

11
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -55,7 +55,7 @@ namespace {
class VISIBILITY_HIDDEN SelectionDAGLegalize {
TargetLowering &TLI;
SelectionDAG &DAG;
unsigned OptLevel;
CodeGenOpt::Level OptLevel;
bool TypesNeedLegalizing;
// Libcall insertion helpers.
@ -139,7 +139,7 @@ class VISIBILITY_HIDDEN SelectionDAGLegalize {
public:
explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing,
unsigned ol);
CodeGenOpt::Level ol);
/// getTypeAction - Return how we should legalize values of this type, either
/// it is already legal or we need to expand it into multiple registers of
@ -350,7 +350,7 @@ SelectionDAGLegalize::ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl,
}
SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
bool types, unsigned ol)
bool types, CodeGenOpt::Level ol)
: TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
TypesNeedLegalizing(types), ValueTypeActions(TLI.getValueTypeActions()) {
assert(MVT::LAST_VALUETYPE <= 32 &&
@ -1276,7 +1276,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
unsigned Line = DSP->getLine();
unsigned Col = DSP->getColumn();
if (OptLevel == 0) {
if (OptLevel == CodeGenOpt::None) {
// A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
// won't hurt anything.
if (useDEBUG_LOC) {
@ -8571,7 +8571,8 @@ SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST,
// SelectionDAG::Legalize - This is the entry point for the file.
//
void SelectionDAG::Legalize(bool TypesNeedLegalizing, unsigned OptLevel) {
void SelectionDAG::Legalize(bool TypesNeedLegalizing,
CodeGenOpt::Level OptLevel) {
/// run - This is the main entry point to this class.
///
SelectionDAGLegalize(*this, TypesNeedLegalizing, OptLevel).LegalizeDAG();

2
lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
View File

@ -630,6 +630,6 @@ void ScheduleDAGFast::ListScheduleBottomUp() {
//===----------------------------------------------------------------------===//
llvm::ScheduleDAGSDNodes *
llvm::createFastDAGScheduler(SelectionDAGISel *IS, unsigned) {
llvm::createFastDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
return new ScheduleDAGFast(*IS->MF);
}

2
lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
View File

@ -261,7 +261,7 @@ void ScheduleDAGList::ListScheduleTopDown() {
/// new hazard recognizer. This scheduler takes ownership of the hazard
/// recognizer and deletes it when done.
ScheduleDAGSDNodes *
llvm::createTDListDAGScheduler(SelectionDAGISel *IS, unsigned) {
llvm::createTDListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
return new ScheduleDAGList(*IS->MF,
new LatencyPriorityQueue(),
IS->CreateTargetHazardRecognizer());

4
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
View File

@ -1505,7 +1505,7 @@ bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
//===----------------------------------------------------------------------===//
llvm::ScheduleDAGSDNodes *
llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
const TargetMachine &TM = IS->TM;
const TargetInstrInfo *TII = TM.getInstrInfo();
const TargetRegisterInfo *TRI = TM.getRegisterInfo();
@ -1519,7 +1519,7 @@ llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
}
llvm::ScheduleDAGSDNodes *
llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
const TargetMachine &TM = IS->TM;
const TargetInstrInfo *TII = TM.getInstrInfo();
const TargetRegisterInfo *TRI = TM.getRegisterInfo();

14
lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
View File

@ -45,7 +45,6 @@
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetIntrinsicInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/CommandLine.h"
@ -335,7 +334,8 @@ void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
DwarfWriter *DW = DAG.getDwarfWriter();
DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
if (DW && DW->ValidDebugInfo(SPI->getContext(), false)) {
if (DW && DW->ValidDebugInfo(SPI->getContext(),
CodeGenOpt::Default)) {
DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
std::string Dir, FN;
unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
@ -354,7 +354,7 @@ void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
Value *SP = FSI->getSubprogram();
if (DW->ValidDebugInfo(SP, false)) {
if (DW->ValidDebugInfo(SP, CodeGenOpt::Default)) {
DISubprogram Subprogram(cast<GlobalVariable>(SP));
DICompileUnit CU(Subprogram.getCompileUnit());
std::string Dir, FN;
@ -3899,7 +3899,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
if (DW && DW->ValidDebugInfo(SPI.getContext(), OptLevel)) {
MachineFunction &MF = DAG.getMachineFunction();
if (OptLevel == 0)
if (OptLevel == CodeGenOpt::None)
DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
SPI.getLine(),
SPI.getColumn(),
@ -3940,7 +3940,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
&& strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) {
// This is end of inlined function. Debugging information for
// inlined function is not handled yet (only supported by FastISel).
if (OptLevel == 0) {
if (OptLevel == CodeGenOpt::None) {
unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
if (ID != 0)
// Returned ID is 0 if this is unbalanced "end of inlined
@ -3968,7 +3968,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
Value *SP = FSI.getSubprogram();
if (SP && DW->ValidDebugInfo(SP, OptLevel)) {
MachineFunction &MF = DAG.getMachineFunction();
if (OptLevel == 0) {
if (OptLevel == CodeGenOpt::None) {
// llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
// (most?) gdb expects.
DebugLoc PrevLoc = CurDebugLoc;
@ -4039,7 +4039,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
return 0;
}
case Intrinsic::dbg_declare: {
if (OptLevel == 0) {
if (OptLevel == CodeGenOpt::None) {
DwarfWriter *DW = DAG.getDwarfWriter();
DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
Value *Variable = DI.getVariable();

6
lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
View File

@ -23,6 +23,7 @@
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/Support/CallSite.h"
#include "llvm/Target/TargetMachine.h"
#include <vector>
#include <set>
@ -357,13 +358,14 @@ public:
/// OptLevel - What optimization level we're generating code for.
///
unsigned OptLevel;
CodeGenOpt::Level OptLevel;
/// GFI - Garbage collection metadata for the function.
GCFunctionInfo *GFI;
SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
FunctionLoweringInfo &funcinfo, unsigned ol)
FunctionLoweringInfo &funcinfo,
CodeGenOpt::Level ol)
: CurDebugLoc(DebugLoc::getUnknownLoc()),
TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol) {
}

8
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -136,10 +136,10 @@ namespace llvm {
/// createDefaultScheduler - This creates an instruction scheduler appropriate
/// for the target.
ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
unsigned OptLevel) {
CodeGenOpt::Level OptLevel) {
const TargetLowering &TLI = IS->getTargetLowering();
if (OptLevel == 0)
if (OptLevel == CodeGenOpt::None)
return createFastDAGScheduler(IS, OptLevel);
if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
return createTDListDAGScheduler(IS, OptLevel);
@ -262,7 +262,7 @@ static void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
// SelectionDAGISel code
//===----------------------------------------------------------------------===//
SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, unsigned OL) :
SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) :
FunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
FuncInfo(new FunctionLoweringInfo(TLI)),
CurDAG(new SelectionDAG(TLI, *FuncInfo)),
@ -645,7 +645,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
if (OptLevel != 0)
if (OptLevel != CodeGenOpt::None)
ComputeLiveOutVRegInfo();
// Third, instruction select all of the operations to machine code, adding the

2
lib/ExecutionEngine/ExecutionEngine.cpp
View File

@ -383,7 +383,7 @@ int ExecutionEngine::runFunctionAsMain(Function *Fn,
ExecutionEngine *ExecutionEngine::create(ModuleProvider *MP,
bool ForceInterpreter,
std::string *ErrorStr,
unsigned OptLevel) {
CodeGenOpt::Level OptLevel) {
ExecutionEngine *EE = 0;
// Make sure we can resolve symbols in the program as well. The zero arg

2
lib/ExecutionEngine/ExecutionEngineBindings.cpp
View File

@ -114,7 +114,7 @@ int LLVMCreateInterpreter(LLVMExecutionEngineRef *OutInterp,
int LLVMCreateJITCompiler(LLVMExecutionEngineRef *OutJIT,
LLVMModuleProviderRef MP,
unsigned OptLevel,
CodeGenOpt::Level OptLevel,
char **OutError) {
std::string Error;
if (ExecutionEngine *JIT = ExecutionEngine::createJIT(unwrap(MP), &Error, 0,

2
lib/ExecutionEngine/Interpreter/Interpreter.cpp
View File

@ -37,7 +37,7 @@ namespace llvm {
/// create - Create a new interpreter object. This can never fail.
///
ExecutionEngine *Interpreter::create(ModuleProvider *MP, std::string* ErrStr,
unsigned OptLevel /*unused*/) {
CodeGenOpt::Level OptLevel /*unused*/) {
// Tell this ModuleProvide to materialize and release the module
if (!MP->materializeModule(ErrStr))
// We got an error, just return 0

2
lib/ExecutionEngine/Interpreter/Interpreter.h
View File

@ -108,7 +108,7 @@ public:
/// create - Create an interpreter ExecutionEngine. This can never fail.
///
static ExecutionEngine *create(ModuleProvider *M, std::string *ErrorStr = 0,
unsigned OptLevel /*unused*/ = 3);
CodeGenOpt::Level = CodeGenOpt::Default);
/// run - Start execution with the specified function and arguments.
///

10
lib/ExecutionEngine/JIT/JIT.cpp
View File

@ -196,7 +196,7 @@ void DarwinRegisterFrame(void* FrameBegin) {
ExecutionEngine *ExecutionEngine::createJIT(ModuleProvider *MP,
std::string *ErrorStr,
JITMemoryManager *JMM,
unsigned OptLevel) {
CodeGenOpt::Level OptLevel) {
ExecutionEngine *EE = JIT::createJIT(MP, ErrorStr, JMM, OptLevel);
if (!EE) return 0;
@ -207,7 +207,7 @@ ExecutionEngine *ExecutionEngine::createJIT(ModuleProvider *MP,
}
JIT::JIT(ModuleProvider *MP, TargetMachine &tm, TargetJITInfo &tji,
JITMemoryManager *JMM, unsigned OptLevel)
JITMemoryManager *JMM, CodeGenOpt::Level OptLevel)
: ExecutionEngine(MP), TM(tm), TJI(tji) {
setTargetData(TM.getTargetData());
@ -272,7 +272,7 @@ void JIT::addModuleProvider(ModuleProvider *MP) {
// Turn the machine code intermediate representation into bytes in memory
// that may be executed.
if (TM.addPassesToEmitMachineCode(PM, *MCE, 3 /* OptLevel */)) {
if (TM.addPassesToEmitMachineCode(PM, *MCE, CodeGenOpt::Default)) {
cerr << "Target does not support machine code emission!\n";
abort();
}
@ -305,7 +305,7 @@ Module *JIT::removeModuleProvider(ModuleProvider *MP, std::string *E) {
// Turn the machine code intermediate representation into bytes in memory
// that may be executed.
if (TM.addPassesToEmitMachineCode(PM, *MCE, 3 /* OptLevel */)) {
if (TM.addPassesToEmitMachineCode(PM, *MCE, CodeGenOpt::Default)) {
cerr << "Target does not support machine code emission!\n";
abort();
}
@ -337,7 +337,7 @@ void JIT::deleteModuleProvider(ModuleProvider *MP, std::string *E) {
// Turn the machine code intermediate representation into bytes in memory
// that may be executed.
if (TM.addPassesToEmitMachineCode(PM, *MCE, 3 /* OptLevel */)) {
if (TM.addPassesToEmitMachineCode(PM, *MCE, CodeGenOpt::Default)) {
cerr << "Target does not support machine code emission!\n";
abort();
}

8
lib/ExecutionEngine/JIT/JIT.h
View File

@ -55,7 +55,7 @@ class JIT : public ExecutionEngine {
JITState *jitstate;
JIT(ModuleProvider *MP, TargetMachine &tm, TargetJITInfo &tji,
JITMemoryManager *JMM, unsigned OptLevel);
JITMemoryManager *JMM, CodeGenOpt::Level OptLevel);
public:
~JIT();
@ -71,7 +71,8 @@ public:
/// for the current target. Otherwise, return null.
///
static ExecutionEngine *create(ModuleProvider *MP, std::string *Err,
unsigned OptLevel = 3) {
CodeGenOpt::Level OptLevel =
CodeGenOpt::Default) {
return createJIT(MP, Err, 0, OptLevel);
}
@ -148,7 +149,8 @@ public:
MachineCodeEmitter *getCodeEmitter() const { return MCE; }
static ExecutionEngine *createJIT(ModuleProvider *MP, std::string *Err,
JITMemoryManager *JMM, unsigned OptLevel);
JITMemoryManager *JMM,
CodeGenOpt::Level OptLevel);
private:
static MachineCodeEmitter *createEmitter(JIT &J, JITMemoryManager *JMM);

3
lib/ExecutionEngine/JIT/TargetSelect.cpp
View File

@ -42,7 +42,8 @@ MAttrs("mattr",
/// available for the current target. Otherwise, return null.
///
ExecutionEngine *JIT::createJIT(ModuleProvider *MP, std::string *ErrorStr,
JITMemoryManager *JMM, unsigned OptLevel) {
JITMemoryManager *JMM,
CodeGenOpt::Level OptLevel) {
const TargetMachineRegistry::entry *TheArch = MArch;
if (TheArch == 0) {
std::string Error;

4
lib/Target/ARM/ARM.h
View File

@ -15,6 +15,7 @@
#ifndef TARGET_ARM_H
#define TARGET_ARM_H
#include "llvm/Target/TargetMachine.h"
#include <cassert>
namespace llvm {
@ -91,7 +92,8 @@ inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
FunctionPass *createARMISelDag(ARMTargetMachine &TM);
FunctionPass *createARMCodePrinterPass(raw_ostream &O,
ARMTargetMachine &TM,
unsigned OptLevel, bool Verbose);
CodeGenOpt::Level OptLevel,
bool Verbose);
FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM,
MachineCodeEmitter &MCE);
FunctionPass *createARMLoadStoreOptimizationPass();

21
lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -138,17 +138,20 @@ const TargetAsmInfo *ARMTargetMachine::createTargetAsmInfo() const {
// Pass Pipeline Configuration
bool ARMTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
bool ARMTargetMachine::addInstSelector(PassManagerBase &PM,
CodeGenOpt::Level OptLevel) {
PM.add(createARMISelDag(*this));
return false;
}
bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM,
CodeGenOpt::Level OptLevel) {
// FIXME: temporarily disabling load / store optimization pass for Thumb mode.
if (OptLevel != 0 && !DisableLdStOpti && !Subtarget.isThumb())
if (OptLevel != CodeGenOpt::None && !DisableLdStOpti && !Subtarget.isThumb())
PM.add(createARMLoadStoreOptimizationPass());
if (OptLevel != 0 && !DisableIfConversion && !Subtarget.isThumb())
if (OptLevel != CodeGenOpt::None &&
!DisableIfConversion && !Subtarget.isThumb())
PM.add(createIfConverterPass());
PM.add(createARMConstantIslandPass());
@ -156,7 +159,7 @@ bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
}
bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
unsigned OptLevel,
CodeGenOpt::Level OptLevel,
bool Verbose,
raw_ostream &Out) {
// Output assembly language.
@ -168,8 +171,10 @@ bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
}
bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE) {
bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
bool DumpAsm,
MachineCodeEmitter &MCE) {
// FIXME: Move this to TargetJITInfo!
if (DefRelocModel == Reloc::Default)
setRelocationModel(Reloc::Static);
@ -186,7 +191,7 @@ bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
}
bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
unsigned OptLevel,
CodeGenOpt::Level OptLevel,
bool DumpAsm,
MachineCodeEmitter &MCE) {
// Machine code emitter pass for ARM.

18
lib/Target/ARM/ARMTargetMachine.h
View File

@ -41,7 +41,8 @@ protected:
// set this functions to ctor pointer at startup time if they are linked in.
typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
ARMTargetMachine &tm,
unsigned OptLevel, bool verbose);
CodeGenOpt::Level OptLevel,
bool verbose);
static AsmPrinterCtorFn AsmPrinterCtor;
public:
@ -69,14 +70,17 @@ public:
virtual const TargetAsmInfo *createTargetAsmInfo() const;
// Pass Pipeline Configuration
virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addAssemblyEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE);
virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE);
virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
bool DumpAsm,
MachineCodeEmitter &MCE);
};
/// ThumbTargetMachine - Thumb target machine.

6
lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
View File

@ -81,7 +81,8 @@ namespace {
bool InCPMode;
public:
explicit ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
const TargetAsmInfo *T, unsigned OL, bool V)
const TargetAsmInfo *T, CodeGenOpt::Level OL,
bool V)
: AsmPrinter(O, TM, T, OL, V), DW(0), MMI(NULL), AFI(NULL), MCP(NULL),
InCPMode(false) {
Subtarget = &TM.getSubtarget<ARMSubtarget>();
@ -1061,7 +1062,8 @@ bool ARMAsmPrinter::doFinalization(Module &M) {
///
FunctionPass *llvm::createARMCodePrinterPass(raw_ostream &o,
ARMTargetMachine &tm,
unsigned OptLevel, bool verbose) {
CodeGenOpt::Level OptLevel,
bool verbose) {
return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
}

6
lib/Target/Alpha/Alpha.h
View File

@ -15,18 +15,20 @@
#ifndef TARGET_ALPHA_H
#define TARGET_ALPHA_H
#include "llvm/Target/TargetMachine.h"
namespace llvm {
class AlphaTargetMachine;
class FunctionPass;
class TargetMachine;
class MachineCodeEmitter;
class raw_ostream;
FunctionPass *createAlphaISelDag(AlphaTargetMachine &TM);
FunctionPass *createAlphaCodePrinterPass(raw_ostream &OS,
TargetMachine &TM,
unsigned OptLevel, bool Verbose);
CodeGenOpt::Level OptLevel,
bool Verbose);
FunctionPass *createAlphaPatternInstructionSelector(TargetMachine &TM);
FunctionPass *createAlphaCodeEmitterPass(AlphaTargetMachine &TM,
MachineCodeEmitter &MCE);

12
lib/Target/Alpha/AlphaTargetMachine.cpp
View File

@ -77,25 +77,26 @@ AlphaTargetMachine::AlphaTargetMachine(const Module &M, const std::string &FS)
//===----------------------------------------------------------------------===//
bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM,
unsigned OptLevel) {
CodeGenOpt::Level OptLevel) {
PM.add(createAlphaISelDag(*this));
return false;
}
bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM,
unsigned OptLevel) {
CodeGenOpt::Level OptLevel) {
// Must run branch selection immediately preceding the asm printer
PM.add(createAlphaBranchSelectionPass());
return false;
}
bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
unsigned OptLevel,
CodeGenOpt::Level OptLevel,
bool Verbose,
raw_ostream &Out) {
PM.add(createAlphaLLRPPass(*this));
PM.add(createAlphaCodePrinterPass(Out, *this, OptLevel, Verbose));
return false;
}
bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE) {
PM.add(createAlphaCodeEmitterPass(*this, MCE));
if (DumpAsm)
@ -103,7 +104,8 @@ bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
return false;
}
bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
unsigned OptLevel, bool DumpAsm,
CodeGenOpt::Level OptLevel,
bool DumpAsm,
MachineCodeEmitter &MCE) {
return addCodeEmitter(PM, OptLevel, DumpAsm, MCE);
}

15
lib/Target/Alpha/AlphaTargetMachine.h
View File

@ -58,14 +58,17 @@ public:
static unsigned getModuleMatchQuality(const Module &M);
// Pass Pipeline Configuration
virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addAssemblyEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE);
virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE);
virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
bool DumpAsm,
MachineCodeEmitter &MCE);
};
} // end namespace llvm

5
lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
View File

@ -37,7 +37,8 @@ namespace {
///
explicit AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
const TargetAsmInfo *T, unsigned OL, bool V)
const TargetAsmInfo *T, CodeGenOpt::Level OL,
bool V)
: AsmPrinter(o, tm, T, OL, V) {}
virtual const char *getPassName() const {
@ -68,7 +69,7 @@ namespace {
///
FunctionPass *llvm::createAlphaCodePrinterPass(raw_ostream &o,
TargetMachine &tm,
unsigned OptLevel,
CodeGenOpt::Level OptLevel,
bool verbose) {
return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
}

2
lib/Target/CBackend/CBackend.cpp
View File

@ -3587,7 +3587,7 @@ void CWriter::visitExtractValueInst(ExtractValueInst &EVI) {
bool CTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
raw_ostream &o,
CodeGenFileType FileType,
unsigned OptLevel) {
CodeGenOpt::Level OptLevel) {
if (FileType != TargetMachine::AssemblyFile) return true;
PM.add(createGCLoweringPass());

2
lib/Target/CBackend/CTargetMachine.h
View File

@ -28,7 +28,7 @@ struct CTargetMachine : public TargetMachine {
virtual bool WantsWholeFile() const { return true; }
virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
CodeGenFileType FileType,
unsigned OptLevel);
CodeGenOpt::Level OptLevel);
// This class always works, but must be requested explicitly on
// llc command line.

11
lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
View File

@ -49,7 +49,8 @@ namespace {
std::set<std::string> FnStubs, GVStubs;
public:
explicit SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
const TargetAsmInfo *T, unsigned OL, bool V) :
const TargetAsmInfo *T, CodeGenOpt::Level OL,
bool V) :
AsmPrinter(O, TM, T, OL, V) {}
virtual const char *getPassName() const {
@ -288,8 +289,9 @@ namespace {
DwarfWriter *DW;
MachineModuleInfo *MMI;
public:
LinuxAsmPrinter(raw_ostream &O, SPUTargetMachine &TM,
const TargetAsmInfo *T, bool F, bool V)
explicit LinuxAsmPrinter(raw_ostream &O, SPUTargetMachine &TM,
const TargetAsmInfo *T, CodeGenOpt::Level F,
bool V)
: SPUAsmPrinter(O, TM, T, F, V), DW(0), MMI(0) {}
virtual const char *getPassName() const {
@ -615,6 +617,7 @@ bool LinuxAsmPrinter::doFinalization(Module &M) {
///
FunctionPass *llvm::createSPUAsmPrinterPass(raw_ostream &o,
SPUTargetMachine &tm,
unsigned OptLevel, bool verbose) {
CodeGenOpt::Level OptLevel,
bool verbose) {
return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
}

4
lib/Target/CellSPU/SPU.h
View File

@ -16,6 +16,7 @@
#define LLVM_TARGET_IBMCELLSPU_H
#include "llvm/Support/DataTypes.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
class SPUTargetMachine;
@ -25,7 +26,8 @@ namespace llvm {
FunctionPass *createSPUISelDag(SPUTargetMachine &TM);
FunctionPass *createSPUAsmPrinterPass(raw_ostream &o,
SPUTargetMachine &tm,
unsigned OptLevel, bool verbose);
CodeGenOpt::Level OptLevel,
bool verbose);
/*--== Utility functions/predicates/etc used all over the place: --==*/
//! Predicate test for a signed 10-bit value

5
lib/Target/CellSPU/SPUTargetMachine.cpp
View File

@ -81,7 +81,8 @@ SPUTargetMachine::SPUTargetMachine(const Module &M, const std::string &FS)
//===----------------------------------------------------------------------===//
bool
SPUTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel)
SPUTargetMachine::addInstSelector(PassManagerBase &PM,
CodeGenOpt::Level OptLevel)
{
// Install an instruction selector.
PM.add(createSPUISelDag(*this));
@ -89,7 +90,7 @@ SPUTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel)
}
bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
unsigned OptLevel,
CodeGenOpt::Level OptLevel,
bool Verbose,
raw_ostream &Out) {
PM.add(createSPUAsmPrinterPass(Out, *this, OptLevel, Verbose));

6
lib/Target/CellSPU/SPUTargetMachine.h
View File

@ -83,8 +83,10 @@ public:
}
// Pass Pipeline Configuration
virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
virtual bool addInstSelector(PassManagerBase &PM,
CodeGenOpt::Level OptLevel);
virtual bool addAssemblyEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
};

2
lib/Target/CppBackend/CPPBackend.cpp
View File

@ -1995,7 +1995,7 @@ char CppWriter::ID = 0;
bool CPPTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
raw_ostream &o,
CodeGenFileType FileType,
unsigned OptLevel) {
CodeGenOpt::Level OptLevel) {
if (FileType != TargetMachine::AssemblyFile) return true;
PM.add(new CppWriter(o));
return false;

2
lib/Target/CppBackend/CPPTargetMachine.h
View File

@ -30,7 +30,7 @@ struct CPPTargetMachine : public TargetMachine {
virtual bool WantsWholeFile() const { return true; }
virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
CodeGenFileType FileType,
unsigned OptLevel);
CodeGenOpt::Level OptLevel);
// This class always works, but shouldn't be the default in most cases.
static unsigned getModuleMatchQuality(const Module &M) { return 1; }

6
lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
View File

@ -25,7 +25,6 @@
#include "llvm/CodeGen/DwarfWriter.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/Target/TargetAsmInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/Mangler.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/Statistic.h"
@ -38,7 +37,8 @@ namespace {
std::set<std::string> ExternalFunctionNames, ExternalObjectNames;
public:
explicit IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
const TargetAsmInfo *T, unsigned OL, bool V)
const TargetAsmInfo *T, CodeGenOpt::Level OL,
bool V)
: AsmPrinter(O, TM, T, OL, V) {}
virtual const char *getPassName() const {
@ -370,7 +370,7 @@ bool IA64AsmPrinter::doFinalization(Module &M) {
///
FunctionPass *llvm::createIA64CodePrinterPass(raw_ostream &o,
IA64TargetMachine &tm,
unsigned OptLevel,
CodeGenOpt::Level OptLevel,
bool verbose) {
return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
}

5
lib/Target/IA64/IA64.h
View File

@ -14,6 +14,8 @@
#ifndef TARGET_IA64_H
#define TARGET_IA64_H
#include "llvm/Target/TargetMachine.h"
namespace llvm {
class IA64TargetMachine;
@ -37,7 +39,8 @@ FunctionPass *createIA64BundlingPass(IA64TargetMachine &TM);
///
FunctionPass *createIA64CodePrinterPass(raw_ostream &o,
IA64TargetMachine &tm,
unsigned OptLevel, bool verbose);
CodeGenOpt::Level OptLevel,
bool verbose);
} // End llvm namespace

8
lib/Target/IA64/IA64TargetMachine.cpp
View File

@ -72,18 +72,20 @@ IA64TargetMachine::IA64TargetMachine(const Module &M, const std::string &FS)
// Pass Pipeline Configuration
//===----------------------------------------------------------------------===//
bool IA64TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLEvel){
bool IA64TargetMachine::addInstSelector(PassManagerBase &PM,
CodeGenOpt::Level OptLevel){
PM.add(createIA64DAGToDAGInstructionSelector(*this));
return false;
}
bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM,
CodeGenOpt::Level OptLevel) {
// Make sure everything is bundled happily
PM.add(createIA64BundlingPass(*this));
return true;
}
bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
unsigned OptLevel,
CodeGenOpt::Level OptLevel,
bool Verbose,
raw_ostream &Out) {
PM.add(createIA64CodePrinterPass(Out, *this, OptLevel, Verbose));

7
lib/Target/IA64/IA64TargetMachine.h
View File

@ -51,9 +51,10 @@ public:
static unsigned getModuleMatchQuality(const Module &M);
// Pass Pipeline Configuration
virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addAssemblyEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
};
} // End llvm namespace

4
lib/Target/MSIL/MSILWriter.cpp
View File

@ -36,7 +36,7 @@ namespace {
virtual bool WantsWholeFile() const { return true; }
virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
CodeGenFileType FileType,
unsigned OptLevel);
CodeGenOpt::Level OptLevel);
// This class always works, but shouldn't be the default in most cases.
static unsigned getModuleMatchQuality(const Module &M) { return 1; }
@ -1664,7 +1664,7 @@ void MSILWriter::printExternals() {
bool MSILTarget::addPassesToEmitWholeFile(PassManager &PM, raw_ostream &o,
CodeGenFileType FileType,
unsigned OptLevel)
CodeGenOpt::Level OptLevel)
{
if (FileType != TargetMachine::AssemblyFile) return true;
MSILWriter* Writer = new MSILWriter(o);

6
lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
View File

@ -50,7 +50,8 @@ namespace {
const MipsSubtarget *Subtarget;
public:
explicit MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM,
const TargetAsmInfo *T, unsigned OL, bool V)
const TargetAsmInfo *T, CodeGenOpt::Level OL,
bool V)
: AsmPrinter(O, TM, T, OL, V) {
Subtarget = &TM.getSubtarget<MipsSubtarget>();
}
@ -91,7 +92,8 @@ namespace {
/// regardless of whether the function is in SSA form.
FunctionPass *llvm::createMipsCodePrinterPass(raw_ostream &o,
MipsTargetMachine &tm,
unsigned OptLevel, bool verbose) {
CodeGenOpt::Level OptLevel,
bool verbose) {
return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
}

5
lib/Target/Mips/Mips.h
View File

@ -15,6 +15,8 @@
#ifndef TARGET_MIPS_H
#define TARGET_MIPS_H
#include "llvm/Target/TargetMachine.h"
namespace llvm {
class MipsTargetMachine;
class FunctionPass;
@ -25,7 +27,8 @@ namespace llvm {
FunctionPass *createMipsDelaySlotFillerPass(MipsTargetMachine &TM);
FunctionPass *createMipsCodePrinterPass(raw_ostream &OS,
MipsTargetMachine &TM,
unsigned OptLevel, bool Verbose);
CodeGenOpt::Level OptLevel,
bool Verbose);
} // end namespace llvm;
// Defines symbolic names for Mips registers. This defines a mapping from

6
lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -105,7 +105,7 @@ getModuleMatchQuality(const Module &M)
// Install an instruction selector pass using
// the ISelDag to gen Mips code.
bool MipsTargetMachine::
addInstSelector(PassManagerBase &PM, unsigned OptLevel)
addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
{
PM.add(createMipsISelDag(*this));
return false;
@ -115,7 +115,7 @@ addInstSelector(PassManagerBase &PM, unsigned OptLevel)
// machine code is emitted. return true if -print-machineinstrs should
// print out the code after the passes.
bool MipsTargetMachine::
addPreEmitPass(PassManagerBase &PM, unsigned OptLevel)
addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
{
PM.add(createMipsDelaySlotFillerPass(*this));
return true;
@ -124,7 +124,7 @@ addPreEmitPass(PassManagerBase &PM, unsigned OptLevel)
// Implements the AssemblyEmitter for the target. Must return
// true if AssemblyEmitter is supported
bool MipsTargetMachine::
addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
addAssemblyEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out)
{
// Output assembly language.

9
lib/Target/Mips/MipsTargetMachine.h
View File

@ -57,9 +57,12 @@ namespace llvm {
static unsigned getModuleMatchQuality(const Module &M);
// Pass Pipeline Configuration
virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
virtual bool addInstSelector(PassManagerBase &PM,
CodeGenOpt::Level OptLevel);
virtual bool addPreEmitPass(PassManagerBase &PM,
CodeGenOpt::Level OptLevel);
virtual bool addAssemblyEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
};

4
lib/Target/PIC16/PIC16.h
View File

@ -15,6 +15,7 @@
#ifndef LLVM_TARGET_PIC16_H
#define LLVM_TARGET_PIC16_H
#include "llvm/Target/TargetMachine.h"
#include <iosfwd>
#include <cassert>
@ -75,7 +76,8 @@ namespace PIC16CC {
FunctionPass *createPIC16ISelDag(PIC16TargetMachine &TM);
FunctionPass *createPIC16CodePrinterPass(raw_ostream &OS,
PIC16TargetMachine &TM,
unsigned OptLevel, bool Verbose);
CodeGenOpt::Level OptLevel,
bool Verbose);
} // end namespace llvm;
// Defines symbolic names for PIC16 registers. This defines a mapping from

2
lib/Target/PIC16/PIC16AsmPrinter.cpp
View File

@ -161,7 +161,7 @@ bool PIC16AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
///
FunctionPass *llvm::createPIC16CodePrinterPass(raw_ostream &o,
PIC16TargetMachine &tm,
unsigned OptLevel,
CodeGenOpt::Level OptLevel,
bool verbose) {
return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
}

3
lib/Target/PIC16/PIC16AsmPrinter.h
View File

@ -25,7 +25,8 @@
namespace llvm {
struct VISIBILITY_HIDDEN PIC16AsmPrinter : public AsmPrinter {
explicit PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
const TargetAsmInfo *T, unsigned OL, bool V)
const TargetAsmInfo *T, CodeGenOpt::Level OL,
bool V)
: AsmPrinter(O, TM, T, OL, V) {
CurBank = "";
FunctionLabelBegin = '@';

6
lib/Target/PIC16/PIC16TargetMachine.cpp
View File

@ -56,15 +56,15 @@ const TargetAsmInfo *PIC16TargetMachine::createTargetAsmInfo() const {
}
bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM,
unsigned OptLevel) {
CodeGenOpt::Level OptLevel) {
// Install an instruction selector.
PM.add(createPIC16ISelDag(*this));
return false;
}
bool PIC16TargetMachine::
addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool Verbose,
raw_ostream &Out) {
addAssemblyEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out) {
// Output assembly language.
PM.add(createPIC16CodePrinterPass(Out, *this, OptLevel, Verbose));
return false;

6
lib/Target/PIC16/PIC16TargetMachine.h
View File

@ -57,8 +57,10 @@ public:
return const_cast<PIC16TargetLowering*>(&TLInfo);
}
virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
virtual bool addInstSelector(PassManagerBase &PM,
CodeGenOpt::Level OptLevel);
virtual bool addAssemblyEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
}; // PIC16TargetMachine.

12
lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
View File

@ -55,7 +55,8 @@ namespace {
const PPCSubtarget &Subtarget;
public:
explicit PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
const TargetAsmInfo *T, unsigned OL, bool V)
const TargetAsmInfo *T, CodeGenOpt::Level OL,
bool V)
: AsmPrinter(O, TM, T, OL, V),
Subtarget(TM.getSubtarget<PPCSubtarget>()) {}
@ -298,7 +299,8 @@ namespace {
MachineModuleInfo *MMI;
public:
explicit PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
const TargetAsmInfo *T, unsigned OL, bool V)
const TargetAsmInfo *T, CodeGenOpt::Level OL,
bool V)
: PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {}
virtual const char *getPassName() const {
@ -327,7 +329,8 @@ namespace {
raw_ostream &OS;
public:
explicit PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
const TargetAsmInfo *T, unsigned OL, bool V)
const TargetAsmInfo *T, CodeGenOpt::Level OL,
bool V)
: PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0), OS(O) {}
virtual const char *getPassName() const {
@ -1176,7 +1179,8 @@ bool PPCDarwinAsmPrinter::doFinalization(Module &M) {
///
FunctionPass *llvm::createPPCAsmPrinterPass(raw_ostream &o,
PPCTargetMachine &tm,
unsigned OptLevel, bool verbose) {
CodeGenOpt::Level OptLevel,
bool verbose) {
const PPCSubtarget *Subtarget = &tm.getSubtarget<PPCSubtarget>();
if (Subtarget->isDarwin()) {

4
lib/Target/PowerPC/PPC.h
View File

@ -18,6 +18,8 @@
// GCC #defines PPC on Linux but we use it as our namespace name
#undef PPC
#include "llvm/Target/TargetMachine.h"
namespace llvm {
class PPCTargetMachine;
class FunctionPass;
@ -28,7 +30,7 @@ FunctionPass *createPPCBranchSelectionPass();
FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
FunctionPass *createPPCAsmPrinterPass(raw_ostream &OS,
PPCTargetMachine &TM,
unsigned OptLevel, bool Verbose);
CodeGenOpt::Level OptLevel, bool Verbose);
FunctionPass *createPPCCodeEmitterPass(PPCTargetMachine &TM,
MachineCodeEmitter &MCE);
} // end namespace llvm;

15
lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@ -129,21 +129,22 @@ PPC64TargetMachine::PPC64TargetMachine(const Module &M, const std::string &FS)
// Pass Pipeline Configuration
//===----------------------------------------------------------------------===//
bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,
CodeGenOpt::Level OptLevel) {
// Install an instruction selector.
PM.add(createPPCISelDag(*this));
return false;
}
bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM,
CodeGenOpt::Level OptLevel) {
// Must run branch selection immediately preceding the asm printer.
PM.add(createPPCBranchSelectionPass());
return false;
}
bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
unsigned OptLevel,
CodeGenOpt::Level OptLevel,
bool Verbose,
raw_ostream &Out) {
assert(AsmPrinterCtor && "AsmPrinter was not linked in");
@ -153,7 +154,8 @@ bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
return false;
}
bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE) {
// The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
// FIXME: This should be moved to TargetJITInfo!!
@ -184,7 +186,8 @@ bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
return false;
}
bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE) {
// Machine code emitter pass for PowerPC.
PM.add(createPPCCodeEmitterPass(*this, MCE));

15
lib/Target/PowerPC/PPCTargetMachine.h
View File

@ -46,7 +46,8 @@ protected:
// set this functions to ctor pointer at startup time if they are linked in.
typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
PPCTargetMachine &tm,
unsigned OptLevel, bool verbose);
CodeGenOpt::Level OptLevel,
bool verbose);
static AsmPrinterCtorFn AsmPrinterCtor;
public:
@ -76,13 +77,15 @@ public:
}
// Pass Pipeline Configuration
virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addAssemblyEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE);
virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE);
virtual bool getEnableTailMergeDefault() const;
};

5
lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
View File

@ -49,7 +49,8 @@ namespace {
ValueMapTy NumberForBB;
public:
explicit SparcAsmPrinter(raw_ostream &O, TargetMachine &TM,
const TargetAsmInfo *T, unsigned OL, bool V)
const TargetAsmInfo *T, CodeGenOpt::Level OL,
bool V)
: AsmPrinter(O, TM, T, OL, V) {}
virtual const char *getPassName() const {
@ -82,7 +83,7 @@ namespace {
///
FunctionPass *llvm::createSparcCodePrinterPass(raw_ostream &o,
TargetMachine &tm,
unsigned OptLevel,
CodeGenOpt::Level OptLevel,
bool verbose) {
return new SparcAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
}

5
lib/Target/Sparc/Sparc.h
View File

@ -15,17 +15,18 @@
#ifndef TARGET_SPARC_H
#define TARGET_SPARC_H
#include "llvm/Target/TargetMachine.h"
#include <cassert>
namespace llvm {
class FunctionPass;
class TargetMachine;
class SparcTargetMachine;
class raw_ostream;
FunctionPass *createSparcISelDag(SparcTargetMachine &TM);
FunctionPass *createSparcCodePrinterPass(raw_ostream &OS, TargetMachine &TM,
unsigned OptLevel, bool Verbose);
CodeGenOpt::Level OptLevel,
bool Verbose);
FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM);
FunctionPass *createSparcFPMoverPass(TargetMachine &TM);
} // end namespace llvm;

7
lib/Target/Sparc/SparcTargetMachine.cpp
View File

@ -69,7 +69,7 @@ unsigned SparcTargetMachine::getModuleMatchQuality(const Module &M) {
}
bool SparcTargetMachine::addInstSelector(PassManagerBase &PM,
unsigned OptLevel) {
CodeGenOpt::Level OptLevel) {
PM.add(createSparcISelDag(*this));
return false;
}
@ -77,14 +77,15 @@ bool SparcTargetMachine::addInstSelector(PassManagerBase &PM,
/// addPreEmitPass - This pass may be implemented by targets that want to run
/// passes immediately before machine code is emitted. This should return
/// true if -print-machineinstrs should print out the code after the passes.
bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel){
bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM,
CodeGenOpt::Level OptLevel){
PM.add(createSparcFPMoverPass(*this));
PM.add(createSparcDelaySlotFillerPass(*this));
return true;
}
bool SparcTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
unsigned OptLevel,
CodeGenOpt::Level OptLevel,
bool Verbose,
raw_ostream &Out) {
// Output assembly language.

7
lib/Target/Sparc/SparcTargetMachine.h
View File

@ -51,9 +51,10 @@ public:
static unsigned getModuleMatchQuality(const Module &M);
// Pass Pipeline Configuration
virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addAssemblyEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
};

3
lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
View File

@ -34,7 +34,8 @@ class VISIBILITY_HIDDEN X86ATTAsmPrinter : public AsmPrinter {
const X86Subtarget *Subtarget;
public:
explicit X86ATTAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
const TargetAsmInfo *T, unsigned OL, bool V)
const TargetAsmInfo *T, CodeGenOpt::Level OL,
bool V)
: AsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {
Subtarget = &TM.getSubtarget<X86Subtarget>();
}

3
lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
View File

@ -25,7 +25,8 @@ using namespace llvm;
///
FunctionPass *llvm::createX86CodePrinterPass(raw_ostream &o,
X86TargetMachine &tm,
unsigned OptLevel, bool verbose) {
CodeGenOpt::Level OptLevel,
bool verbose) {
const X86Subtarget *Subtarget = &tm.getSubtarget<X86Subtarget>();
if (Subtarget->isFlavorIntel()) {

3
lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
View File

@ -26,7 +26,8 @@ namespace llvm {
struct VISIBILITY_HIDDEN X86IntelAsmPrinter : public AsmPrinter {
explicit X86IntelAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
const TargetAsmInfo *T, unsigned OL, bool V)
const TargetAsmInfo *T, CodeGenOpt::Level OL,
bool V)
: AsmPrinter(O, TM, T, OL, V) {}
virtual const char *getPassName() const {

7
lib/Target/X86/X86.h
View File

@ -15,6 +15,8 @@
#ifndef TARGET_X86_H
#define TARGET_X86_H
#include "llvm/Target/TargetMachine.h"
namespace llvm {
class X86TargetMachine;
@ -25,7 +27,7 @@ class raw_ostream;
/// createX86ISelDag - This pass converts a legalized DAG into a
/// X86-specific DAG, ready for instruction scheduling.
///
FunctionPass *createX86ISelDag(X86TargetMachine &TM, unsigned OptSize);
FunctionPass *createX86ISelDag(X86TargetMachine &TM, CodeGenOpt::Level OptLevel);
/// createX86FloatingPointStackifierPass - This function returns a pass which
/// converts floating point register references and pseudo instructions into
@ -44,7 +46,8 @@ FunctionPass *createX87FPRegKillInserterPass();
///
FunctionPass *createX86CodePrinterPass(raw_ostream &o,
X86TargetMachine &tm,
unsigned OptLevel, bool Verbose);
CodeGenOpt::Level OptLevel,
bool Verbose);
/// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
/// to the specified MCE object.

9
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -134,7 +134,7 @@ namespace {
bool OptForSize;
public:
explicit X86DAGToDAGISel(X86TargetMachine &tm, unsigned OptLevel)
explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
: SelectionDAGISel(tm, OptLevel),
TM(tm), X86Lowering(*TM.getTargetLowering()),
Subtarget(&TM.getSubtarget<X86Subtarget>()),
@ -306,7 +306,7 @@ static inline bool isNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse) {
bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
SDNode *Root) const {
if (OptLevel == 0) return false;
if (OptLevel == CodeGenOpt::None) return false;
if (U == Root)
switch (U->getOpcode()) {
@ -714,7 +714,7 @@ void X86DAGToDAGISel::InstructionSelect() {
OptForSize = F->hasFnAttr(Attribute::OptimizeForSize);
DEBUG(BB->dump());
if (OptLevel != 0)
if (OptLevel != CodeGenOpt::None)
PreprocessForRMW();
// FIXME: This should only happen when not compiled with -O0.
@ -1744,6 +1744,7 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
/// createX86ISelDag - This pass converts a legalized DAG into a
/// X86-specific DAG, ready for instruction scheduling.
///
FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, unsigned OptLevel) {
FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
llvm::CodeGenOpt::Level OptLevel) {
return new X86DAGToDAGISel(TM, OptLevel);
}

17
lib/Target/X86/X86TargetMachine.cpp
View File

@ -180,7 +180,8 @@ X86TargetMachine::X86TargetMachine(const Module &M, const std::string &FS,
// Pass Pipeline Configuration
//===----------------------------------------------------------------------===//
bool X86TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
bool X86TargetMachine::addInstSelector(PassManagerBase &PM,
CodeGenOpt::Level OptLevel) {
// Install an instruction selector.
PM.add(createX86ISelDag(*this, OptLevel));
@ -194,20 +195,22 @@ bool X86TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
return false;
}
bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, unsigned OptLevel) {
bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM,
CodeGenOpt::Level OptLevel) {
// Calculate and set max stack object alignment early, so we can decide
// whether we will need stack realignment (and thus FP).
PM.add(createX86MaxStackAlignmentCalculatorPass());
return false; // -print-machineinstr shouldn't print after this.
}
bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM, unsigned OptLevel) {
bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM,
CodeGenOpt::Level OptLevel) {
PM.add(createX86FloatingPointStackifierPass());
return true; // -print-machineinstr should print after this.
}
bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
unsigned OptLevel,
CodeGenOpt::Level OptLevel,
bool Verbose,
raw_ostream &Out) {
assert(AsmPrinterCtor && "AsmPrinter was not linked in");
@ -216,7 +219,8 @@ bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
return false;
}
bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE) {
// FIXME: Move this to TargetJITInfo!
// On Darwin, do not override 64-bit setting made in X86TargetMachine().
@ -245,7 +249,8 @@ bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
}
bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
unsigned OptLevel, bool DumpAsm,
CodeGenOpt::Level OptLevel,
bool DumpAsm,
MachineCodeEmitter &MCE) {
PM.add(createX86CodeEmitterPass(*this, MCE));
if (DumpAsm) {

17
lib/Target/X86/X86TargetMachine.h
View File

@ -45,7 +45,8 @@ protected:
// set this functions to ctor pointer at startup time if they are linked in.
typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
X86TargetMachine &tm,
unsigned OptLevel, bool verbose);
CodeGenOpt::Level OptLevel,
bool verbose);
static AsmPrinterCtorFn AsmPrinterCtor;
public:
@ -74,14 +75,16 @@ public:
}
// Set up the pass pipeline.
virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
virtual bool addPreRegAlloc(PassManagerBase &PM, unsigned OptLevel);
virtual bool addPostRegAlloc(PassManagerBase &PM, unsigned OptLevel);
virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addAssemblyEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE);
virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE);
/// symbolicAddressesAreRIPRel - Return true if symbolic addresses are

5
lib/Target/XCore/XCore.h
View File

@ -15,6 +15,8 @@
#ifndef TARGET_XCORE_H
#define TARGET_XCORE_H
#include "llvm/Target/TargetMachine.h"
namespace llvm {
class FunctionPass;
class TargetMachine;
@ -24,7 +26,8 @@ namespace llvm {
FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM);
FunctionPass *createXCoreCodePrinterPass(raw_ostream &OS,
XCoreTargetMachine &TM,
unsigned OptLevel, bool Verbose);
CodeGenOpt::Level OptLevel,
bool Verbose);
} // end namespace llvm;
// Defines symbolic names for XCore registers. This defines a mapping from

7
lib/Target/XCore/XCoreAsmPrinter.cpp
View File

@ -57,8 +57,9 @@ namespace {
DwarfWriter *DW;
const XCoreSubtarget &Subtarget;
public:
XCoreAsmPrinter(raw_ostream &O, XCoreTargetMachine &TM,
const TargetAsmInfo *T, unsigned OL, bool V)
explicit XCoreAsmPrinter(raw_ostream &O, XCoreTargetMachine &TM,
const TargetAsmInfo *T, CodeGenOpt::Level OL,
bool V)
: AsmPrinter(O, TM, T, OL, V), DW(0),
Subtarget(*TM.getSubtargetImpl()) {}
@ -105,7 +106,7 @@ namespace {
///
FunctionPass *llvm::createXCoreCodePrinterPass(raw_ostream &o,
XCoreTargetMachine &tm,
unsigned OptLevel,
CodeGenOpt::Level OptLevel,
bool verbose) {
return new XCoreAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
}

4
lib/Target/XCore/XCoreTargetMachine.cpp
View File

@ -56,13 +56,13 @@ unsigned XCoreTargetMachine::getModuleMatchQuality(const Module &M) {
}
bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM,
unsigned OptLevel) {
CodeGenOpt::Level OptLevel) {
PM.add(createXCoreISelDag(*this));
return false;
}
bool XCoreTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
unsigned OptLevel,
CodeGenOpt::Level OptLevel,
bool Verbose,
raw_ostream &Out) {
// Output assembly language.

5
lib/Target/XCore/XCoreTargetMachine.h
View File

@ -52,8 +52,9 @@ public:
static unsigned getModuleMatchQuality(const Module &M);
// Pass Pipeline Configuration
virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addAssemblyEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
};

25
tools/llc/llc.cpp
View File

@ -56,12 +56,12 @@ OutputFilename("o", cl::desc("Output filename"), cl::value_desc("filename"));
static cl::opt<bool> Force("f", cl::desc("Overwrite output files"));
// Determine optimization level. Level -O0 is equivalent to "fast" code gen.
static cl::opt<unsigned>
static cl::opt<char>
OptLevel("O",
cl::desc("Optimization level. Similar to llvm-gcc -O. (default: -O3)"),
cl::desc("Optimization level. Similar to llvm-gcc -O."),
cl::Prefix,
cl::ZeroOrMore,
cl::init(3));
cl::init(' '));
static cl::opt<std::string>
TargetTriple("mtriple", cl::desc("Override target triple for module"));
@ -253,6 +253,19 @@ int main(int argc, char **argv) {
raw_ostream *Out = GetOutputStream(argv[0]);
if (Out == 0) return 1;
CodeGenOpt::Level OLvl = CodeGenOpt::Aggressive;
switch (OptLevel) {
default:
case ' ': break;
case '0': OLvl = CodeGenOpt::None; break;
case '1': OLvl = CodeGenOpt::One; break;
case '2': OLvl = CodeGenOpt::Two; break;
case 's': OLvl = CodeGenOpt::Size; break;
case '3': OLvl = CodeGenOpt::Aggressive; break;
case '4': OLvl = CodeGenOpt::LTO; break;
}
// If this target requires addPassesToEmitWholeFile, do it now. This is
// used by strange things like the C backend.
if (Target.WantsWholeFile()) {
@ -262,7 +275,7 @@ int main(int argc, char **argv) {
PM.add(createVerifierPass());
// Ask the target to add backend passes as necessary.
if (Target.addPassesToEmitWholeFile(PM, *Out, FileType, OptLevel)) {
if (Target.addPassesToEmitWholeFile(PM, *Out, FileType, OLvl)) {
std::cerr << argv[0] << ": target does not support generation of this"
<< " file type!\n";
if (Out != &outs()) delete Out;
@ -288,7 +301,7 @@ int main(int argc, char **argv) {
// Override default to generate verbose assembly.
Target.setAsmVerbosityDefault(true);
switch (Target.addPassesToEmitFile(Passes, *Out, FileType, OptLevel)) {
switch (Target.addPassesToEmitFile(Passes, *Out, FileType, OLvl)) {
default:
assert(0 && "Invalid file model!");
return 1;
@ -309,7 +322,7 @@ int main(int argc, char **argv) {
break;
}
if (Target.addPassesToEmitFileFinish(Passes, MCE, OptLevel)) {
if (Target.addPassesToEmitFileFinish(Passes, MCE, OLvl)) {
std::cerr << argv[0] << ": target does not support generation of this"
<< " file type!\n";
if (Out != &outs()) delete Out;

4
tools/lli/lli.cpp
View File

@ -122,7 +122,9 @@ int main(int argc, char **argv, char * const *envp) {
if (!TargetTriple.empty())
Mod->setTargetTriple(TargetTriple);
EE = ExecutionEngine::create(MP, ForceInterpreter, &ErrorMsg, Fast);
EE = ExecutionEngine::create(MP, ForceInterpreter, &ErrorMsg,
Fast ?
CodeGenOpt::None : CodeGenOpt::Aggressive);
if (!EE && !ErrorMsg.empty()) {
std::cerr << argv[0] << ":error creating EE: " << ErrorMsg << "\n";
exit(1);

6
tools/lto/LTOCodeGenerator.cpp
View File

@ -442,7 +442,8 @@ bool LTOCodeGenerator::generateAssemblyCode(raw_ostream& out,
MachineCodeEmitter* mce = NULL;
switch (_target->addPassesToEmitFile(*codeGenPasses, out,
TargetMachine::AssemblyFile, 3)) {
TargetMachine::AssemblyFile,
CodeGenOpt::Default)) {
case FileModel::MachOFile:
mce = AddMachOWriter(*codeGenPasses, out, *_target);
break;
@ -457,7 +458,8 @@ bool LTOCodeGenerator::generateAssemblyCode(raw_ostream& out,
return true;
}
if (_target->addPassesToEmitFileFinish(*codeGenPasses, mce, 3)) {
if (_target->addPassesToEmitFileFinish(*codeGenPasses, mce,
CodeGenOpt::Default)) {
errMsg = "target does not support generation of this file type";
return true;
}

2
utils/TableGen/AsmWriterEmitter.cpp
View File

@ -650,7 +650,7 @@ void AsmWriterEmitter::run(std::ostream &O) {
O << "\";\n\n";
O << " if (TAI->doesSupportDebugInformation() &&\n"
<< " DW->ShouldEmitDwarfDebug() && OptLevel != 0) {\n"
<< " DW->ShouldEmitDwarfDebug() && OptLevel != CodeGenOpt::None) {\n"
<< " DebugLoc CurDL = MI->getDebugLoc();\n\n"
<< " if (!CurDL.isUnknown()) {\n"
<< " static DebugLocTuple PrevDLT(~0U, ~0U, ~0U);\n"

2
utils/TableGen/DAGISelEmitter.cpp
View File

@ -465,7 +465,7 @@ public:
NumInputRootOps = N->getNumChildren();
if (DisablePatternForFastISel(N, CGP))
emitCheck("OptLevel != 0");
emitCheck("OptLevel != CodeGenOpt::None");
emitCheck(PredicateCheck);
}