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eliminate PreprocessForRMW now that isel handles it.
We still preprocess calls and fp return stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97598 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -207,7 +207,7 @@ namespace {
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SDValue &Index, SDValue &Disp,
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SDValue &Segment);
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void PreprocessForRMW();
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void PreprocessForCallLoads();
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void PreprocessForFPConvert();
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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@ -352,57 +352,6 @@ X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
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return true;
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}
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/// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand
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/// and move load below the TokenFactor. Replace store's chain operand with
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/// load's chain result.
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static void MoveBelowTokenFactor(SelectionDAG *CurDAG, SDValue Load,
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SDValue Store, SDValue TF) {
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SmallVector<SDValue, 4> Ops;
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for (unsigned i = 0, e = TF.getNode()->getNumOperands(); i != e; ++i)
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if (Load.getNode() == TF.getOperand(i).getNode())
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Ops.push_back(Load.getOperand(0));
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else
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Ops.push_back(TF.getOperand(i));
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SDValue NewTF = CurDAG->UpdateNodeOperands(TF, &Ops[0], Ops.size());
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SDValue NewLoad = CurDAG->UpdateNodeOperands(Load, NewTF,
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Load.getOperand(1),
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Load.getOperand(2));
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CurDAG->UpdateNodeOperands(Store, NewLoad.getValue(1), Store.getOperand(1),
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Store.getOperand(2), Store.getOperand(3));
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}
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/// isRMWLoad - Return true if N is a load that's part of RMW sub-DAG. The
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/// chain produced by the load must only be used by the store's chain operand,
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/// otherwise this may produce a cycle in the DAG.
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///
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static bool isRMWLoad(SDValue N, SDValue Chain, SDValue Address,
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SDValue &Load) {
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if (N.getOpcode() == ISD::BIT_CONVERT) {
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if (!N.hasOneUse())
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return false;
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N = N.getOperand(0);
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}
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LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
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if (!LD || LD->isVolatile())
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return false;
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if (LD->getAddressingMode() != ISD::UNINDEXED)
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return false;
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ISD::LoadExtType ExtType = LD->getExtensionType();
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if (ExtType != ISD::NON_EXTLOAD && ExtType != ISD::EXTLOAD)
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return false;
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if (N.hasOneUse() &&
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LD->hasNUsesOfValue(1, 1) &&
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N.getOperand(1) == Address &&
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LD->isOperandOf(Chain.getNode())) {
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Load = N;
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return true;
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}
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return false;
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}
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/// MoveBelowCallSeqStart - Replace CALLSEQ_START operand with load's chain
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/// operand and move load below the call's chain operand.
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static void MoveBelowCallSeqStart(SelectionDAG *CurDAG, SDValue Load,
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@ -467,95 +416,37 @@ static bool isCalleeLoad(SDValue Callee, SDValue &Chain) {
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}
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void X86DAGToDAGISel::PreprocessForRMW() {
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void X86DAGToDAGISel::PreprocessForCallLoads() {
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for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
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E = CurDAG->allnodes_end(); I != E; ++I) {
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if (I->getOpcode() == X86ISD::CALL) {
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/// Also try moving call address load from outside callseq_start to just
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/// before the call to allow it to be folded.
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///
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/// [Load chain]
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/// ^
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/// |
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/// [Load]
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/// ^ ^
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/// | |
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/// / \--
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/// / |
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///[CALLSEQ_START] |
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/// ^ |
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/// | |
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/// [LOAD/C2Reg] |
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/// | |
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/// \ /
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/// \ /
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/// [CALL]
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SDValue Chain = I->getOperand(0);
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SDValue Load = I->getOperand(1);
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if (!isCalleeLoad(Load, Chain))
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continue;
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MoveBelowCallSeqStart(CurDAG, Load, SDValue(I, 0), Chain);
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++NumLoadMoved;
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if (I->getOpcode() != X86ISD::CALL)
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continue;
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}
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continue;
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if (!ISD::isNON_TRUNCStore(I))
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continue;
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/// Also try moving call address load from outside callseq_start to just
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/// before the call to allow it to be folded.
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///
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/// [Load chain]
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/// ^
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/// |
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/// [Load]
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/// ^ ^
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/// | |
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/// / \--
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/// / |
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///[CALLSEQ_START] |
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/// ^ |
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/// | |
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/// [LOAD/C2Reg] |
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/// | |
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/// \ /
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/// \ /
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/// [CALL]
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SDValue Chain = I->getOperand(0);
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if (Chain.getNode()->getOpcode() != ISD::TokenFactor)
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SDValue Load = I->getOperand(1);
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if (!isCalleeLoad(Load, Chain))
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continue;
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SDValue N1 = I->getOperand(1);
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SDValue N2 = I->getOperand(2);
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if ((N1.getValueType().isFloatingPoint() &&
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!N1.getValueType().isVector()) ||
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!N1.hasOneUse())
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continue;
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bool RModW = false;
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SDValue Load;
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unsigned Opcode = N1.getNode()->getOpcode();
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switch (Opcode) {
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case ISD::ADD:
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case ISD::MUL:
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case ISD::AND:
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case ISD::OR:
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case ISD::XOR:
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case ISD::ADDC:
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case ISD::ADDE:
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case ISD::VECTOR_SHUFFLE: {
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SDValue N10 = N1.getOperand(0);
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SDValue N11 = N1.getOperand(1);
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RModW = isRMWLoad(N10, Chain, N2, Load);
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if (!RModW)
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RModW = isRMWLoad(N11, Chain, N2, Load);
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break;
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}
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case ISD::SUB:
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case ISD::SHL:
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case ISD::SRA:
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case ISD::SRL:
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case ISD::ROTL:
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case ISD::ROTR:
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case ISD::SUBC:
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case ISD::SUBE:
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case X86ISD::SHLD:
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case X86ISD::SHRD: {
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SDValue N10 = N1.getOperand(0);
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RModW = isRMWLoad(N10, Chain, N2, Load);
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break;
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}
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}
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if (RModW) {
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MoveBelowTokenFactor(CurDAG, Load, SDValue(I, 0), Chain);
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++NumLoadMoved;
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checkForCycles(I);
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}
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MoveBelowCallSeqStart(CurDAG, Load, SDValue(I, 0), Chain);
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++NumLoadMoved;
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}
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}
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@ -631,7 +522,7 @@ void X86DAGToDAGISel::PreprocessISelDAG() {
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OptForSize = MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize);
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if (OptLevel != CodeGenOpt::None)
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PreprocessForRMW();
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PreprocessForCallLoads();
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// FIXME: This should only happen when not compiled with -O0.
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PreprocessForFPConvert();
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