RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-11-28 06:00:30 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Add custom conversion from v2u32 to v2f32 in 32-bit mode

Browse Source 
- As there's no 64-bit GPRs in 32-bit mode, a custom conversion from v2u32 to
  v2f32 is added to improve the efficiency of the code generated.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166545 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Michael Liao 2012-10-24 04:09:32 +00:00
parent 2ef5bd3ba6
commit 991b6a22b6
3 changed files with 35 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
lib/Target/X86/X86ISelLowering.cpp
View File

@ -950,6 +950,10 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
// As there is no 64-bit GPR available, we need build a special custom
// sequence to convert from v2i32 to v2f32.
if (!Subtarget->is64Bit())
setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
@ -11754,6 +11758,22 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
}
return;
}
case ISD::UINT_TO_FP: {
if (N->getOperand(0).getValueType() != MVT::v2i32 &&
N->getValueType(0) != MVT::v2f32)
return;
SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
N->getOperand(0));
SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
MVT::f64);
SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
return;
}
case ISD::FP_ROUND: {
SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
Results.push_back(V);

4
lib/Target/X86/X86InstrSSE.td
View File

@ -5882,6 +5882,8 @@ let Predicates = [HasAVX] in {
(VPMOVZXDQrm addr:$src)>;
def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
(VPMOVZXDQrm addr:$src)>;
def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
(VPMOVZXDQrm addr:$src)>;
}
let Predicates = [UseSSE41] in {
@ -5914,6 +5916,8 @@ let Predicates = [UseSSE41] in {
(PMOVZXDQrm addr:$src)>;
def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
(PMOVZXDQrm addr:$src)>;
def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
(PMOVZXDQrm addr:$src)>;
}
//===----------------------------------------------------------------------===//

11
test/CodeGen/X86/cvtv2f32.ll Normal file
View File

@ -0,0 +1,11 @@
; RUN: llc < %s -mtriple=i686-linux-pc -mcpu=corei7 | FileCheck %s
define <2 x float> @bar(<2 x i32> %in) {
%r = uitofp <2 x i32> %in to <2 x float>
ret <2 x float> %r
; CHECK: bar
; CHECK: or
; CHECK: subpd
; CHECK: cvtpd2ps
; CHECK: ret
}