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Prepare support for AltiVec multiply, divide, and sqrt.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24700 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2005-12-13 22:55:22 +00:00
parent 328ead9fce
commit 993aeb2ed9
3 changed files with 19 additions and 2 deletions
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4
lib/Target/PowerPC/PPCISelLowering.h
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@ -39,6 +39,10 @@ namespace llvm {
/// of that FP value.
FCTIDZ, FCTIWZ,
// VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
// three v4f32 operands and producing a v4f32 result.
VMADDFP, VNMSUBFP,
/// Hi/Lo - These represent the high and low 16-bit parts of a global
/// address respectively. These nodes have two operands, the first of
/// which must be a TargetGlobalAddress, and the second of which must be a

14
lib/Target/PowerPC/PPCInstrInfo.td
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@ -27,8 +27,10 @@ def PPCfsel : SDNode<"PPCISD::FSEL",
SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
// amounts. These nodes are generated by the multi-precision shift code.
@ -949,6 +951,14 @@ def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
(ADDIS GPRC:$in, tconstpool:$g)>;
// Fused multiply add and multiply sub for packed float. These are represented
// separately from the real instructions above, for operations that must have
// the additional precision, such as Newton-Rhapson (used by divide, sqrt)
def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
(VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
(VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
// Standard shifts. These are represented separately from the real shifts above
// so that we can distinguish between shifts that allow 5-bit and 6-bit shift
// amounts.

3
lib/Target/TargetSelectionDAG.td
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@ -82,6 +82,9 @@ def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
]>;
def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
]>;
def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
SDTCisSameAs<0, 1>, SDTCisInt<0>
]>;