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don't bother making x&-1 only to simplify it in dag combine. This commonly occurs expanding i64 ops.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46383 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2008-01-26 01:05:42 +00:00
parent 6bccafdfae
commit 9967c15183
1 changed files with 2 additions and 0 deletions
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2
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -1877,6 +1877,8 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
// worth handling here.
if (N2C && N2C->getValue() == 0)
return N2;
if (N2C && N2C->isAllOnesValue()) // X & -1 -> X
return N1;
break;
case ISD::OR:
case ISD::XOR: