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Move duplicated AddLiveIn function from X86 and ARM backends to be a method
in the MachineFunction class, renaming it to addLiveIn for consistency with the same method in MachineBasicBlock. Thanks for Anton for suggesting this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69615 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -33,6 +33,7 @@ class MachineFrameInfo;
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class MachineConstantPool;
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class MachineJumpTableInfo;
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class TargetMachine;
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class TargetRegisterClass;
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template <>
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struct ilist_traits<MachineBasicBlock>
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@ -238,6 +239,10 @@ public:
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typedef std::reverse_iterator<const_iterator> const_reverse_iterator;
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typedef std::reverse_iterator<iterator> reverse_iterator;
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/// addLiveIn - Add the specified physical register as a live-in value and
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/// create a corresponding virtual register for it.
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unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC);
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//===--------------------------------------------------------------------===//
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// BasicBlock accessor functions.
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//
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@ -385,6 +385,16 @@ MachineFunction& MachineFunction::get(const Function *F)
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return *mc;
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}
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/// addLiveIn - Add the specified physical register as a live-in value and
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/// create a corresponding virtual register for it.
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unsigned MachineFunction::addLiveIn(unsigned PReg,
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const TargetRegisterClass *RC) {
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assert(RC->contains(PReg) && "Not the correct regclass!");
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unsigned VReg = getRegInfo().createVirtualRegister(RC);
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getRegInfo().addLiveIn(PReg, VReg);
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return VReg;
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}
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/// getOrCreateDebugLocID - Look up the DebugLocTuple index with the given
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/// source file, line, and column. If none currently exists, create a new
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/// DebugLocTuple, and insert it into the DebugIdMap.
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@ -1053,17 +1053,6 @@ static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
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return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
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}
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/// AddLiveIn - This helper function adds the specified physical register to the
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/// MachineFunction as a live-in value. It also creates a corresponding virtual
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/// register for it.
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static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
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const TargetRegisterClass *RC) {
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assert(RC->contains(PReg) && "Not the correct regclass!");
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unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
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MF.getRegInfo().addLiveIn(PReg, VReg);
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return VReg;
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}
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SDValue
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ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
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MachineFunction &MF = DAG.getMachineFunction();
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@ -1101,7 +1090,7 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
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assert(0 && "RegVT not supported by FORMAL_ARGUMENTS Lowering");
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// Transform the arguments stored in physical registers into virtual ones.
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unsigned Reg = AddLiveIn(MF, VA.getLocReg(), RC);
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unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
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SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
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// f64 is passed in i32 pairs and must be combined.
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@ -1118,7 +1107,7 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
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SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
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ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0);
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} else {
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Reg = AddLiveIn(MF, VA.getLocReg(), RC);
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Reg = MF.addLiveIn(VA.getLocReg(), RC);
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ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
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}
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@ -1195,7 +1184,7 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
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else
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RC = ARM::GPRRegisterClass;
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unsigned VReg = AddLiveIn(MF, GPRArgRegs[NumGPRs], RC);
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unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
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SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
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SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
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MemOps.push_back(Store);
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@ -1147,17 +1147,6 @@ LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
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// For info on fast calling convention see Fast Calling Convention (tail call)
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// implementation LowerX86_32FastCCCallTo.
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/// AddLiveIn - This helper function adds the specified physical register to the
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/// MachineFunction as a live in value. It also creates a corresponding virtual
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/// register for it.
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static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
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const TargetRegisterClass *RC) {
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assert(RC->contains(PReg) && "Not the correct regclass!");
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unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
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MF.getRegInfo().addLiveIn(PReg, VReg);
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return VReg;
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}
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/// CallIsStructReturn - Determines whether a CALL node uses struct return
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/// semantics.
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static bool CallIsStructReturn(CallSDNode *TheCall) {
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@ -1356,7 +1345,7 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
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assert(0 && "Unknown argument type!");
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}
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unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
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unsigned Reg = DAG.getMachineFunction().addLiveIn(VA.getLocReg(), RC);
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SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
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// If this is an 8 or 16-bit value, it is really passed promoted to 32
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@ -1472,8 +1461,8 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
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SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
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DAG.getIntPtrConstant(VarArgsGPOffset));
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for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
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unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
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X86::GR64RegisterClass);
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unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
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X86::GR64RegisterClass);
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SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i64);
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SDValue Store =
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DAG.getStore(Val.getValue(1), dl, Val, FIN,
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@ -1487,8 +1476,8 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
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FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
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DAG.getIntPtrConstant(VarArgsFPOffset));
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for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
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unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
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X86::VR128RegisterClass);
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unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
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X86::VR128RegisterClass);
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SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::v4f32);
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SDValue Store =
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DAG.getStore(Val.getValue(1), dl, Val, FIN,
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