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disallow direct access to SDValue::ResNo, provide a getter instead

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55394 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Gabor Greif 2008-08-26 22:36:50 +00:00
parent 13269335a5
commit 99a6cb92d1
17 changed files with 77 additions and 73 deletions
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8
include/llvm/CodeGen/SelectionDAGNodes.h
View File

@ -811,11 +811,15 @@ namespace ISD {
class SDValue {
public:
SDNode *Val; // The node defining the value we are using.
private:
unsigned ResNo; // Which return value of the node we are using.
public:
SDValue() : Val(0), ResNo(0) {}
SDValue(SDNode *val, unsigned resno) : Val(val), ResNo(resno) {}
/// get the index which selects a specific result in the SDNode
unsigned getResNo() const { return ResNo; }
bool operator==(const SDValue &O) const {
return Val == O.Val && ResNo == O.ResNo;
}
@ -882,7 +886,7 @@ template<> struct DenseMapInfo<SDValue> {
}
static unsigned getHashValue(const SDValue &Val) {
return ((unsigned)((uintptr_t)Val.Val >> 4) ^
(unsigned)((uintptr_t)Val.Val >> 9)) + Val.ResNo;
(unsigned)((uintptr_t)Val.Val >> 9)) + Val.getResNo();
}
static bool isEqual(const SDValue &LHS, const SDValue &RHS) {
return LHS == RHS;

4
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -2730,7 +2730,7 @@ static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
SDNode *User = *UI;
for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
SDValue UseOp = User->getOperand(i);
if (UseOp.Val == N && UseOp.ResNo == 0) {
if (UseOp.Val == N && UseOp.getResNo() == 0) {
BothLiveOut = true;
break;
}
@ -3366,7 +3366,7 @@ static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
SDValue Elt = N->getOperand(i);
if (Elt.getOpcode() != ISD::MERGE_VALUES)
return Elt.Val;
return Elt.getOperand(Elt.ResNo).Val;
return Elt.getOperand(Elt.getResNo()).Val;
}
/// CombineConsecutiveLoads - build_pair (load, load) -> load

46
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -821,7 +821,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
return Result.getValue(Op.ResNo);
return Result.getValue(Op.getResNo());
}
// Otherwise this is an unhandled builtin node. splat.
#ifndef NDEBUG
@ -901,7 +901,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
Tmp2 = LegalizeOp(Result.getValue(1));
AddLegalizedOperand(Op.getValue(0), Tmp1);
AddLegalizedOperand(Op.getValue(1), Tmp2);
return Op.ResNo ? Tmp2 : Tmp1;
return Op.getResNo() ? Tmp2 : Tmp1;
case ISD::EHSELECTION: {
Tmp1 = LegalizeOp(Node->getOperand(0));
Tmp2 = LegalizeOp(Node->getOperand(1));
@ -935,7 +935,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
Tmp2 = LegalizeOp(Result.getValue(1));
AddLegalizedOperand(Op.getValue(0), Tmp1);
AddLegalizedOperand(Op.getValue(1), Tmp2);
return Op.ResNo ? Tmp2 : Tmp1;
return Op.getResNo() ? Tmp2 : Tmp1;
case ISD::EH_RETURN: {
MVT VT = Node->getValueType(0);
// The only "good" option for this node is to custom lower it.
@ -959,7 +959,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
break;
case ISD::MERGE_VALUES:
// Legalize eliminates MERGE_VALUES nodes.
Result = Node->getOperand(Op.ResNo);
Result = Node->getOperand(Op.getResNo());
break;
case ISD::CopyFromReg:
Tmp1 = LegalizeOp(Node->getOperand(0));
@ -980,7 +980,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
// legalized both of them.
AddLegalizedOperand(Op.getValue(0), Result);
AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
return Result.getValue(Op.ResNo);
return Result.getValue(Op.getResNo());
case ISD::UNDEF: {
MVT VT = Op.getValueType();
switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
@ -1025,7 +1025,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
// legalized both of them.
AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
return Result.getValue(Op.ResNo);
return Result.getValue(Op.getResNo());
}
case ISD::DBG_STOPPOINT:
@ -1199,7 +1199,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
}
AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
return Result.getValue(Op.ResNo);
return Result.getValue(Op.getResNo());
}
case ISD::ATOMIC_LOAD_ADD:
case ISD::ATOMIC_LOAD_SUB:
@ -1232,7 +1232,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
}
AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
return Result.getValue(Op.ResNo);
return Result.getValue(Op.getResNo());
}
case ISD::Constant: {
ConstantSDNode *CN = cast<ConstantSDNode>(Node);
@ -1331,7 +1331,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
if (Tmp3.Val->getValueType(i) == MVT::Flag)
continue;
Tmp1 = LegalizeOp(Tmp3.getValue(i));
if (Op.ResNo == i)
if (Op.getResNo() == i)
Tmp2 = Tmp1;
AddLegalizedOperand(SDValue(Node, i), Tmp1);
}
@ -1625,7 +1625,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
if (Node->getNumValues() == 2)
AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
return Result.getValue(Op.ResNo);
return Result.getValue(Op.getResNo());
case ISD::DYNAMIC_STACKALLOC: {
MVT VT = Node->getValueType(0);
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
@ -1684,7 +1684,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
// legalized both of them.
AddLegalizedOperand(SDValue(Node, 0), Tmp1);
AddLegalizedOperand(SDValue(Node, 1), Tmp2);
return Op.ResNo ? Tmp2 : Tmp1;
return Op.getResNo() ? Tmp2 : Tmp1;
}
case ISD::INLINEASM: {
SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
@ -1720,7 +1720,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
// INLINE asm returns a chain and flag, make sure to add both to the map.
AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
return Result.getValue(Op.ResNo);
return Result.getValue(Op.getResNo());
}
case ISD::BR:
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
@ -1935,7 +1935,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
// legalized both of them.
AddLegalizedOperand(SDValue(Node, 0), Tmp3);
AddLegalizedOperand(SDValue(Node, 1), Tmp4);
return Op.ResNo ? Tmp4 : Tmp3;
return Op.getResNo() ? Tmp4 : Tmp3;
} else {
MVT SrcVT = LD->getMemoryVT();
unsigned SrcWidth = SrcVT.getSizeInBits();
@ -2124,7 +2124,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
// both of them.
AddLegalizedOperand(SDValue(Node, 0), Tmp1);
AddLegalizedOperand(SDValue(Node, 1), Tmp2);
return Op.ResNo ? Tmp2 : Tmp1;
return Op.getResNo() ? Tmp2 : Tmp1;
}
}
case ISD::EXTRACT_ELEMENT: {
@ -2215,7 +2215,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
Result = LegalizeOp(Result);
} else {
SDNode *InVal = Tmp2.Val;
int InIx = Tmp2.ResNo;
int InIx = Tmp2.getResNo();
unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
MVT EVT = InVal->getValueType(InIx).getVectorElementType();
@ -2411,7 +2411,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
// in the high half of the vector.
if (ST->getValue().getValueType().isVector()) {
SDNode *InVal = ST->getValue().Val;
int InIx = ST->getValue().ResNo;
int InIx = ST->getValue().getResNo();
MVT InVT = InVal->getValueType(InIx);
unsigned NumElems = InVT.getVectorNumElements();
MVT EVT = InVT.getVectorElementType();
@ -2619,7 +2619,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
// legalized both of them.
AddLegalizedOperand(SDValue(Node, 0), Tmp1);
AddLegalizedOperand(SDValue(Node, 1), Tmp2);
return Op.ResNo ? Tmp2 : Tmp1;
return Op.getResNo() ? Tmp2 : Tmp1;
case ISD::STACKRESTORE:
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
@ -2875,7 +2875,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
Tmp2 = LegalizeOp(Tmp1.getValue(i));
AddLegalizedOperand(SDValue(Node, i), Tmp2);
if (i == Op.ResNo)
if (i == Op.getResNo())
RetVal = Tmp2;
}
assert(RetVal.Val && "Illegal result number");
@ -2888,7 +2888,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
// legalized all of them.
for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
return Result.getValue(Op.ResNo);
return Result.getValue(Op.getResNo());
}
// Binary operators
@ -3278,7 +3278,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
// legalized both of them.
AddLegalizedOperand(SDValue(Node, 0), Result);
AddLegalizedOperand(SDValue(Node, 1), Tmp1);
return Op.ResNo ? Tmp1 : Result;
return Op.getResNo() ? Tmp1 : Result;
}
case ISD::VACOPY:
@ -3574,7 +3574,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
// The input has to be a vector type, we have to either scalarize it, pack
// it, or convert it based on whether the input vector type is legal.
SDNode *InVal = Node->getOperand(0).Val;
int InIx = Node->getOperand(0).ResNo;
int InIx = Node->getOperand(0).getResNo();
unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
MVT EVT = InVal->getValueType(InIx).getVectorElementType();
@ -3876,7 +3876,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
Result = LegalizeOp(Result);
AddLegalizedOperand(SDValue(Node, 0), Result);
AddLegalizedOperand(SDValue(Node, 1), Tmp1);
return Op.ResNo ? Tmp1 : Result;
return Op.getResNo() ? Tmp1 : Result;
}
case ISD::FLT_ROUNDS_: {
MVT VT = Node->getValueType(0);
@ -5808,7 +5808,7 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
break;
}
// FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
assert(Op.ResNo == 0 && Node->getNumValues() == 2 &&
assert(Op.getResNo() == 0 && Node->getNumValues() == 2 &&
Op.getValue(1).getValueType() == MVT::Other &&
"unhandled MERGE_VALUES");
ExpandOp(Op.getOperand(0), Lo, Hi);

14
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
View File

@ -62,7 +62,7 @@ static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
if (TargetRegisterInfo::isVirtualRegister(Reg))
return;
unsigned ResNo = User->getOperand(2).ResNo;
unsigned ResNo = User->getOperand(2).getResNo();
if (Def->isMachineOpcode()) {
const TargetInstrDesc &II = TII->get(Def->getMachineOpcode());
if (ResNo >= II.getNumDefs() &&
@ -430,7 +430,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
bool Match = true;
if (User->getOpcode() == ISD::CopyToReg &&
User->getOperand(2).Val == Node &&
User->getOperand(2).ResNo == ResNo) {
User->getOperand(2).getResNo() == ResNo) {
unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
VRBase = DestReg;
@ -440,9 +440,9 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
} else {
for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
SDValue Op = User->getOperand(i);
if (Op.Val != Node || Op.ResNo != ResNo)
if (Op.Val != Node || Op.getResNo() != ResNo)
continue;
MVT VT = Node->getValueType(Op.ResNo);
MVT VT = Node->getValueType(Op.getResNo());
if (VT != MVT::Other && VT != MVT::Flag)
Match = false;
}
@ -490,7 +490,7 @@ unsigned ScheduleDAG::getDstOfOnlyCopyToRegUse(SDNode *Node,
SDNode *User = *Node->use_begin();
if (User->getOpcode() == ISD::CopyToReg &&
User->getOperand(2).Val == Node &&
User->getOperand(2).ResNo == ResNo) {
User->getOperand(2).getResNo() == ResNo) {
unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
if (TargetRegisterInfo::isVirtualRegister(Reg))
return Reg;
@ -514,7 +514,7 @@ void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
SDNode *User = *UI;
if (User->getOpcode() == ISD::CopyToReg &&
User->getOperand(2).Val == Node &&
User->getOperand(2).ResNo == i) {
User->getOperand(2).getResNo() == i) {
unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
VRBase = Reg;
@ -547,7 +547,7 @@ unsigned ScheduleDAG::getVR(SDValue Op,
if (Op.isMachineOpcode() &&
Op.getMachineOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
// Add an IMPLICIT_DEF instruction before every use.
unsigned VReg = getDstOfOnlyCopyToRegUse(Op.Val, Op.ResNo);
unsigned VReg = getDstOfOnlyCopyToRegUse(Op.Val, Op.getResNo());
// IMPLICIT_DEF can produce any type of result so its TargetInstrDesc
// does not include operand register class info.
if (!VReg) {

2
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
View File

@ -652,7 +652,7 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
}
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
const SDValue &Op = N->getOperand(i);
MVT VT = Op.Val->getValueType(Op.ResNo);
MVT VT = Op.Val->getValueType(Op.getResNo());
if (VT == MVT::Flag)
return NULL;
}

20
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -327,7 +327,7 @@ static void AddNodeIDOperands(FoldingSetNodeID &ID,
const SDValue *Ops, unsigned NumOps) {
for (; NumOps; --NumOps, ++Ops) {
ID.AddPointer(Ops->Val);
ID.AddInteger(Ops->ResNo);
ID.AddInteger(Ops->getResNo());
}
}
@ -337,7 +337,7 @@ static void AddNodeIDOperands(FoldingSetNodeID &ID,
const SDUse *Ops, unsigned NumOps) {
for (; NumOps; --NumOps, ++Ops) {
ID.AddPointer(Ops->getVal());
ID.AddInteger(Ops->getSDValue().ResNo);
ID.AddInteger(Ops->getSDValue().getResNo());
}
}
@ -3666,7 +3666,7 @@ SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) {
// See if the modified node already exists.
void *InsertPos = 0;
if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos))
return SDValue(Existing, InN.ResNo);
return SDValue(Existing, InN.getResNo());
// Nope it doesn't. Remove the node from its current place in the maps.
if (InsertPos)
@ -3695,7 +3695,7 @@ UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) {
// See if the modified node already exists.
void *InsertPos = 0;
if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos))
return SDValue(Existing, InN.ResNo);
return SDValue(Existing, InN.getResNo());
// Nope it doesn't. Remove the node from its current place in the maps.
if (InsertPos)
@ -3761,7 +3761,7 @@ UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) {
// See if the modified node already exists.
void *InsertPos = 0;
if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos))
return SDValue(Existing, InN.ResNo);
return SDValue(Existing, InN.getResNo());
// Nope it doesn't. Remove the node from its current place in the maps.
if (InsertPos)
@ -4161,7 +4161,7 @@ SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList,
void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To,
DAGUpdateListener *UpdateListener) {
SDNode *From = FromN.Val;
assert(From->getNumValues() == 1 && FromN.ResNo == 0 &&
assert(From->getNumValues() == 1 && FromN.getResNo() == 0 &&
"Cannot replace with this method!");
assert(From != To.Val && "Cannot replace uses of with self");
@ -4267,7 +4267,7 @@ void SelectionDAG::ReplaceAllUsesWith(SDNode *From,
for (SDNode::op_iterator I = U->op_begin(), E = U->op_end();
I != E; ++I, ++operandNum)
if (I->getVal() == From) {
const SDValue &ToOp = To[I->getSDValue().ResNo];
const SDValue &ToOp = To[I->getSDValue().getResNo()];
From->removeUser(operandNum, U);
*I = ToOp;
I->setUser(U);
@ -4573,7 +4573,7 @@ bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const {
// TODO: Only iterate over uses of a given value of the node
for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) {
if (UI.getUse().getSDValue().ResNo == Value) {
if (UI.getUse().getSDValue().getResNo() == Value) {
if (NUses == 0)
return false;
--NUses;
@ -4591,7 +4591,7 @@ bool SDNode::hasAnyUseOfValue(unsigned Value) const {
assert(Value < getNumValues() && "Bad value!");
for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI)
if (UI.getUse().getSDValue().ResNo == Value)
if (UI.getUse().getSDValue().getResNo() == Value)
return true;
return false;
@ -5000,7 +5000,7 @@ void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
if (i) OS << ", ";
OS << (void*)getOperand(i).Val;
if (unsigned RN = getOperand(i).ResNo)
if (unsigned RN = getOperand(i).getResNo())
OS << ":" << RN;
}

22
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -1306,7 +1306,7 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) {
else if (F->paramHasAttr(0, ParamAttr::ZExt))
ExtendKind = ISD::ZERO_EXTEND;
getCopyToParts(DAG, SDValue(RetOp.Val, RetOp.ResNo + j),
getCopyToParts(DAG, SDValue(RetOp.Val, RetOp.getResNo() + j),
&Parts[0], NumParts, PartVT, ExtendKind);
for (unsigned i = 0; i < NumParts; ++i) {
@ -2736,15 +2736,15 @@ void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
// Copy the beginning value(s) from the original aggregate.
for (; i != LinearIndex; ++i)
Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
SDValue(Agg.Val, Agg.ResNo + i);
SDValue(Agg.Val, Agg.getResNo() + i);
// Copy values from the inserted value(s).
for (; i != LinearIndex + NumValValues; ++i)
Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
SDValue(Val.Val, Val.ResNo + i - LinearIndex);
SDValue(Val.Val, Val.getResNo() + i - LinearIndex);
// Copy remaining value(s) from the original aggregate.
for (; i != NumAggValues; ++i)
Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) :
SDValue(Agg.Val, Agg.ResNo + i);
SDValue(Agg.Val, Agg.getResNo() + i);
setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0], NumAggValues),
&Values[0], NumAggValues));
@ -2769,8 +2769,8 @@ void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
// Copy out the selected value(s).
for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
Values[i - LinearIndex] =
OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val->getValueType(Agg.ResNo + i)) :
SDValue(Agg.Val, Agg.ResNo + i);
OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val->getValueType(Agg.getResNo() + i)) :
SDValue(Agg.Val, Agg.getResNo() + i);
setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0], NumValValues),
&Values[0], NumValValues));
@ -2965,7 +2965,7 @@ void SelectionDAGLowering::visitStore(StoreInst &I) {
bool isVolatile = I.isVolatile();
unsigned Alignment = I.getAlignment();
for (unsigned i = 0; i != NumValues; ++i)
Chains[i] = DAG.getStore(Root, SDValue(Src.Val, Src.ResNo + i),
Chains[i] = DAG.getStore(Root, SDValue(Src.Val, Src.getResNo() + i),
DAG.getNode(ISD::ADD, PtrVT, Ptr,
DAG.getConstant(Offsets[i], PtrVT)),
PtrV, Offsets[i],
@ -3810,7 +3810,7 @@ void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG,
unsigned NumParts = TLI->getNumRegisters(ValueVT);
MVT RegisterVT = RegVTs[Value];
getCopyToParts(DAG, Val.getValue(Val.ResNo + Value),
getCopyToParts(DAG, Val.getValue(Val.getResNo() + Value),
&Parts[Part], NumParts, RegisterVT);
Part += NumParts;
}
@ -4763,7 +4763,7 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
Value != NumValues; ++Value) {
MVT VT = ValueVTs[Value];
const Type *ArgTy = VT.getTypeForMVT();
SDValue Op = SDValue(Args[i].Node.Val, Args[i].Node.ResNo + Value);
SDValue Op = SDValue(Args[i].Node.Val, Args[i].Node.getResNo() + Value);
ISD::ArgFlagsTy Flags;
unsigned OriginalAlignment =
getTargetData()->getABITypeAlignment(ArgTy);
@ -5017,8 +5017,8 @@ static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op,
(Op.getOpcode() == ISD::LOAD &&
IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) ||
(Op.getOpcode() == ISD::MERGE_VALUES &&
Op.getOperand(Op.ResNo).getOpcode() == ISD::LOAD &&
IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.ResNo).
Op.getOperand(Op.getResNo()).getOpcode() == ISD::LOAD &&
IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.getResNo()).
getOperand(1))))
return true;
return false;

4
lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
View File

@ -59,7 +59,7 @@ namespace llvm {
static EdgeIter getEdgeTarget(const void *Node, EdgeIter I) {
SDNode *TargetNode = *I;
SDNodeIterator NI = SDNodeIterator::begin(TargetNode);
std::advance(NI, I.getNode()->getOperand(I.getOperand()).ResNo);
std::advance(NI, I.getNode()->getOperand(I.getOperand()).getResNo());
return NI;
}
@ -110,7 +110,7 @@ namespace llvm {
GraphWriter<SelectionDAG*> &GW) {
GW.emitSimpleNode(0, "plaintext=circle", "GraphRoot");
if (G->getRoot().Val)
GW.emitEdge(0, -1, G->getRoot().Val, G->getRoot().ResNo,
GW.emitEdge(0, -1, G->getRoot().Val, G->getRoot().getResNo(),
"color=blue,style=dashed");
}
};

2
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -733,7 +733,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
InFlag = SDValue(ResNode, 1);
ReplaceUses(SDValue(Op.Val, 1), InFlag);
}
ReplaceUses(SDValue(Op.Val, 0), SDValue(Chain.Val, Chain.ResNo));
ReplaceUses(SDValue(Op.Val, 0), SDValue(Chain.Val, Chain.getResNo()));
return NULL;
}
case ARMISD::CMOV: {

2
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -646,7 +646,7 @@ SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
ResultVals.push_back(Chain);
SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size());
return Res.getValue(Op.ResNo);
return Res.getValue(Op.getResNo());
}
static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {

2
lib/Target/CellSPU/SPUISelLowering.cpp
View File

@ -1292,7 +1292,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
// Otherwise, merge everything together with a MERGE_VALUES node.
ResultVals[NumResults++] = Chain;
SDValue Res = DAG.getMergeValues(ResultVals, NumResults);
return Res.getValue(Op.ResNo);
return Res.getValue(Op.getResNo());
}
static SDValue

4
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -750,7 +750,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG)
// Handle result values, copying them out of physregs into vregs that we
// return.
return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.getResNo());
}
/// LowerCallResult - Lower the result values of an ISD::CALL into the
@ -926,7 +926,7 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
// Return the new list of results.
return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
ArgValues.size()).getValue(Op.ResNo);
ArgValues.size()).getValue(Op.getResNo());
}
//===----------------------------------------------------------------------===//

2
lib/Target/PIC16/PIC16ISelLowering.cpp
View File

@ -544,7 +544,7 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
ArgValues.push_back(Root);
return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
ArgValues.size()).getValue(Op.ResNo);
ArgValues.size()).getValue(Op.getResNo());
}

4
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -2511,7 +2511,7 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG,
"Flag must be set. Depend on flag being set in LowerRET");
Chain = DAG.getNode(PPCISD::TAILCALL,
Op.Val->getVTList(), &Ops[0], Ops.size());
return SDValue(Chain.Val, Op.ResNo);
return SDValue(Chain.Val, Op.getResNo());
}
Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
@ -2548,7 +2548,7 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG,
ResultVals.push_back(Chain);
SDValue Res = DAG.getMergeValues(Op.Val->getVTList(), &ResultVals[0],
ResultVals.size());
return Res.getValue(Op.ResNo);
return Res.getValue(Op.getResNo());
}
SDValue PPCTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG,

4
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -253,7 +253,7 @@ static SDNode *findFlagUse(SDNode *N) {
SDNode *User = *I;
for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
SDValue Op = User->getOperand(i);
if (Op.Val == N && Op.ResNo == FlagResNo)
if (Op.Val == N && Op.getResNo() == FlagResNo)
return User;
}
}
@ -888,7 +888,7 @@ DOUT << "AlreadySelected " << AlreadySelected << "\n";
case ISD::SMUL_LOHI:
case ISD::UMUL_LOHI:
// A mul_lohi where we need the low part can be folded as a plain multiply.
if (N.ResNo != 0) break;
if (N.getResNo() != 0) break;
// FALL THROUGH
case ISD::MUL:
// X*[3,5,9] -> X+X*[2,4,8]

6
lib/Target/X86/X86ISelLowering.cpp
View File

@ -1396,7 +1396,7 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
// Return the new list of results.
return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
ArgValues.size()).getValue(Op.ResNo);
ArgValues.size()).getValue(Op.getResNo());
}
SDValue
@ -1760,7 +1760,7 @@ SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
Chain = DAG.getNode(X86ISD::TAILCALL,
Op.Val->getVTList(), &Ops[0], Ops.size());
return SDValue(Chain.Val, Op.ResNo);
return SDValue(Chain.Val, Op.getResNo());
}
Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size());
@ -1787,7 +1787,7 @@ SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
// Handle result values, copying them out of physregs into vregs that we
// return.
return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.getResNo());
}

4
utils/TableGen/DAGISelEmitter.cpp
View File

@ -1190,7 +1190,7 @@ public:
ReplaceFroms.push_back("SDValue(N.Val, " +
utostr(NumPatResults) + ")");
ReplaceTos.push_back("SDValue(" + ChainName + ".Val, " +
ChainName + ".ResNo" + ")");
ChainName + ".getResNo()" + ")");
ChainAssignmentNeeded |= NodeHasChain;
}
@ -1203,7 +1203,7 @@ public:
ReplaceFroms.push_back("SDValue(N.Val, " +
utostr(NumPatResults+1) +
")");
ReplaceTos.push_back("SDValue(ResNode, N.ResNo-1)");
ReplaceTos.push_back("SDValue(ResNode, N.getResNo()-1)");
}
ReplaceFroms.push_back("SDValue(N.Val, " +
utostr(NumPatResults) + ")");