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Eliminate constant-extender profitability checks from Hexagon isel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231992 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek
parent
f7243645ff
commit
9a062b62a7
@ -51,7 +51,6 @@ class HexagonDAGToDAGISel : public SelectionDAGISel {
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// Keep a reference to HexagonTargetMachine.
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const HexagonTargetMachine& TM;
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DenseMap<const GlobalValue *, unsigned> GlobalAddressUseCountMap;
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public:
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explicit HexagonDAGToDAGISel(HexagonTargetMachine &targetmachine,
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CodeGenOpt::Level OptLevel)
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@ -119,7 +118,6 @@ public:
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SDNode *SelectConstant(SDNode *N);
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SDNode *SelectConstantFP(SDNode *N);
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SDNode *SelectAdd(SDNode *N);
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bool isConstExtProfitable(SDNode *N) const;
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// XformMskToBitPosU5Imm - Returns the bit position which
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// the single bit 32 bit mask represents.
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@ -1427,37 +1425,6 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
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return false;
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}
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bool HexagonDAGToDAGISel::isConstExtProfitable(SDNode *N) const {
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unsigned UseCount = 0;
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for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
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UseCount++;
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}
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return (UseCount <= 1);
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}
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//===--------------------------------------------------------------------===//
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// Return 'true' if use count of the global address is below threshold.
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//===--------------------------------------------------------------------===//
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bool HexagonDAGToDAGISel::hasNumUsesBelowThresGA(SDNode *N) const {
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assert(N->getOpcode() == ISD::TargetGlobalAddress &&
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"Expecting a target global address");
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// Always try to fold the address.
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if (TM.getOptLevel() == CodeGenOpt::Aggressive)
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return true;
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GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
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DenseMap<const GlobalValue *, unsigned>::const_iterator GI =
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GlobalAddressUseCountMap.find(GA->getGlobal());
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if (GI == GlobalAddressUseCountMap.end())
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return false;
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return GI->second <= MaxNumOfUsesForConstExtenders;
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}
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//===--------------------------------------------------------------------===//
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// Return true if the non-GP-relative global address can be folded.
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//===--------------------------------------------------------------------===//
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@ -330,7 +330,7 @@ let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
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def A2_combineii: ALU32Inst <(outs DoubleRegs:$Rdd), (ins s8Ext:$s8, s8Imm:$S8),
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"$Rdd = combine(#$s8, #$S8)",
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[(set (i64 DoubleRegs:$Rdd),
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(i64 (HexagonCOMBINE(i32 s8ExtPred:$s8), (i32 s8ImmPred:$S8))))]> {
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(i64 (HexagonCOMBINE(i32 s32ImmPred:$s8), (i32 s8ImmPred:$S8))))]> {
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bits<5> Rdd;
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bits<8> s8;
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bits<8> S8;
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@ -415,7 +415,7 @@ multiclass Addri_base<string mnemonic, SDNode OpNode> {
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defm addi : Addri_base<"add", add>, ImmRegRel, PredNewRel;
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def: Pat<(i32 (add I32:$Rs, s16ExtPred:$s16)),
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def: Pat<(i32 (add I32:$Rs, s32ImmPred:$s16)),
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(i32 (A2_addi I32:$Rs, imm:$s16))>;
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//===----------------------------------------------------------------------===//
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@ -429,7 +429,7 @@ class T_ALU32ri_logical <string mnemonic, SDNode OpNode, bits<2> MinOp>
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: ALU32_ri <(outs IntRegs:$Rd),
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(ins IntRegs:$Rs, s10Ext:$s10),
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"$Rd = "#mnemonic#"($Rs, #$s10)" ,
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[(set (i32 IntRegs:$Rd), (OpNode (i32 IntRegs:$Rs), s10ExtPred:$s10))]> {
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[(set (i32 IntRegs:$Rd), (OpNode (i32 IntRegs:$Rs), s32ImmPred:$s10))]> {
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bits<5> Rd;
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bits<5> Rs;
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bits<10> s10;
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@ -474,7 +474,7 @@ def A2_nop: ALU32Inst <(outs), (ins), "nop" > {
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let Inst{27-24} = 0b1111;
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}
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def: Pat<(sub s10ExtPred:$s10, IntRegs:$Rs),
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def: Pat<(sub s32ImmPred:$s10, IntRegs:$Rs),
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(A2_subri imm:$s10, IntRegs:$Rs)>;
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// Rd = not(Rs) gets mapped to Rd=sub(#-1, Rs).
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@ -622,7 +622,7 @@ let InputType = "imm", isExtendable = 1, isExtentSigned = 1,
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isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16, isMoveImm = 1,
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isPredicated = 0, isPredicable = 1, isReMaterializable = 1 in
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def A2_tfrsi : ALU32Inst<(outs IntRegs:$Rd), (ins s16Ext:$s16), "$Rd = #$s16",
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[(set (i32 IntRegs:$Rd), s16ExtPred:$s16)], "", ALU32_2op_tc_1_SLOT0123>,
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[(set (i32 IntRegs:$Rd), s32ImmPred:$s16)], "", ALU32_2op_tc_1_SLOT0123>,
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ImmRegRel, PredRel {
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bits<5> Rd;
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bits<16> s16;
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@ -690,11 +690,11 @@ let opExtendable = 3 in
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def C2_muxir : T_MUX1<0b0, (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
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"$Rd = mux($Pu, $Rs, #$s8)">;
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def : Pat<(i32 (select I1:$Pu, s8ExtPred:$s8, I32:$Rs)),
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(C2_muxri I1:$Pu, s8ExtPred:$s8, I32:$Rs)>;
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def : Pat<(i32 (select I1:$Pu, s32ImmPred:$s8, I32:$Rs)),
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(C2_muxri I1:$Pu, s32ImmPred:$s8, I32:$Rs)>;
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def : Pat<(i32 (select I1:$Pu, I32:$Rs, s8ExtPred:$s8)),
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(C2_muxir I1:$Pu, I32:$Rs, s8ExtPred:$s8)>;
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def : Pat<(i32 (select I1:$Pu, I32:$Rs, s32ImmPred:$s8)),
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(C2_muxir I1:$Pu, I32:$Rs, s32ImmPred:$s8)>;
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// C2_muxii: Scalar mux immediates.
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let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1,
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@ -703,7 +703,7 @@ def C2_muxii: ALU32Inst <(outs IntRegs:$Rd),
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(ins PredRegs:$Pu, s8Ext:$s8, s8Imm:$S8),
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"$Rd = mux($Pu, #$s8, #$S8)" ,
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[(set (i32 IntRegs:$Rd),
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(i32 (select I1:$Pu, s8ExtPred:$s8, s8ImmPred:$S8)))] > {
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(i32 (select I1:$Pu, s32ImmPred:$s8, s8ImmPred:$S8)))] > {
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bits<5> Rd;
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bits<2> Pu;
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bits<8> s8;
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@ -1780,21 +1780,21 @@ multiclass Loadx_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
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}
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let AddedComplexity = 20 in {
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defm: Loadx_pat<load, i32, s11_2ExtPred, L2_loadri_io>;
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defm: Loadx_pat<load, i64, s11_3ExtPred, L2_loadrd_io>;
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defm: Loadx_pat<atomic_load_8 , i32, s11_0ExtPred, L2_loadrub_io>;
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defm: Loadx_pat<atomic_load_16, i32, s11_1ExtPred, L2_loadruh_io>;
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defm: Loadx_pat<atomic_load_32, i32, s11_2ExtPred, L2_loadri_io>;
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defm: Loadx_pat<atomic_load_64, i64, s11_3ExtPred, L2_loadrd_io>;
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defm: Loadx_pat<load, i32, s30_2ImmPred, L2_loadri_io>;
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defm: Loadx_pat<load, i64, s29_3ImmPred, L2_loadrd_io>;
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defm: Loadx_pat<atomic_load_8 , i32, s32_0ImmPred, L2_loadrub_io>;
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defm: Loadx_pat<atomic_load_16, i32, s31_1ImmPred, L2_loadruh_io>;
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defm: Loadx_pat<atomic_load_32, i32, s30_2ImmPred, L2_loadri_io>;
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defm: Loadx_pat<atomic_load_64, i64, s29_3ImmPred, L2_loadrd_io>;
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defm: Loadx_pat<extloadi1, i32, s11_0ExtPred, L2_loadrub_io>;
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defm: Loadx_pat<extloadi8, i32, s11_0ExtPred, L2_loadrub_io>;
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defm: Loadx_pat<extloadi16, i32, s11_1ExtPred, L2_loadruh_io>;
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defm: Loadx_pat<sextloadi8, i32, s11_0ExtPred, L2_loadrb_io>;
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defm: Loadx_pat<sextloadi16, i32, s11_1ExtPred, L2_loadrh_io>;
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defm: Loadx_pat<zextloadi1, i32, s11_0ExtPred, L2_loadrub_io>;
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defm: Loadx_pat<zextloadi8, i32, s11_0ExtPred, L2_loadrub_io>;
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defm: Loadx_pat<zextloadi16, i32, s11_1ExtPred, L2_loadruh_io>;
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defm: Loadx_pat<extloadi1, i32, s32_0ImmPred, L2_loadrub_io>;
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defm: Loadx_pat<extloadi8, i32, s32_0ImmPred, L2_loadrub_io>;
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defm: Loadx_pat<extloadi16, i32, s31_1ImmPred, L2_loadruh_io>;
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defm: Loadx_pat<sextloadi8, i32, s32_0ImmPred, L2_loadrb_io>;
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defm: Loadx_pat<sextloadi16, i32, s31_1ImmPred, L2_loadrh_io>;
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defm: Loadx_pat<zextloadi1, i32, s32_0ImmPred, L2_loadrub_io>;
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defm: Loadx_pat<zextloadi8, i32, s32_0ImmPred, L2_loadrub_io>;
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defm: Loadx_pat<zextloadi16, i32, s31_1ImmPred, L2_loadruh_io>;
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// No sextloadi1.
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}
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@ -2739,7 +2739,7 @@ class T_MType_mpy_ri <bit isNeg, Operand ImmOp, list<dag> pattern>
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let isExtendable = 1, opExtentBits = 8, opExtendable = 2 in
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def M2_mpysip : T_MType_mpy_ri <0, u8Ext,
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[(set (i32 IntRegs:$Rd), (mul IntRegs:$Rs, u8ExtPred:$u8))]>;
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[(set (i32 IntRegs:$Rd), (mul IntRegs:$Rs, u32ImmPred:$u8))]>;
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def M2_mpysin : T_MType_mpy_ri <1, u8Imm,
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[(set (i32 IntRegs:$Rd), (ineg (mul IntRegs:$Rs,
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@ -2761,7 +2761,7 @@ let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9,
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def M2_mpysmi : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
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"$dst = mpyi($src1, #$src2)",
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[(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
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s9ExtPred:$src2))]>, ImmRegRel;
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s32ImmPred:$src2))]>, ImmRegRel;
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let hasNewValue = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 3,
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InputType = "imm" in
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@ -2812,7 +2812,7 @@ class T_MType_acc_rr <string mnemonic, bits<3> MajOp, bits<3> MinOp,
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let CextOpcode = "MPYI_acc", Itinerary = M_tc_3x_SLOT23 in {
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def M2_macsip : T_MType_acc_ri <"+= mpyi", 0b010, u8Ext,
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[(set (i32 IntRegs:$dst),
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(add (mul IntRegs:$src2, u8ExtPred:$src3),
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(add (mul IntRegs:$src2, u32ImmPred:$src3),
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IntRegs:$src1))]>, ImmRegRel;
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def M2_maci : T_MType_acc_rr <"+= mpyi", 0b000, 0b000, 0,
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@ -2825,7 +2825,7 @@ let CextOpcode = "ADD_acc" in {
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let isExtentSigned = 1 in
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def M2_accii : T_MType_acc_ri <"+= add", 0b100, s8Ext,
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[(set (i32 IntRegs:$dst),
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(add (add (i32 IntRegs:$src2), s8_16ExtPred:$src3),
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(add (add (i32 IntRegs:$src2), s16_16ImmPred:$src3),
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(i32 IntRegs:$src1)))]>, ImmRegRel;
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def M2_acci : T_MType_acc_rr <"+= add", 0b000, 0b001, 0,
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@ -2857,9 +2857,9 @@ class T_MType_acc_pat2 <InstHexagon MI, SDNode firstOp, SDNode secOp>
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(MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
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def : T_MType_acc_pat2 <M2_xor_xacc, xor, xor>;
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def : T_MType_acc_pat1 <M2_macsin, mul, sub, u8ExtPred>;
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def : T_MType_acc_pat1 <M2_macsin, mul, sub, u32ImmPred>;
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def : T_MType_acc_pat1 <M2_naccii, add, sub, s8_16ExtPred>;
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def : T_MType_acc_pat1 <M2_naccii, add, sub, s16_16ImmPred>;
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def : T_MType_acc_pat2 <M2_nacci, add, sub>;
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//===----------------------------------------------------------------------===//
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@ -3610,15 +3610,15 @@ class SwapSt<PatFrag F>
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: PatFrag<(ops node:$val, node:$ptr), F.Fragment>;
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let AddedComplexity = 20 in {
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defm: Storex_pat<truncstorei8, I32, s11_0ExtPred, S2_storerb_io>;
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defm: Storex_pat<truncstorei16, I32, s11_1ExtPred, S2_storerh_io>;
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defm: Storex_pat<store, I32, s11_2ExtPred, S2_storeri_io>;
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defm: Storex_pat<store, I64, s11_3ExtPred, S2_storerd_io>;
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defm: Storex_pat<truncstorei8, I32, s32_0ImmPred, S2_storerb_io>;
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defm: Storex_pat<truncstorei16, I32, s31_1ImmPred, S2_storerh_io>;
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defm: Storex_pat<store, I32, s30_2ImmPred, S2_storeri_io>;
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defm: Storex_pat<store, I64, s29_3ImmPred, S2_storerd_io>;
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defm: Storex_pat<SwapSt<atomic_store_8>, I32, s11_0ExtPred, S2_storerb_io>;
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defm: Storex_pat<SwapSt<atomic_store_16>, I32, s11_1ExtPred, S2_storerh_io>;
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defm: Storex_pat<SwapSt<atomic_store_32>, I32, s11_2ExtPred, S2_storeri_io>;
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defm: Storex_pat<SwapSt<atomic_store_64>, I64, s11_3ExtPred, S2_storerd_io>;
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defm: Storex_pat<SwapSt<atomic_store_8>, I32, s32_0ImmPred, S2_storerb_io>;
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defm: Storex_pat<SwapSt<atomic_store_16>, I32, s31_1ImmPred, S2_storerh_io>;
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defm: Storex_pat<SwapSt<atomic_store_32>, I32, s30_2ImmPred, S2_storeri_io>;
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defm: Storex_pat<SwapSt<atomic_store_64>, I64, s29_3ImmPred, S2_storerd_io>;
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}
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// Simple patterns should be tried with the least priority.
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@ -3633,9 +3633,9 @@ def: Storex_simple_pat<SwapSt<atomic_store_32>, I32, S2_storeri_io>;
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def: Storex_simple_pat<SwapSt<atomic_store_64>, I64, S2_storerd_io>;
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let AddedComplexity = 20 in {
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defm: Storexm_pat<truncstorei8, I64, s11_0ExtPred, LoReg, S2_storerb_io>;
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defm: Storexm_pat<truncstorei16, I64, s11_1ExtPred, LoReg, S2_storerh_io>;
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defm: Storexm_pat<truncstorei32, I64, s11_2ExtPred, LoReg, S2_storeri_io>;
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defm: Storexm_pat<truncstorei8, I64, s32_0ImmPred, LoReg, S2_storerb_io>;
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defm: Storexm_pat<truncstorei16, I64, s31_1ImmPred, LoReg, S2_storerh_io>;
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defm: Storexm_pat<truncstorei32, I64, s30_2ImmPred, LoReg, S2_storeri_io>;
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}
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def: Storexm_simple_pat<truncstorei8, I64, LoReg, S2_storerb_io>;
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@ -4415,7 +4415,7 @@ def C2_pxfer_map: SInst<(outs PredRegs:$dst), (ins PredRegs:$src),
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// Patterns for loads of i1:
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def: Pat<(i1 (load AddrFI:$fi)),
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(C2_tfrrp (L2_loadrub_io AddrFI:$fi, 0))>;
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def: Pat<(i1 (load (add (i32 IntRegs:$Rs), s11_0ExtPred:$Off))),
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def: Pat<(i1 (load (add (i32 IntRegs:$Rs), s32ImmPred:$Off))),
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(C2_tfrrp (L2_loadrub_io IntRegs:$Rs, imm:$Off))>;
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def: Pat<(i1 (load (i32 IntRegs:$Rs))),
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(C2_tfrrp (L2_loadrub_io IntRegs:$Rs, 0))>;
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@ -4426,7 +4426,7 @@ def I1toI32: OutPatFrag<(ops node:$Rs),
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def I32toI1: OutPatFrag<(ops node:$Rs),
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(i1 (C2_tfrrp (i32 $Rs)))>;
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defm: Storexm_pat<store, I1, s11_0ExtPred, I1toI32, S2_storerb_io>;
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defm: Storexm_pat<store, I1, s32ImmPred, I1toI32, S2_storerb_io>;
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def: Storexm_simple_pat<store, I1, I1toI32, S2_storerb_io>;
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//===----------------------------------------------------------------------===//
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@ -4917,19 +4917,19 @@ def: Pat<(add (i1 PredRegs:$src1), -1),
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(C2_not PredRegs:$src1)>;
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// Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
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def: Pat<(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ExtPred:$src3),
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(C2_muxii PredRegs:$src1, s8ExtPred:$src3, s8ImmPred:$src2)>;
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def: Pat<(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s32ImmPred:$src3),
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(C2_muxii PredRegs:$src1, s32ImmPred:$src3, s8ImmPred:$src2)>;
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// Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
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// => r0 = C2_muxir(p0, r1, #i)
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def: Pat<(select (not (i1 PredRegs:$src1)), s8ExtPred:$src2,
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def: Pat<(select (not (i1 PredRegs:$src1)), s32ImmPred:$src2,
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(i32 IntRegs:$src3)),
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(C2_muxir PredRegs:$src1, IntRegs:$src3, s8ExtPred:$src2)>;
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(C2_muxir PredRegs:$src1, IntRegs:$src3, s32ImmPred:$src2)>;
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// Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
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// => r0 = C2_muxri (p0, #i, r1)
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def: Pat<(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s8ExtPred:$src3),
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(C2_muxri PredRegs:$src1, s8ExtPred:$src3, IntRegs:$src2)>;
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def: Pat<(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s32ImmPred:$src3),
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(C2_muxri PredRegs:$src1, s32ImmPred:$src3, IntRegs:$src2)>;
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|
||||
// Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
|
||||
def: Pat<(brcond (not (i1 PredRegs:$src1)), bb:$offset),
|
||||
@ -4994,8 +4994,8 @@ def: Pat<(i1 (trunc (i64 DoubleRegs:$src))),
|
||||
|
||||
// rs <= rt -> !(rs > rt).
|
||||
let AddedComplexity = 30 in
|
||||
def: Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
|
||||
(C2_not (C2_cmpgti IntRegs:$src1, s10ExtPred:$src2))>;
|
||||
def: Pat<(i1 (setle (i32 IntRegs:$src1), s32ImmPred:$src2)),
|
||||
(C2_not (C2_cmpgti IntRegs:$src1, s32ImmPred:$src2))>;
|
||||
|
||||
// rs <= rt -> !(rs > rt).
|
||||
def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
|
||||
@ -5009,8 +5009,8 @@ def: Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
|
||||
// Hexagon_TODO: We should improve on this.
|
||||
// rs != rt -> !(rs == rt).
|
||||
let AddedComplexity = 30 in
|
||||
def: Pat<(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
|
||||
(C2_not (C2_cmpeqi IntRegs:$src1, s10ExtPred:$src2))>;
|
||||
def: Pat<(i1 (setne (i32 IntRegs:$src1), s32ImmPred:$src2)),
|
||||
(C2_not (C2_cmpeqi IntRegs:$src1, s32ImmPred:$src2))>;
|
||||
|
||||
// Convert setne back to xor for hexagon since we compute w/ pred registers.
|
||||
def: Pat<(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
|
||||
@ -5028,8 +5028,8 @@ def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
|
||||
|
||||
// cmpge(Rs, Imm) -> cmpgt(Rs, Imm-1)
|
||||
let AddedComplexity = 30 in
|
||||
def: Pat<(i1 (setge (i32 IntRegs:$src1), s8ExtPred:$src2)),
|
||||
(C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s8ExtPred:$src2))>;
|
||||
def: Pat<(i1 (setge (i32 IntRegs:$src1), s32ImmPred:$src2)),
|
||||
(C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s32ImmPred:$src2))>;
|
||||
|
||||
// Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
|
||||
// rss >= rtt -> !(rtt > rss).
|
||||
@ -5040,20 +5040,21 @@ def: Pat<(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
|
||||
// !cmpge(Rs, Imm) -> !cmpgt(Rs, Imm-1).
|
||||
// rs < rt -> !(rs >= rt).
|
||||
let AddedComplexity = 30 in
|
||||
def: Pat<(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
|
||||
(C2_not (C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s8ExtPred:$src2)))>;
|
||||
def: Pat<(i1 (setlt (i32 IntRegs:$src1), s32ImmPred:$src2)),
|
||||
(C2_not (C2_cmpgti IntRegs:$src1,
|
||||
(DEC_CONST_SIGNED s32ImmPred:$src2)))>;
|
||||
|
||||
// Generate cmpgeu(Rs, #0) -> cmpeq(Rs, Rs)
|
||||
def: Pat<(i1 (setuge (i32 IntRegs:$src1), 0)),
|
||||
(C2_cmpeq IntRegs:$src1, IntRegs:$src1)>;
|
||||
|
||||
// Generate cmpgeu(Rs, #u8) -> cmpgtu(Rs, #u8 -1)
|
||||
def: Pat<(i1 (setuge (i32 IntRegs:$src1), u8ExtPred:$src2)),
|
||||
(C2_cmpgtui IntRegs:$src1, (DEC_CONST_UNSIGNED u8ExtPred:$src2))>;
|
||||
def: Pat<(i1 (setuge (i32 IntRegs:$src1), u32ImmPred:$src2)),
|
||||
(C2_cmpgtui IntRegs:$src1, (DEC_CONST_UNSIGNED u32ImmPred:$src2))>;
|
||||
|
||||
// Generate cmpgtu(Rs, #u9)
|
||||
def: Pat<(i1 (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)),
|
||||
(C2_cmpgtui IntRegs:$src1, u9ExtPred:$src2)>;
|
||||
def: Pat<(i1 (setugt (i32 IntRegs:$src1), u32ImmPred:$src2)),
|
||||
(C2_cmpgtui IntRegs:$src1, u32ImmPred:$src2)>;
|
||||
|
||||
// Map from Rs >= Rt -> !(Rt > Rs).
|
||||
// rs >= rt -> !(rt > rs).
|
||||
@ -5804,4 +5805,4 @@ include "HexagonInstrInfoV5.td"
|
||||
// ALU32/64/Vector +
|
||||
//===----------------------------------------------------------------------===///
|
||||
|
||||
include "HexagonInstrInfoVector.td"
|
||||
include "HexagonInstrInfoVector.td"
|
||||
|
||||
@ -269,10 +269,10 @@ class T_RCMP_EQ_ri<string mnemonic, bit IsNeg>
|
||||
def A4_rcmpeqi : T_RCMP_EQ_ri<"cmp.eq", 0>;
|
||||
def A4_rcmpneqi : T_RCMP_EQ_ri<"!cmp.eq", 1>;
|
||||
|
||||
def: Pat<(i32 (zext (i1 (seteq (i32 IntRegs:$Rs), s8ExtPred:$s8)))),
|
||||
(A4_rcmpeqi IntRegs:$Rs, s8ExtPred:$s8)>;
|
||||
def: Pat<(i32 (zext (i1 (setne (i32 IntRegs:$Rs), s8ExtPred:$s8)))),
|
||||
(A4_rcmpneqi IntRegs:$Rs, s8ExtPred:$s8)>;
|
||||
def: Pat<(i32 (zext (i1 (seteq (i32 IntRegs:$Rs), s32ImmPred:$s8)))),
|
||||
(A4_rcmpeqi IntRegs:$Rs, s32ImmPred:$s8)>;
|
||||
def: Pat<(i32 (zext (i1 (setne (i32 IntRegs:$Rs), s32ImmPred:$s8)))),
|
||||
(A4_rcmpneqi IntRegs:$Rs, s32ImmPred:$s8)>;
|
||||
|
||||
// Preserve the S2_tstbit_r generation
|
||||
def: Pat<(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
|
||||
@ -317,11 +317,11 @@ def A4_combineir : T_Combine1<0b01, (ins s8Ext:$s8, IntRegs:$Rs),
|
||||
// The complexity of the combines involving immediates should be greater
|
||||
// than the complexity of the combine with two registers.
|
||||
let AddedComplexity = 50 in {
|
||||
def: Pat<(HexagonCOMBINE IntRegs:$r, s8ExtPred:$i),
|
||||
(A4_combineri IntRegs:$r, s8ExtPred:$i)>;
|
||||
def: Pat<(HexagonCOMBINE IntRegs:$r, s32ImmPred:$i),
|
||||
(A4_combineri IntRegs:$r, s32ImmPred:$i)>;
|
||||
|
||||
def: Pat<(HexagonCOMBINE s8ExtPred:$i, IntRegs:$r),
|
||||
(A4_combineir s8ExtPred:$i, IntRegs:$r)>;
|
||||
def: Pat<(HexagonCOMBINE s32ImmPred:$i, IntRegs:$r),
|
||||
(A4_combineir s32ImmPred:$i, IntRegs:$r)>;
|
||||
}
|
||||
|
||||
// A4_combineii: Set two small immediates.
|
||||
@ -343,7 +343,7 @@ def A4_combineii: ALU32Inst<(outs DoubleRegs:$Rdd), (ins s8Imm:$s8, u6Ext:$U6),
|
||||
// The complexity of the combine with two immediates should be greater than
|
||||
// the complexity of a combine involving a register.
|
||||
let AddedComplexity = 75 in
|
||||
def: Pat<(HexagonCOMBINE s8ImmPred:$s8, u6ExtPred:$u6),
|
||||
def: Pat<(HexagonCOMBINE s8ImmPred:$s8, u32ImmPred:$u6),
|
||||
(A4_combineii imm:$s8, imm:$u6)>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -375,14 +375,14 @@ multiclass Loadxm_pat<PatFrag Load, ValueType VT, PatFrag ValueMod,
|
||||
(VT (ValueMod (MI IntRegs:$Rs, 0)))>;
|
||||
}
|
||||
|
||||
defm: Loadxm_pat<extloadi1, i64, Zext64, s11_0ExtPred, L2_loadrub_io>;
|
||||
defm: Loadxm_pat<extloadi8, i64, Zext64, s11_0ExtPred, L2_loadrub_io>;
|
||||
defm: Loadxm_pat<extloadi16, i64, Zext64, s11_1ExtPred, L2_loadruh_io>;
|
||||
defm: Loadxm_pat<zextloadi1, i64, Zext64, s11_0ExtPred, L2_loadrub_io>;
|
||||
defm: Loadxm_pat<zextloadi8, i64, Zext64, s11_0ExtPred, L2_loadrub_io>;
|
||||
defm: Loadxm_pat<zextloadi16, i64, Zext64, s11_1ExtPred, L2_loadruh_io>;
|
||||
defm: Loadxm_pat<sextloadi8, i64, Sext64, s11_0ExtPred, L2_loadrb_io>;
|
||||
defm: Loadxm_pat<sextloadi16, i64, Sext64, s11_1ExtPred, L2_loadrh_io>;
|
||||
defm: Loadxm_pat<extloadi1, i64, Zext64, s32_0ImmPred, L2_loadrub_io>;
|
||||
defm: Loadxm_pat<extloadi8, i64, Zext64, s32_0ImmPred, L2_loadrub_io>;
|
||||
defm: Loadxm_pat<extloadi16, i64, Zext64, s31_1ImmPred, L2_loadruh_io>;
|
||||
defm: Loadxm_pat<zextloadi1, i64, Zext64, s32_0ImmPred, L2_loadrub_io>;
|
||||
defm: Loadxm_pat<zextloadi8, i64, Zext64, s32_0ImmPred, L2_loadrub_io>;
|
||||
defm: Loadxm_pat<zextloadi16, i64, Zext64, s31_1ImmPred, L2_loadruh_io>;
|
||||
defm: Loadxm_pat<sextloadi8, i64, Sext64, s32_0ImmPred, L2_loadrb_io>;
|
||||
defm: Loadxm_pat<sextloadi16, i64, Sext64, s31_1ImmPred, L2_loadrh_io>;
|
||||
|
||||
// Map Rdd = anyext(Rs) -> Rdd = combine(#0, Rs).
|
||||
def: Pat<(i64 (anyext (i32 IntRegs:$src1))), (Zext64 IntRegs:$src1)>;
|
||||
@ -663,9 +663,9 @@ def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
|
||||
(i64 (A4_combineir 0, (L2_loadri_io AddrFI:$src1, 0)))>;
|
||||
|
||||
let AddedComplexity = 100 in
|
||||
def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
|
||||
def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s30_2ImmPred:$offset)))),
|
||||
(i64 (A4_combineir 0, (L2_loadri_io IntRegs:$src1,
|
||||
s11_2ExtPred:$offset)))>;
|
||||
s30_2ImmPred:$offset)))>;
|
||||
|
||||
// anyext i32->i64
|
||||
def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
|
||||
@ -791,8 +791,8 @@ multiclass T_StoreAbsReg_Pats <InstHexagon MI, RegisterClass RC, ValueType VT,
|
||||
PatFrag stOp> {
|
||||
def : Pat<(stOp (VT RC:$src4),
|
||||
(add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
|
||||
u0AlwaysExtPred:$src3)),
|
||||
(MI IntRegs:$src1, u2ImmPred:$src2, u0AlwaysExtPred:$src3, RC:$src4)>;
|
||||
u32ImmPred:$src3)),
|
||||
(MI IntRegs:$src1, u2ImmPred:$src2, u32ImmPred:$src3, RC:$src4)>;
|
||||
|
||||
def : Pat<(stOp (VT RC:$src4),
|
||||
(add (shl IntRegs:$src1, u2ImmPred:$src2),
|
||||
@ -1180,17 +1180,17 @@ let AddedComplexity = 40 in {
|
||||
// is not extendable. This could cause problems during removing the frame
|
||||
// indices, since the offset with respect to R29/R30 may not fit in the
|
||||
// u6 field.
|
||||
def: Storexm_add_pat<truncstorei8, s8ExtPred, u6_0ImmPred, ToImmByte,
|
||||
def: Storexm_add_pat<truncstorei8, s32ImmPred, u6_0ImmPred, ToImmByte,
|
||||
S4_storeirb_io>;
|
||||
def: Storexm_add_pat<truncstorei16, s8ExtPred, u6_1ImmPred, ToImmHalf,
|
||||
def: Storexm_add_pat<truncstorei16, s32ImmPred, u6_1ImmPred, ToImmHalf,
|
||||
S4_storeirh_io>;
|
||||
def: Storexm_add_pat<store, s8ExtPred, u6_2ImmPred, ToImmWord,
|
||||
def: Storexm_add_pat<store, s32ImmPred, u6_2ImmPred, ToImmWord,
|
||||
S4_storeiri_io>;
|
||||
}
|
||||
|
||||
def: Storexm_simple_pat<truncstorei8, s8ExtPred, ToImmByte, S4_storeirb_io>;
|
||||
def: Storexm_simple_pat<truncstorei16, s8ExtPred, ToImmHalf, S4_storeirh_io>;
|
||||
def: Storexm_simple_pat<store, s8ExtPred, ToImmWord, S4_storeiri_io>;
|
||||
def: Storexm_simple_pat<truncstorei8, s32ImmPred, ToImmByte, S4_storeirb_io>;
|
||||
def: Storexm_simple_pat<truncstorei16, s32ImmPred, ToImmHalf, S4_storeirh_io>;
|
||||
def: Storexm_simple_pat<store, s32ImmPred, ToImmWord, S4_storeiri_io>;
|
||||
|
||||
// memb(Rx++#s4:0:circ(Mu))=Rt
|
||||
// memb(Rx++I:circ(Mu))=Rt
|
||||
@ -1845,23 +1845,23 @@ def Hexagongat_pcrel_ba : SDNode<"HexagonISD::AT_PCREL",
|
||||
|
||||
// PIC: Map from a block address computation to a PC-relative add
|
||||
def: Pat<(Hexagongat_pcrel_ba tblockaddress:$src1),
|
||||
(C4_addipc u6ExtPred:$src1)>;
|
||||
(C4_addipc u32ImmPred:$src1)>;
|
||||
|
||||
// PIC: Map from the computation to generate a GOT pointer to a PC-relative add
|
||||
def: Pat<(Hexagonpic_add texternalsym:$src1),
|
||||
(C4_addipc u6ExtPred:$src1)>;
|
||||
(C4_addipc u32ImmPred:$src1)>;
|
||||
|
||||
// PIC: Map from a jump table address computation to a PC-relative add
|
||||
def: Pat<(Hexagongat_pcrel_jt tjumptable:$src1),
|
||||
(C4_addipc u6ExtPred:$src1)>;
|
||||
(C4_addipc u32ImmPred:$src1)>;
|
||||
|
||||
// PIC: Map from a GOT-relative symbol reference to a load
|
||||
def: Pat<(Hexagonat_got (i32 IntRegs:$src1), tglobaladdr:$src2),
|
||||
(L2_loadri_io IntRegs:$src1, s11_2ExtPred:$src2)>;
|
||||
(L2_loadri_io IntRegs:$src1, s30_2ImmPred:$src2)>;
|
||||
|
||||
// PIC: Map from a static symbol reference to a PC-relative add
|
||||
def: Pat<(Hexagongat_pcrel tglobaladdr:$src1),
|
||||
(C4_addipc u6ExtPred:$src1)>;
|
||||
(C4_addipc u32ImmPred:$src1)>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// CR -
|
||||
@ -1902,7 +1902,7 @@ def S4_addaddi : ALU64Inst <(outs IntRegs:$Rd),
|
||||
(ins IntRegs:$Rs, IntRegs:$Ru, s6Ext:$s6),
|
||||
"$Rd = add($Rs, add($Ru, #$s6))" ,
|
||||
[(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs),
|
||||
(add (i32 IntRegs:$Ru), s6_16ExtPred:$s6)))],
|
||||
(add (i32 IntRegs:$Ru), s16_16ImmPred:$s6)))],
|
||||
"", ALU64_tc_2_SLOT23> {
|
||||
bits<5> Rd;
|
||||
bits<5> Rs;
|
||||
@ -1943,19 +1943,19 @@ def S4_subaddi: ALU64Inst <(outs IntRegs:$Rd),
|
||||
}
|
||||
|
||||
// Rd=add(Rs,sub(#s6,Ru))
|
||||
def: Pat<(add (i32 IntRegs:$src1), (sub s6_10ExtPred:$src2,
|
||||
def: Pat<(add (i32 IntRegs:$src1), (sub s32ImmPred:$src2,
|
||||
(i32 IntRegs:$src3))),
|
||||
(S4_subaddi IntRegs:$src1, s6_10ExtPred:$src2, IntRegs:$src3)>;
|
||||
(S4_subaddi IntRegs:$src1, s32ImmPred:$src2, IntRegs:$src3)>;
|
||||
|
||||
// Rd=sub(add(Rs,#s6),Ru)
|
||||
def: Pat<(sub (add (i32 IntRegs:$src1), s6_10ExtPred:$src2),
|
||||
def: Pat<(sub (add (i32 IntRegs:$src1), s32ImmPred:$src2),
|
||||
(i32 IntRegs:$src3)),
|
||||
(S4_subaddi IntRegs:$src1, s6_10ExtPred:$src2, IntRegs:$src3)>;
|
||||
(S4_subaddi IntRegs:$src1, s32ImmPred:$src2, IntRegs:$src3)>;
|
||||
|
||||
// Rd=add(sub(Rs,Ru),#s6)
|
||||
def: Pat<(add (sub (i32 IntRegs:$src1), (i32 IntRegs:$src3)),
|
||||
(s6_10ExtPred:$src2)),
|
||||
(S4_subaddi IntRegs:$src1, s6_10ExtPred:$src2, IntRegs:$src3)>;
|
||||
(s32ImmPred:$src2)),
|
||||
(S4_subaddi IntRegs:$src1, s32ImmPred:$src2, IntRegs:$src3)>;
|
||||
|
||||
|
||||
// Add or subtract doublewords with carry.
|
||||
@ -2108,7 +2108,7 @@ def S4_or_andix:
|
||||
(ins IntRegs:$Ru, IntRegs:$_src_, s10Ext:$s10),
|
||||
"$Rx = or($Ru, and($_src_, #$s10))" ,
|
||||
[(set (i32 IntRegs:$Rx),
|
||||
(or (i32 IntRegs:$Ru), (and (i32 IntRegs:$_src_), s10ExtPred:$s10)))] ,
|
||||
(or (i32 IntRegs:$Ru), (and (i32 IntRegs:$_src_), s32ImmPred:$s10)))] ,
|
||||
"$_src_ = $Rx", ALU64_tc_2_SLOT23> {
|
||||
bits<5> Rx;
|
||||
bits<5> Ru;
|
||||
@ -2253,7 +2253,7 @@ class T_CompOR <string mnemonic, bits<2> MajOp, SDNode OpNode>
|
||||
(ins IntRegs:$src1, IntRegs:$Rs, s10Ext:$s10),
|
||||
"$Rx |= "#mnemonic#"($Rs, #$s10)",
|
||||
[(set (i32 IntRegs:$Rx), (or (i32 IntRegs:$src1),
|
||||
(OpNode (i32 IntRegs:$Rs), s10ExtPred:$s10)))],
|
||||
(OpNode (i32 IntRegs:$Rs), s32ImmPred:$s10)))],
|
||||
"$src1 = $Rx", ALU64_tc_2_SLOT23>, ImmRegRel {
|
||||
bits<5> Rx;
|
||||
bits<5> Rs;
|
||||
@ -2415,7 +2415,7 @@ def M4_mpyri_addi : MInst<(outs IntRegs:$Rd),
|
||||
"$Rd = add(#$u6, mpyi($Rs, #$U6))" ,
|
||||
[(set (i32 IntRegs:$Rd),
|
||||
(add (mul (i32 IntRegs:$Rs), u6ImmPred:$U6),
|
||||
u6ExtPred:$u6))] ,"",ALU64_tc_3x_SLOT23> {
|
||||
u32ImmPred:$u6))] ,"",ALU64_tc_3x_SLOT23> {
|
||||
bits<5> Rd;
|
||||
bits<6> u6;
|
||||
bits<5> Rs;
|
||||
@ -2440,7 +2440,7 @@ def M4_mpyrr_addi : MInst <(outs IntRegs:$Rd),
|
||||
(ins u6Ext:$u6, IntRegs:$Rs, IntRegs:$Rt),
|
||||
"$Rd = add(#$u6, mpyi($Rs, $Rt))" ,
|
||||
[(set (i32 IntRegs:$Rd),
|
||||
(add (mul (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), u6ExtPred:$u6))],
|
||||
(add (mul (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), u32ImmPred:$u6))],
|
||||
"", ALU64_tc_3x_SLOT23>, ImmRegRel {
|
||||
bits<5> Rd;
|
||||
bits<6> u6;
|
||||
@ -2490,7 +2490,7 @@ def M4_mpyri_addr_u2 : T_AddMpy<0b0, u6_2ImmPred,
|
||||
|
||||
let isExtendable = 1, opExtentBits = 6, opExtendable = 3,
|
||||
CextOpcode = "ADD_MPY", InputType = "imm" in
|
||||
def M4_mpyri_addr : T_AddMpy<0b1, u6ExtPred,
|
||||
def M4_mpyri_addr : T_AddMpy<0b1, u32ImmPred,
|
||||
(ins IntRegs:$src1, IntRegs:$src3, u6Ext:$src2)>, ImmRegRel;
|
||||
|
||||
// Rx=add(Ru,mpyi(Rx,Rs))
|
||||
@ -2624,7 +2624,7 @@ class T_S4_ShiftOperate<string MnOp, string MnSh, SDNode Op, SDNode Sh,
|
||||
: MInst_acc<(outs IntRegs:$Rd), (ins u8Ext:$u8, IntRegs:$Rx, u5Imm:$U5),
|
||||
"$Rd = "#MnOp#"(#$u8, "#MnSh#"($Rx, #$U5))",
|
||||
[(set (i32 IntRegs:$Rd),
|
||||
(Op (Sh I32:$Rx, u5ImmPred:$U5), u8ExtPred:$u8))],
|
||||
(Op (Sh I32:$Rx, u5ImmPred:$U5), u32ImmPred:$u8))],
|
||||
"$Rd = $Rx", Itin> {
|
||||
|
||||
bits<5> Rd;
|
||||
@ -2959,7 +2959,7 @@ let isExtendable = 1, opExtendable = 1, isExtentSigned = 0 in {
|
||||
// mem[bh](Rs+#u6) += #U5
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
multiclass MemOpi_u5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
|
||||
multiclass MemOpi_u5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf ImmPred,
|
||||
InstHexagon MI, SDNode OpNode> {
|
||||
let AddedComplexity = 180 in
|
||||
def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), u5ImmPred:$addend),
|
||||
@ -2967,24 +2967,24 @@ multiclass MemOpi_u5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
|
||||
(MI IntRegs:$addr, 0, u5ImmPred:$addend)>;
|
||||
|
||||
let AddedComplexity = 190 in
|
||||
def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, ExtPred:$offset)),
|
||||
def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, ImmPred:$offset)),
|
||||
u5ImmPred:$addend),
|
||||
(add IntRegs:$base, ExtPred:$offset)),
|
||||
(MI IntRegs:$base, ExtPred:$offset, u5ImmPred:$addend)>;
|
||||
(add IntRegs:$base, ImmPred:$offset)),
|
||||
(MI IntRegs:$base, ImmPred:$offset, u5ImmPred:$addend)>;
|
||||
}
|
||||
|
||||
multiclass MemOpi_u5ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
|
||||
multiclass MemOpi_u5ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf ImmPred,
|
||||
InstHexagon addMI, InstHexagon subMI> {
|
||||
defm: MemOpi_u5Pats<ldOp, stOp, ExtPred, addMI, add>;
|
||||
defm: MemOpi_u5Pats<ldOp, stOp, ExtPred, subMI, sub>;
|
||||
defm: MemOpi_u5Pats<ldOp, stOp, ImmPred, addMI, add>;
|
||||
defm: MemOpi_u5Pats<ldOp, stOp, ImmPred, subMI, sub>;
|
||||
}
|
||||
|
||||
multiclass MemOpi_u5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
|
||||
// Half Word
|
||||
defm: MemOpi_u5ALUOp <ldOpHalf, truncstorei16, u6_1ExtPred,
|
||||
defm: MemOpi_u5ALUOp <ldOpHalf, truncstorei16, u31_1ImmPred,
|
||||
L4_iadd_memoph_io, L4_isub_memoph_io>;
|
||||
// Byte
|
||||
defm: MemOpi_u5ALUOp <ldOpByte, truncstorei8, u6ExtPred,
|
||||
defm: MemOpi_u5ALUOp <ldOpByte, truncstorei8, u32ImmPred,
|
||||
L4_iadd_memopb_io, L4_isub_memopb_io>;
|
||||
}
|
||||
|
||||
@ -2994,7 +2994,7 @@ let Predicates = [UseMEMOP] in {
|
||||
defm: MemOpi_u5ExtType<extloadi8, extloadi16>; // any extend
|
||||
|
||||
// Word
|
||||
defm: MemOpi_u5ALUOp <load, store, u6_2ExtPred, L4_iadd_memopw_io,
|
||||
defm: MemOpi_u5ALUOp <load, store, u30_2ImmPred, L4_iadd_memopw_io,
|
||||
L4_isub_memopw_io>;
|
||||
}
|
||||
|
||||
@ -3005,7 +3005,7 @@ let Predicates = [UseMEMOP] in {
|
||||
// mem[bh](Rs+#u6) += #m5
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
multiclass MemOpi_m5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
|
||||
multiclass MemOpi_m5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf ImmPred,
|
||||
PatLeaf immPred, SDNodeXForm xformFunc,
|
||||
InstHexagon MI> {
|
||||
let AddedComplexity = 190 in
|
||||
@ -3013,18 +3013,18 @@ multiclass MemOpi_m5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
|
||||
(MI IntRegs:$addr, 0, (xformFunc immPred:$subend))>;
|
||||
|
||||
let AddedComplexity = 195 in
|
||||
def: Pat<(stOp (add (ldOp (add IntRegs:$base, extPred:$offset)),
|
||||
def: Pat<(stOp (add (ldOp (add IntRegs:$base, ImmPred:$offset)),
|
||||
immPred:$subend),
|
||||
(add IntRegs:$base, extPred:$offset)),
|
||||
(MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$subend))>;
|
||||
(add IntRegs:$base, ImmPred:$offset)),
|
||||
(MI IntRegs:$base, ImmPred:$offset, (xformFunc immPred:$subend))>;
|
||||
}
|
||||
|
||||
multiclass MemOpi_m5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
|
||||
// Half Word
|
||||
defm: MemOpi_m5Pats <ldOpHalf, truncstorei16, u6_1ExtPred, m5HImmPred,
|
||||
defm: MemOpi_m5Pats <ldOpHalf, truncstorei16, u31_1ImmPred, m5HImmPred,
|
||||
MEMOPIMM_HALF, L4_isub_memoph_io>;
|
||||
// Byte
|
||||
defm: MemOpi_m5Pats <ldOpByte, truncstorei8, u6ExtPred, m5BImmPred,
|
||||
defm: MemOpi_m5Pats <ldOpByte, truncstorei8, u32ImmPred, m5BImmPred,
|
||||
MEMOPIMM_BYTE, L4_isub_memopb_io>;
|
||||
}
|
||||
|
||||
@ -3034,7 +3034,7 @@ let Predicates = [UseMEMOP] in {
|
||||
defm: MemOpi_m5ExtType<extloadi8, extloadi16>; // any extend
|
||||
|
||||
// Word
|
||||
defm: MemOpi_m5Pats <load, store, u6_2ExtPred, m5ImmPred,
|
||||
defm: MemOpi_m5Pats <load, store, u30_2ImmPred, m5ImmPred,
|
||||
MEMOPIMM, L4_isub_memopw_io>;
|
||||
}
|
||||
|
||||
@ -3063,16 +3063,16 @@ multiclass MemOpi_bitPats <PatFrag ldOp, PatFrag stOp, PatLeaf immPred,
|
||||
|
||||
multiclass MemOpi_bitExtType<PatFrag ldOpByte, PatFrag ldOpHalf> {
|
||||
// Byte - clrbit
|
||||
defm: MemOpi_bitPats<ldOpByte, truncstorei8, Clr3ImmPred, u6ExtPred,
|
||||
defm: MemOpi_bitPats<ldOpByte, truncstorei8, Clr3ImmPred, u32ImmPred,
|
||||
CLRMEMIMM_BYTE, L4_iand_memopb_io, and>;
|
||||
// Byte - setbit
|
||||
defm: MemOpi_bitPats<ldOpByte, truncstorei8, Set3ImmPred, u6ExtPred,
|
||||
defm: MemOpi_bitPats<ldOpByte, truncstorei8, Set3ImmPred, u32ImmPred,
|
||||
SETMEMIMM_BYTE, L4_ior_memopb_io, or>;
|
||||
// Half Word - clrbit
|
||||
defm: MemOpi_bitPats<ldOpHalf, truncstorei16, Clr4ImmPred, u6_1ExtPred,
|
||||
defm: MemOpi_bitPats<ldOpHalf, truncstorei16, Clr4ImmPred, u31_1ImmPred,
|
||||
CLRMEMIMM_SHORT, L4_iand_memoph_io, and>;
|
||||
// Half Word - setbit
|
||||
defm: MemOpi_bitPats<ldOpHalf, truncstorei16, Set4ImmPred, u6_1ExtPred,
|
||||
defm: MemOpi_bitPats<ldOpHalf, truncstorei16, Set4ImmPred, u31_1ImmPred,
|
||||
SETMEMIMM_SHORT, L4_ior_memoph_io, or>;
|
||||
}
|
||||
|
||||
@ -3085,9 +3085,9 @@ let Predicates = [UseMEMOP] in {
|
||||
|
||||
// memw(Rs+#0) = [clrbit|setbit](#U5)
|
||||
// memw(Rs+#u6:2) = [clrbit|setbit](#U5)
|
||||
defm: MemOpi_bitPats<load, store, Clr5ImmPred, u6_2ExtPred, CLRMEMIMM,
|
||||
defm: MemOpi_bitPats<load, store, Clr5ImmPred, u30_2ImmPred, CLRMEMIMM,
|
||||
L4_iand_memopw_io, and>;
|
||||
defm: MemOpi_bitPats<load, store, Set5ImmPred, u6_2ExtPred, SETMEMIMM,
|
||||
defm: MemOpi_bitPats<load, store, Set5ImmPred, u30_2ImmPred, SETMEMIMM,
|
||||
L4_ior_memopw_io, or>;
|
||||
}
|
||||
|
||||
@ -3125,11 +3125,11 @@ multiclass MemOPr_ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
|
||||
|
||||
multiclass MemOPr_ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
|
||||
// Half Word
|
||||
defm: MemOPr_ALUOp <ldOpHalf, truncstorei16, u6_1ExtPred,
|
||||
defm: MemOPr_ALUOp <ldOpHalf, truncstorei16, u31_1ImmPred,
|
||||
L4_add_memoph_io, L4_sub_memoph_io,
|
||||
L4_and_memoph_io, L4_or_memoph_io>;
|
||||
// Byte
|
||||
defm: MemOPr_ALUOp <ldOpByte, truncstorei8, u6ExtPred,
|
||||
defm: MemOPr_ALUOp <ldOpByte, truncstorei8, u32ImmPred,
|
||||
L4_add_memopb_io, L4_sub_memopb_io,
|
||||
L4_and_memopb_io, L4_or_memopb_io>;
|
||||
}
|
||||
@ -3141,7 +3141,7 @@ let Predicates = [UseMEMOP] in {
|
||||
defm: MemOPr_ExtType<sextloadi8, sextloadi16>; // sign extend
|
||||
defm: MemOPr_ExtType<extloadi8, extloadi16>; // any extend
|
||||
// Word
|
||||
defm: MemOPr_ALUOp <load, store, u6_2ExtPred, L4_add_memopw_io,
|
||||
defm: MemOPr_ALUOp <load, store, u30_2ImmPred, L4_add_memopw_io,
|
||||
L4_sub_memopw_io, L4_and_memopw_io, L4_or_memopw_io>;
|
||||
}
|
||||
|
||||
@ -3165,23 +3165,23 @@ def C4_cmpneqi : T_CMP <"cmp.eq", 0b00, 1, s10Ext>;
|
||||
def C4_cmpltei : T_CMP <"cmp.gt", 0b01, 1, s10Ext>;
|
||||
def C4_cmplteui : T_CMP <"cmp.gtu", 0b10, 1, u9Ext>;
|
||||
|
||||
def : T_CMP_pat <C4_cmpneqi, setne, s10ExtPred>;
|
||||
def : T_CMP_pat <C4_cmpltei, setle, s10ExtPred>;
|
||||
def : T_CMP_pat <C4_cmpneqi, setne, s32ImmPred>;
|
||||
def : T_CMP_pat <C4_cmpltei, setle, s32ImmPred>;
|
||||
def : T_CMP_pat <C4_cmplteui, setule, u9ImmPred>;
|
||||
|
||||
// rs <= rt -> !(rs > rt).
|
||||
/*
|
||||
def: Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
|
||||
(C2_not (C2_cmpgti IntRegs:$src1, s10ExtPred:$src2))>;
|
||||
// (C4_cmpltei IntRegs:$src1, s10ExtPred:$src2)>;
|
||||
def: Pat<(i1 (setle (i32 IntRegs:$src1), s32ImmPred:$src2)),
|
||||
(C2_not (C2_cmpgti IntRegs:$src1, s32ImmPred:$src2))>;
|
||||
// (C4_cmpltei IntRegs:$src1, s32ImmPred:$src2)>;
|
||||
*/
|
||||
// Map cmplt(Rs, Imm) -> !cmpgt(Rs, Imm-1).
|
||||
def: Pat<(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
|
||||
(C4_cmpltei IntRegs:$src1, (DEC_CONST_SIGNED s8ExtPred:$src2))>;
|
||||
def: Pat<(i1 (setlt (i32 IntRegs:$src1), s32ImmPred:$src2)),
|
||||
(C4_cmpltei IntRegs:$src1, (DEC_CONST_SIGNED s32ImmPred:$src2))>;
|
||||
|
||||
// rs != rt -> !(rs == rt).
|
||||
def: Pat<(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
|
||||
(C4_cmpneqi IntRegs:$src1, s10ExtPred:$src2)>;
|
||||
def: Pat<(i1 (setne (i32 IntRegs:$src1), s32ImmPred:$src2)),
|
||||
(C4_cmpneqi IntRegs:$src1, s32ImmPred:$src2)>;
|
||||
|
||||
// SDNode for converting immediate C to C-1.
|
||||
def DEC_CONST_BYTE : SDNodeXForm<imm, [{
|
||||
@ -3356,7 +3356,7 @@ class T_StoreAbs_Pred <string mnemonic, RegisterClass RC, bits<2> MajOp,
|
||||
//===----------------------------------------------------------------------===//
|
||||
class T_StoreAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
|
||||
bits<2> MajOp, bit isHalf>
|
||||
: T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, u0AlwaysExt, 1, isHalf>,
|
||||
: T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, u32Imm, 1, isHalf>,
|
||||
AddrModeRel {
|
||||
string ImmOpStr = !cast<string>(ImmOp);
|
||||
let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
|
||||
@ -3397,7 +3397,7 @@ multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC,
|
||||
let hasSideEffects = 0, isPredicable = 1, mayStore = 1, isNVStore = 1,
|
||||
isNewValue = 1, opNewValue = 1 in
|
||||
class T_StoreAbsGP_NV <string mnemonic, Operand ImmOp, bits<2>MajOp, bit isAbs>
|
||||
: NVInst_V4<(outs), (ins u0AlwaysExt:$addr, IntRegs:$src),
|
||||
: NVInst_V4<(outs), (ins u32Imm:$addr, IntRegs:$src),
|
||||
mnemonic # !if(isAbs, "(##", "(#")#"$addr) = $src.new",
|
||||
[], "", V2LDST_tc_st_SLOT0> {
|
||||
bits<19> addr;
|
||||
@ -3627,7 +3627,7 @@ class T_LoadAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
|
||||
|
||||
class T_LoadAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
|
||||
bits<3> MajOp>
|
||||
: T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, u0AlwaysExt, 1>, AddrModeRel {
|
||||
: T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, u32Imm, 1>, AddrModeRel {
|
||||
|
||||
string ImmOpStr = !cast<string>(ImmOp);
|
||||
let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
|
||||
@ -3787,17 +3787,17 @@ def: Pat<(i64 (ctlz I64:$src1)), (Zext64 (S2_cl0p I64:$src1))>;
|
||||
def: Pat<(i64 (cttz I64:$src1)), (Zext64 (S2_ct0p I64:$src1))>;
|
||||
|
||||
let AddedComplexity = 30 in {
|
||||
def: Storea_pat<truncstorei8, I32, u0AlwaysExtPred, S2_storerbabs>;
|
||||
def: Storea_pat<truncstorei16, I32, u0AlwaysExtPred, S2_storerhabs>;
|
||||
def: Storea_pat<store, I32, u0AlwaysExtPred, S2_storeriabs>;
|
||||
def: Storea_pat<truncstorei8, I32, u32ImmPred, S2_storerbabs>;
|
||||
def: Storea_pat<truncstorei16, I32, u32ImmPred, S2_storerhabs>;
|
||||
def: Storea_pat<store, I32, u32ImmPred, S2_storeriabs>;
|
||||
}
|
||||
|
||||
let AddedComplexity = 30 in {
|
||||
def: Loada_pat<load, i32, u0AlwaysExtPred, L4_loadri_abs>;
|
||||
def: Loada_pat<sextloadi8, i32, u0AlwaysExtPred, L4_loadrb_abs>;
|
||||
def: Loada_pat<zextloadi8, i32, u0AlwaysExtPred, L4_loadrub_abs>;
|
||||
def: Loada_pat<sextloadi16, i32, u0AlwaysExtPred, L4_loadrh_abs>;
|
||||
def: Loada_pat<zextloadi16, i32, u0AlwaysExtPred, L4_loadruh_abs>;
|
||||
def: Loada_pat<load, i32, u32ImmPred, L4_loadri_abs>;
|
||||
def: Loada_pat<sextloadi8, i32, u32ImmPred, L4_loadrb_abs>;
|
||||
def: Loada_pat<zextloadi8, i32, u32ImmPred, L4_loadrub_abs>;
|
||||
def: Loada_pat<sextloadi16, i32, u32ImmPred, L4_loadrh_abs>;
|
||||
def: Loada_pat<zextloadi16, i32, u32ImmPred, L4_loadruh_abs>;
|
||||
}
|
||||
|
||||
// Indexed store word - global address.
|
||||
|
||||
@ -139,11 +139,11 @@ def S5_popcountp : ALU64_rr<(outs IntRegs:$Rd), (ins DoubleRegs:$Rss),
|
||||
let Inst{20-16} = Rss;
|
||||
}
|
||||
|
||||
defm: Loadx_pat<load, f32, s11_2ExtPred, L2_loadri_io>;
|
||||
defm: Loadx_pat<load, f64, s11_3ExtPred, L2_loadrd_io>;
|
||||
defm: Loadx_pat<load, f32, s30_2ImmPred, L2_loadri_io>;
|
||||
defm: Loadx_pat<load, f64, s29_3ImmPred, L2_loadrd_io>;
|
||||
|
||||
defm: Storex_pat<store, F32, s11_2ExtPred, S2_storeri_io>;
|
||||
defm: Storex_pat<store, F64, s11_3ExtPred, S2_storerd_io>;
|
||||
defm: Storex_pat<store, F32, s30_2ImmPred, S2_storeri_io>;
|
||||
defm: Storex_pat<store, F64, s29_3ImmPred, S2_storerd_io>;
|
||||
def: Storex_simple_pat<store, F32, S2_storeri_io>;
|
||||
def: Storex_simple_pat<store, F64, S2_storerd_io>;
|
||||
|
||||
|
||||
@ -690,16 +690,15 @@ def: T_RR_pat<A2_combine_hl, int_hexagon_A2_combine_hl>;
|
||||
def: T_RR_pat<A2_combine_lh, int_hexagon_A2_combine_lh>;
|
||||
def: T_RR_pat<A2_combine_ll, int_hexagon_A2_combine_ll>;
|
||||
|
||||
def: T_II_pat<A2_combineii, int_hexagon_A2_combineii, s8ExtPred, s8ImmPred>;
|
||||
def: T_II_pat<A2_combineii, int_hexagon_A2_combineii, s32ImmPred, s8ImmPred>;
|
||||
|
||||
def: Pat<(i32 (int_hexagon_C2_mux (I32:$Rp), (I32:$Rs),
|
||||
(I32:$Rt))),
|
||||
def: Pat<(i32 (int_hexagon_C2_mux (I32:$Rp), (I32:$Rs), (I32:$Rt))),
|
||||
(i32 (C2_mux (C2_tfrrp IntRegs:$Rp), IntRegs:$Rs, IntRegs:$Rt))>;
|
||||
|
||||
// Mux
|
||||
def : T_QRI_pat<C2_muxir, int_hexagon_C2_muxir, s8ExtPred>;
|
||||
def : T_QIR_pat<C2_muxri, int_hexagon_C2_muxri, s8ExtPred>;
|
||||
def : T_QII_pat<C2_muxii, int_hexagon_C2_muxii, s8ExtPred, s8ImmPred>;
|
||||
def : T_QRI_pat<C2_muxir, int_hexagon_C2_muxir, s32ImmPred>;
|
||||
def : T_QIR_pat<C2_muxri, int_hexagon_C2_muxri, s32ImmPred>;
|
||||
def : T_QII_pat<C2_muxii, int_hexagon_C2_muxii, s32ImmPred, s8ImmPred>;
|
||||
|
||||
// Shift halfword
|
||||
def : T_R_pat<A2_aslh, int_hexagon_A2_aslh>;
|
||||
@ -720,17 +719,17 @@ def : T_RR_pat<C2_cmpeq, int_hexagon_C2_cmpeq>;
|
||||
def : T_RR_pat<C2_cmpgt, int_hexagon_C2_cmpgt>;
|
||||
def : T_RR_pat<C2_cmpgtu, int_hexagon_C2_cmpgtu>;
|
||||
|
||||
def : T_RI_pat<C2_cmpeqi, int_hexagon_C2_cmpeqi, s10ExtPred>;
|
||||
def : T_RI_pat<C2_cmpgti, int_hexagon_C2_cmpgti, s10ExtPred>;
|
||||
def : T_RI_pat<C2_cmpgtui, int_hexagon_C2_cmpgtui, u9ExtPred>;
|
||||
def : T_RI_pat<C2_cmpeqi, int_hexagon_C2_cmpeqi, s32ImmPred>;
|
||||
def : T_RI_pat<C2_cmpgti, int_hexagon_C2_cmpgti, s32ImmPred>;
|
||||
def : T_RI_pat<C2_cmpgtui, int_hexagon_C2_cmpgtui, u32ImmPred>;
|
||||
|
||||
def : Pat <(i32 (int_hexagon_C2_cmpgei (I32:$src1), s8ExtPred:$src2)),
|
||||
def : Pat <(i32 (int_hexagon_C2_cmpgei (I32:$src1), s32ImmPred:$src2)),
|
||||
(i32 (C2_cmpgti (I32:$src1),
|
||||
(DEC_CONST_SIGNED s8ExtPred:$src2)))>;
|
||||
(DEC_CONST_SIGNED s32ImmPred:$src2)))>;
|
||||
|
||||
def : Pat <(i32 (int_hexagon_C2_cmpgeui (I32:$src1), u8ExtPred:$src2)),
|
||||
def : Pat <(i32 (int_hexagon_C2_cmpgeui (I32:$src1), u32ImmPred:$src2)),
|
||||
(i32 (C2_cmpgtui (I32:$src1),
|
||||
(DEC_CONST_UNSIGNED u8ExtPred:$src2)))>;
|
||||
(DEC_CONST_UNSIGNED u32ImmPred:$src2)))>;
|
||||
|
||||
// The instruction, Pd=cmp.geu(Rs, #u8) -> Pd=cmp.eq(Rs,Rs) when #u8 == 0.
|
||||
def : Pat <(i32 (int_hexagon_C2_cmpgeui (I32:$src1), 0)),
|
||||
|
||||
@ -234,17 +234,17 @@ def: T_RR_pat<A4_orn, int_hexagon_A4_orn>;
|
||||
*********************************************************************/
|
||||
|
||||
// Combine Words Into Doublewords.
|
||||
def: T_RI_pat<A4_combineri, int_hexagon_A4_combineri, s8ExtPred>;
|
||||
def: T_IR_pat<A4_combineir, int_hexagon_A4_combineir, s8ExtPred>;
|
||||
def: T_RI_pat<A4_combineri, int_hexagon_A4_combineri, s32ImmPred>;
|
||||
def: T_IR_pat<A4_combineir, int_hexagon_A4_combineir, s32ImmPred>;
|
||||
|
||||
/********************************************************************
|
||||
* ALU32/PRED *
|
||||
*********************************************************************/
|
||||
|
||||
// Compare
|
||||
def : T_RI_pat<C4_cmpneqi, int_hexagon_C4_cmpneqi, s10ExtPred>;
|
||||
def : T_RI_pat<C4_cmpltei, int_hexagon_C4_cmpltei, s10ExtPred>;
|
||||
def : T_RI_pat<C4_cmplteui, int_hexagon_C4_cmplteui, u9ExtPred>;
|
||||
def : T_RI_pat<C4_cmpneqi, int_hexagon_C4_cmpneqi, s32ImmPred>;
|
||||
def : T_RI_pat<C4_cmpltei, int_hexagon_C4_cmpltei, s32ImmPred>;
|
||||
def : T_RI_pat<C4_cmplteui, int_hexagon_C4_cmplteui, u32ImmPred>;
|
||||
|
||||
def: T_RR_pat<A4_rcmpeq, int_hexagon_A4_rcmpeq>;
|
||||
def: T_RR_pat<A4_rcmpneq, int_hexagon_A4_rcmpneq>;
|
||||
|
||||
@ -66,162 +66,131 @@ def nOneImm : Operand<i32>;
|
||||
// Immediate predicates
|
||||
//
|
||||
def s32ImmPred : PatLeaf<(i32 imm), [{
|
||||
// s32ImmPred predicate - True if the immediate fits in a 32-bit sign extended
|
||||
// field.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isInt<32>(v);
|
||||
}]>;
|
||||
|
||||
def s32_24ImmPred : PatLeaf<(i32 imm), [{
|
||||
// s32_24ImmPred predicate - True if the immediate fits in a 32-bit sign
|
||||
// extended field that is a multiple of 0x1000000.
|
||||
def s32_0ImmPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isShiftedInt<32,24>(v);
|
||||
return isInt<32>(v);
|
||||
}]>;
|
||||
|
||||
def s32_16s8ImmPred : PatLeaf<(i32 imm), [{
|
||||
// s32_16s8ImmPred predicate - True if the immediate fits in a 32-bit sign
|
||||
// extended field that is a multiple of 0x10000.
|
||||
def s31_1ImmPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isShiftedInt<24,16>(v);
|
||||
return isShiftedInt<31,1>(v);
|
||||
}]>;
|
||||
|
||||
def s30_2ImmPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isShiftedInt<31,1>(v);
|
||||
}]>;
|
||||
|
||||
def s29_3ImmPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isShiftedInt<31,1>(v);
|
||||
}]>;
|
||||
|
||||
def s22_10ImmPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isShiftedInt<22,10>(v);
|
||||
}]>;
|
||||
|
||||
def s8_24ImmPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isShiftedInt<8,24>(v);
|
||||
}]>;
|
||||
|
||||
def s16_16ImmPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isShiftedInt<16,16>(v);
|
||||
}]>;
|
||||
|
||||
def s26_6ImmPred : PatLeaf<(i32 imm), [{
|
||||
// s26_6ImmPred predicate - True if the immediate fits in a 32-bit
|
||||
// sign extended field.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isShiftedInt<26,6>(v);
|
||||
}]>;
|
||||
|
||||
|
||||
def s16ImmPred : PatLeaf<(i32 imm), [{
|
||||
// s16ImmPred predicate - True if the immediate fits in a 16-bit sign extended
|
||||
// field.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isInt<16>(v);
|
||||
}]>;
|
||||
|
||||
|
||||
def s13ImmPred : PatLeaf<(i32 imm), [{
|
||||
// s13ImmPred predicate - True if the immediate fits in a 13-bit sign extended
|
||||
// field.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isInt<13>(v);
|
||||
}]>;
|
||||
|
||||
|
||||
def s12ImmPred : PatLeaf<(i32 imm), [{
|
||||
// s12ImmPred predicate - True if the immediate fits in a 12-bit
|
||||
// sign extended field.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isInt<12>(v);
|
||||
}]>;
|
||||
|
||||
def s11_0ImmPred : PatLeaf<(i32 imm), [{
|
||||
// s11_0ImmPred predicate - True if the immediate fits in a 11-bit
|
||||
// sign extended field.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isInt<11>(v);
|
||||
}]>;
|
||||
|
||||
|
||||
def s11_1ImmPred : PatLeaf<(i32 imm), [{
|
||||
// s11_1ImmPred predicate - True if the immediate fits in a 12-bit
|
||||
// sign extended field and is a multiple of 2.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isShiftedInt<11,1>(v);
|
||||
}]>;
|
||||
|
||||
|
||||
def s11_2ImmPred : PatLeaf<(i32 imm), [{
|
||||
// s11_2ImmPred predicate - True if the immediate fits in a 13-bit
|
||||
// sign extended field and is a multiple of 4.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isShiftedInt<11,2>(v);
|
||||
}]>;
|
||||
|
||||
|
||||
def s11_3ImmPred : PatLeaf<(i32 imm), [{
|
||||
// s11_3ImmPred predicate - True if the immediate fits in a 14-bit
|
||||
// sign extended field and is a multiple of 8.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isShiftedInt<11,3>(v);
|
||||
}]>;
|
||||
|
||||
|
||||
def s10ImmPred : PatLeaf<(i32 imm), [{
|
||||
// s10ImmPred predicate - True if the immediate fits in a 10-bit sign extended
|
||||
// field.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isInt<10>(v);
|
||||
}]>;
|
||||
|
||||
|
||||
def s9ImmPred : PatLeaf<(i32 imm), [{
|
||||
// s9ImmPred predicate - True if the immediate fits in a 9-bit sign extended
|
||||
// field.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isInt<9>(v);
|
||||
}]>;
|
||||
|
||||
def m9ImmPred : PatLeaf<(i32 imm), [{
|
||||
// m9ImmPred predicate - True if the immediate fits in a 9-bit magnitude
|
||||
// field. The range of m9 is -255 to 255.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isInt<9>(v) && (v != -256);
|
||||
}]>;
|
||||
|
||||
def s8ImmPred : PatLeaf<(i32 imm), [{
|
||||
// s8ImmPred predicate - True if the immediate fits in a 8-bit sign extended
|
||||
// field.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isInt<8>(v);
|
||||
}]>;
|
||||
|
||||
|
||||
def s8Imm64Pred : PatLeaf<(i64 imm), [{
|
||||
// s8ImmPred predicate - True if the immediate fits in a 8-bit sign extended
|
||||
// field.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isInt<8>(v);
|
||||
}]>;
|
||||
|
||||
|
||||
def s6ImmPred : PatLeaf<(i32 imm), [{
|
||||
// s6ImmPred predicate - True if the immediate fits in a 6-bit sign extended
|
||||
// field.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isInt<6>(v);
|
||||
}]>;
|
||||
|
||||
|
||||
def s4_0ImmPred : PatLeaf<(i32 imm), [{
|
||||
// s4_0ImmPred predicate - True if the immediate fits in a 4-bit sign extended
|
||||
// field.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isInt<4>(v);
|
||||
}]>;
|
||||
|
||||
|
||||
def s4_1ImmPred : PatLeaf<(i32 imm), [{
|
||||
// s4_1ImmPred predicate - True if the immediate fits in a 4-bit sign extended
|
||||
// field of 2.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isShiftedInt<4,1>(v);
|
||||
}]>;
|
||||
|
||||
|
||||
def s4_2ImmPred : PatLeaf<(i32 imm), [{
|
||||
// s4_2ImmPred predicate - True if the immediate fits in a 4-bit sign extended
|
||||
// field that is a multiple of 4.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isShiftedInt<4,2>(v);
|
||||
}]>;
|
||||
|
||||
|
||||
def s4_3ImmPred : PatLeaf<(i32 imm), [{
|
||||
// s4_3ImmPred predicate - True if the immediate fits in a 4-bit sign extended
|
||||
// field that is a multiple of 8.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isShiftedInt<4,3>(v);
|
||||
}]>;
|
||||
@ -233,56 +202,61 @@ def u64ImmPred : PatLeaf<(i64 imm), [{
|
||||
}]>;
|
||||
|
||||
def u32ImmPred : PatLeaf<(i32 imm), [{
|
||||
// u32ImmPred predicate - True if the immediate fits in a 32-bit field.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isUInt<32>(v);
|
||||
}]>;
|
||||
|
||||
def u32_0ImmPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isUInt<32>(v);
|
||||
}]>;
|
||||
|
||||
def u31_1ImmPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isShiftedUInt<31,1>(v);
|
||||
}]>;
|
||||
|
||||
def u30_2ImmPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isShiftedUInt<30,2>(v);
|
||||
}]>;
|
||||
|
||||
def u29_3ImmPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isShiftedUInt<29,3>(v);
|
||||
}]>;
|
||||
|
||||
def u26_6ImmPred : PatLeaf<(i32 imm), [{
|
||||
// u26_6ImmPred - True if the immediate fits in a 32-bit field and
|
||||
// is a multiple of 64.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isShiftedUInt<26,6>(v);
|
||||
}]>;
|
||||
|
||||
def u16ImmPred : PatLeaf<(i32 imm), [{
|
||||
// u16ImmPred predicate - True if the immediate fits in a 16-bit unsigned
|
||||
// field.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isUInt<16>(v);
|
||||
}]>;
|
||||
|
||||
def u16_s8ImmPred : PatLeaf<(i32 imm), [{
|
||||
// u16_s8ImmPred predicate - True if the immediate fits in a 16-bit sign
|
||||
// extended s8 field.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isShiftedUInt<16,8>(v);
|
||||
}]>;
|
||||
|
||||
def u16_0ImmPred : PatLeaf<(i32 imm), [{
|
||||
// True if the immediate fits in a 16-bit unsigned field.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isUInt<16>(v);
|
||||
}]>;
|
||||
|
||||
def u11_3ImmPred : PatLeaf<(i32 imm), [{
|
||||
// True if the immediate fits in a 14-bit unsigned field, and the lowest
|
||||
// three bits are 0.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isShiftedUInt<11,3>(v);
|
||||
}]>;
|
||||
|
||||
def u9ImmPred : PatLeaf<(i32 imm), [{
|
||||
// u9ImmPred predicate - True if the immediate fits in a 9-bit unsigned
|
||||
// field.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isUInt<9>(v);
|
||||
}]>;
|
||||
|
||||
|
||||
def u8ImmPred : PatLeaf<(i32 imm), [{
|
||||
// u8ImmPred predicate - True if the immediate fits in a 8-bit unsigned
|
||||
// field.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isUInt<8>(v);
|
||||
}]>;
|
||||
@ -294,81 +268,56 @@ def u7StrictPosImmPred : ImmLeaf<i32, [{
|
||||
}]>;
|
||||
|
||||
def u7ImmPred : PatLeaf<(i32 imm), [{
|
||||
// u7ImmPred predicate - True if the immediate fits in a 7-bit unsigned
|
||||
// field.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isUInt<7>(v);
|
||||
}]>;
|
||||
|
||||
|
||||
def u6ImmPred : PatLeaf<(i32 imm), [{
|
||||
// u6ImmPred predicate - True if the immediate fits in a 6-bit unsigned
|
||||
// field.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isUInt<6>(v);
|
||||
}]>;
|
||||
|
||||
def u6_0ImmPred : PatLeaf<(i32 imm), [{
|
||||
// u6_0ImmPred predicate - True if the immediate fits in a 6-bit unsigned
|
||||
// field. Same as u6ImmPred.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isUInt<6>(v);
|
||||
}]>;
|
||||
|
||||
def u6_1ImmPred : PatLeaf<(i32 imm), [{
|
||||
// u6_1ImmPred predicate - True if the immediate fits in a 7-bit unsigned
|
||||
// field that is 1 bit alinged - multiple of 2.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isShiftedUInt<6,1>(v);
|
||||
}]>;
|
||||
|
||||
def u6_2ImmPred : PatLeaf<(i32 imm), [{
|
||||
// u6_2ImmPred predicate - True if the immediate fits in a 8-bit unsigned
|
||||
// field that is 2 bits alinged - multiple of 4.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isShiftedUInt<6,2>(v);
|
||||
}]>;
|
||||
|
||||
def u6_3ImmPred : PatLeaf<(i32 imm), [{
|
||||
// u6_3ImmPred predicate - True if the immediate fits in a 9-bit unsigned
|
||||
// field that is 3 bits alinged - multiple of 8.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isShiftedUInt<6,3>(v);
|
||||
}]>;
|
||||
|
||||
def u5ImmPred : PatLeaf<(i32 imm), [{
|
||||
// u5ImmPred predicate - True if the immediate fits in a 5-bit unsigned
|
||||
// field.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isUInt<5>(v);
|
||||
}]>;
|
||||
|
||||
def u4ImmPred : PatLeaf<(i32 imm), [{
|
||||
// u4ImmPred predicate - True if the immediate fits in a 4-bit unsigned
|
||||
// field.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isUInt<4>(v);
|
||||
}]>;
|
||||
|
||||
def u3ImmPred : PatLeaf<(i32 imm), [{
|
||||
// u3ImmPred predicate - True if the immediate fits in a 3-bit unsigned
|
||||
// field.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isUInt<3>(v);
|
||||
}]>;
|
||||
|
||||
|
||||
def u2ImmPred : PatLeaf<(i32 imm), [{
|
||||
// u2ImmPred predicate - True if the immediate fits in a 2-bit unsigned
|
||||
// field.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isUInt<2>(v);
|
||||
}]>;
|
||||
|
||||
|
||||
def u1ImmPred : PatLeaf<(i1 imm), [{
|
||||
// u1ImmPred predicate - True if the immediate fits in a 1-bit unsigned
|
||||
// field.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isUInt<1>(v);
|
||||
}]>;
|
||||
@ -511,212 +460,6 @@ let PrintMethod = "printExtOperand" in {
|
||||
def u6_3Ext : Operand<i32>;
|
||||
}
|
||||
|
||||
let PrintMethod = "printImmOperand" in
|
||||
def u0AlwaysExt : Operand<i32>;
|
||||
|
||||
// Predicates for constant extendable operands
|
||||
def s16ExtPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
if (isInt<16>(v))
|
||||
return true;
|
||||
|
||||
// Return true if extending this immediate is profitable and the value
|
||||
// can fit in a 32-bit signed field.
|
||||
return isConstExtProfitable(Node) && isInt<32>(v);
|
||||
}]>;
|
||||
|
||||
def s10ExtPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
if (isInt<10>(v))
|
||||
return true;
|
||||
|
||||
// Return true if extending this immediate is profitable and the value
|
||||
// can fit in a 32-bit signed field.
|
||||
return isConstExtProfitable(Node) && isInt<32>(v);
|
||||
}]>;
|
||||
|
||||
def s9ExtPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
if (isInt<9>(v))
|
||||
return true;
|
||||
|
||||
// Return true if extending this immediate is profitable and the value
|
||||
// can fit in a 32-bit unsigned field.
|
||||
return isConstExtProfitable(Node) && isInt<32>(v);
|
||||
}]>;
|
||||
|
||||
def s8ExtPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
if (isInt<8>(v))
|
||||
return true;
|
||||
|
||||
// Return true if extending this immediate is profitable and the value
|
||||
// can fit in a 32-bit signed field.
|
||||
return isConstExtProfitable(Node) && isInt<32>(v);
|
||||
}]>;
|
||||
|
||||
def s8_16ExtPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
if (isInt<8>(v))
|
||||
return true;
|
||||
|
||||
// Return true if extending this immediate is profitable and the value
|
||||
// can't fit in a 16-bit signed field. This is required to avoid
|
||||
// unnecessary constant extenders.
|
||||
return isConstExtProfitable(Node) && !isInt<16>(v);
|
||||
}]>;
|
||||
|
||||
def s6ExtPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
if (isInt<6>(v))
|
||||
return true;
|
||||
|
||||
// Return true if extending this immediate is profitable and the value
|
||||
// can fit in a 32-bit unsigned field.
|
||||
return isConstExtProfitable(Node) && isInt<32>(v);
|
||||
}]>;
|
||||
|
||||
def s6_16ExtPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
if (isInt<6>(v))
|
||||
return true;
|
||||
|
||||
// Return true if extending this immediate is profitable and the value
|
||||
// can't fit in a 16-bit signed field. This is required to avoid
|
||||
// unnecessary constant extenders.
|
||||
return isConstExtProfitable(Node) && !isInt<16>(v);
|
||||
}]>;
|
||||
|
||||
def s6_10ExtPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
if (isInt<6>(v))
|
||||
return true;
|
||||
|
||||
// Return true if extending this immediate is profitable and the value
|
||||
// can't fit in a 10-bit signed field. This is required to avoid
|
||||
// unnecessary constant extenders.
|
||||
return isConstExtProfitable(Node) && !isInt<10>(v);
|
||||
}]>;
|
||||
|
||||
def s11_0ExtPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
if (isInt<11>(v))
|
||||
return true;
|
||||
|
||||
// Return true if extending this immediate is profitable and the value
|
||||
// can fit in a 32-bit signed field.
|
||||
return isConstExtProfitable(Node) && isInt<32>(v);
|
||||
}]>;
|
||||
|
||||
def s11_1ExtPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
if (isInt<12>(v))
|
||||
return isShiftedInt<11,1>(v);
|
||||
|
||||
// Return true if extending this immediate is profitable and the low 1 bit
|
||||
// is zero (2-byte aligned).
|
||||
return isConstExtProfitable(Node) && isInt<32>(v) && ((v % 2) == 0);
|
||||
}]>;
|
||||
|
||||
def s11_2ExtPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
if (isInt<13>(v))
|
||||
return isShiftedInt<11,2>(v);
|
||||
|
||||
// Return true if extending this immediate is profitable and the low 2-bits
|
||||
// are zero (4-byte aligned).
|
||||
return isConstExtProfitable(Node) && isInt<32>(v) && ((v % 4) == 0);
|
||||
}]>;
|
||||
|
||||
def s11_3ExtPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
if (isInt<14>(v))
|
||||
return isShiftedInt<11,3>(v);
|
||||
|
||||
// Return true if extending this immediate is profitable and the low 3-bits
|
||||
// are zero (8-byte aligned).
|
||||
return isConstExtProfitable(Node) && isInt<32>(v) && ((v % 8) == 0);
|
||||
}]>;
|
||||
|
||||
def u0AlwaysExtPred : PatLeaf<(i32 imm), [{
|
||||
// Predicate for an unsigned 32-bit value that always needs to be extended.
|
||||
if (isConstExtProfitable(Node)) {
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isUInt<32>(v);
|
||||
}
|
||||
return false;
|
||||
}]>;
|
||||
|
||||
def u6ExtPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
if (isUInt<6>(v))
|
||||
return true;
|
||||
|
||||
// Return true if extending this immediate is profitable and the value
|
||||
// can fit in a 32-bit unsigned field.
|
||||
return isConstExtProfitable(Node) && isUInt<32>(v);
|
||||
}]>;
|
||||
|
||||
def u7ExtPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
if (isUInt<7>(v))
|
||||
return true;
|
||||
|
||||
// Return true if extending this immediate is profitable and the value
|
||||
// can fit in a 32-bit unsigned field.
|
||||
return isConstExtProfitable(Node) && isUInt<32>(v);
|
||||
}]>;
|
||||
|
||||
def u8ExtPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
if (isUInt<8>(v))
|
||||
return true;
|
||||
|
||||
// Return true if extending this immediate is profitable and the value
|
||||
// can fit in a 32-bit unsigned field.
|
||||
return isConstExtProfitable(Node) && isUInt<32>(v);
|
||||
}]>;
|
||||
|
||||
def u9ExtPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
if (isUInt<9>(v))
|
||||
return true;
|
||||
|
||||
// Return true if extending this immediate is profitable and the value
|
||||
// can fit in a 32-bit unsigned field.
|
||||
return isConstExtProfitable(Node) && isUInt<32>(v);
|
||||
}]>;
|
||||
|
||||
def u6_1ExtPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
if (isUInt<7>(v))
|
||||
return isShiftedUInt<6,1>(v);
|
||||
|
||||
// Return true if extending this immediate is profitable and the value
|
||||
// can fit in a 32-bit unsigned field.
|
||||
return isConstExtProfitable(Node) && isUInt<32>(v) && ((v % 2) == 0);
|
||||
}]>;
|
||||
|
||||
def u6_2ExtPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
if (isUInt<8>(v))
|
||||
return isShiftedUInt<6,2>(v);
|
||||
|
||||
// Return true if extending this immediate is profitable and the value
|
||||
// can fit in a 32-bit unsigned field.
|
||||
return isConstExtProfitable(Node) && isUInt<32>(v) && ((v % 4) == 0);
|
||||
}]>;
|
||||
|
||||
def u6_3ExtPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
if (isUInt<9>(v))
|
||||
return isShiftedUInt<6,3>(v);
|
||||
|
||||
// Return true if extending this immediate is profitable and the value
|
||||
// can fit in a 32-bit unsigned field.
|
||||
return isConstExtProfitable(Node) && isUInt<32>(v) && ((v % 8) == 0);
|
||||
}]>;
|
||||
|
||||
|
||||
// This complex pattern exists only to create a machine instruction operand
|
||||
// of type "frame index". There doesn't seem to be a way to do that directly
|
||||
|
||||
Loading…
Reference in New Issue
Block a user