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[mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics)
Changes to MIPS SelectionDAG: * Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single operation and implemented the DAG combines necessary to fold sign/zero extends into the extract. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191199 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
parent
a399d698a8
commit
9a1aaeb012
@ -779,18 +779,18 @@ def int_mips_clti_u_d : GCCBuiltin<"__builtin_msa_clti_u_d">,
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Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_mips_copy_s_b : GCCBuiltin<"__builtin_msa_copy_s_b">,
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Intrinsic<[llvm_i32_ty], [llvm_v16i8_ty, llvm_i32_ty], []>;
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Intrinsic<[llvm_i32_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_mips_copy_s_h : GCCBuiltin<"__builtin_msa_copy_s_h">,
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Intrinsic<[llvm_i32_ty], [llvm_v8i16_ty, llvm_i32_ty], []>;
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Intrinsic<[llvm_i32_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_mips_copy_s_w : GCCBuiltin<"__builtin_msa_copy_s_w">,
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Intrinsic<[llvm_i32_ty], [llvm_v4i32_ty, llvm_i32_ty], []>;
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Intrinsic<[llvm_i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_mips_copy_u_b : GCCBuiltin<"__builtin_msa_copy_u_b">,
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Intrinsic<[llvm_i32_ty], [llvm_v16i8_ty, llvm_i32_ty], []>;
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Intrinsic<[llvm_i32_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_mips_copy_u_h : GCCBuiltin<"__builtin_msa_copy_u_h">,
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Intrinsic<[llvm_i32_ty], [llvm_v8i16_ty, llvm_i32_ty], []>;
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Intrinsic<[llvm_i32_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_mips_copy_u_w : GCCBuiltin<"__builtin_msa_copy_u_w">,
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Intrinsic<[llvm_i32_ty], [llvm_v4i32_ty, llvm_i32_ty], []>;
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Intrinsic<[llvm_i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_mips_ctcmsa : GCCBuiltin<"__builtin_msa_ctcmsa">,
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>;
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@ -214,6 +214,8 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO";
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case MipsISD::VSPLAT: return "MipsISD::VSPLAT";
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case MipsISD::VSPLATD: return "MipsISD::VSPLATD";
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case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
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case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
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case MipsISD::VNOR: return "MipsISD::VNOR";
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default: return NULL;
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}
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@ -167,6 +167,10 @@ namespace llvm {
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// Combined (XOR (OR $a, $b), -1)
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VNOR,
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// Extended vector element extraction
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VEXTRACT_SEXT_ELT,
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VEXTRACT_ZEXT_ELT,
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// Load/Store Left/Right nodes.
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LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
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LWR,
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@ -23,6 +23,33 @@ def MipsVSplatD : SDNode<"MipsISD::VSPLATD", SDT_MipsSplat>;
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def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT",
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SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
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def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT",
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SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
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// Pattern fragments
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def vextract_sext_i8 : PatFrag<(ops node:$vec, node:$idx),
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(MipsVExtractSExt node:$vec, node:$idx, i8)>;
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def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx),
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(MipsVExtractSExt node:$vec, node:$idx, i16)>;
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def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx),
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(MipsVExtractSExt node:$vec, node:$idx, i32)>;
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def vextract_zext_i8 : PatFrag<(ops node:$vec, node:$idx),
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(MipsVExtractZExt node:$vec, node:$idx, i8)>;
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def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx),
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(MipsVExtractZExt node:$vec, node:$idx, i16)>;
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def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx),
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(MipsVExtractZExt node:$vec, node:$idx, i32)>;
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def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx),
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(v16i8 (vector_insert node:$vec, node:$val, node:$idx))>;
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def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx),
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(v8i16 (vector_insert node:$vec, node:$val, node:$idx))>;
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def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx),
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(v4i32 (vector_insert node:$vec, node:$val, node:$idx))>;
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def vsplati8 : PatFrag<(ops node:$in), (v16i8 (MipsVSplat (i32 node:$in)))>;
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def vsplati16 : PatFrag<(ops node:$in), (v8i16 (MipsVSplat (i32 node:$in)))>;
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def vsplati32 : PatFrag<(ops node:$in), (v4i32 (MipsVSplat (i32 node:$in)))>;
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@ -805,12 +832,12 @@ class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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}
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class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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RegisterClass RCD, RegisterClass RCWS,
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ValueType VecTy, RegisterClass RCD, RegisterClass RCWS,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs RCD:$rd);
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dag InOperandList = (ins RCWS:$ws, uimm6:$n);
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dag InOperandList = (ins RCWS:$ws, uimm4:$n);
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string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]");
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list<dag> Pattern = [(set RCD:$rd, (OpNode RCWS:$ws, immZExt6:$n))];
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list<dag> Pattern = [(set RCD:$rd, (OpNode (VecTy RCWS:$ws), immZExt4:$n))];
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InstrItinClass Itinerary = itin;
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}
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@ -922,11 +949,11 @@ class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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RegisterClass RCD, RegisterClass RCWS,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs RCD:$wd);
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dag InOperandList = (ins RCD:$wd_in, uimm6:$n, RCWS:$rs);
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dag InOperandList = (ins RCD:$wd_in, RCWS:$rs, uimm6:$n);
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string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs");
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list<dag> Pattern = [(set RCD:$wd, (OpNode RCD:$wd_in,
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immZExt6:$n,
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RCWS:$rs))];
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RCWS:$rs,
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immZExt6:$n))];
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InstrItinClass Itinerary = itin;
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string Constraints = "$wd = $wd_in";
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}
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@ -1222,18 +1249,18 @@ class CLTI_U_W_DESC : MSA_SI5_DESC_BASE<"clti_u.w", int_mips_clti_u_w,
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class CLTI_U_D_DESC : MSA_SI5_DESC_BASE<"clti_u.d", int_mips_clti_u_d,
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MSA128D>;
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class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", int_mips_copy_s_b,
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class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8, v16i8,
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GPR32, MSA128B>;
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class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", int_mips_copy_s_h,
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class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16,
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GPR32, MSA128H>;
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class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", int_mips_copy_s_w,
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class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32,
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GPR32, MSA128W>;
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class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", int_mips_copy_u_b,
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class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8, v16i8,
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GPR32, MSA128B>;
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class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", int_mips_copy_u_h,
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class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16,
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GPR32, MSA128H>;
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class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", int_mips_copy_u_w,
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class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32,
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GPR32, MSA128W>;
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class CTCMSA_DESC {
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@ -1561,12 +1588,12 @@ class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", int_mips_ilvr_h, MSA128H>;
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class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", int_mips_ilvr_w, MSA128W>;
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class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", int_mips_ilvr_d, MSA128D>;
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class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", int_mips_insert_b,
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MSA128B, GPR32>;
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class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", int_mips_insert_h,
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MSA128H, GPR32>;
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class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", int_mips_insert_w,
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MSA128W, GPR32>;
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class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8, MSA128B,
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GPR32>;
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class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16, MSA128H,
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GPR32>;
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class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32, MSA128W,
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GPR32>;
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class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", int_mips_insve_b, MSA128B>;
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class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", int_mips_insve_h, MSA128H>;
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@ -2689,6 +2716,9 @@ def XORI_B : XORI_B_ENC, XORI_B_DESC;
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class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> :
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Pat<pattern, result>, Requires<pred>;
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def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx),
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(COPY_S_W MSA128W:$ws, immZExt4:$idx)>;
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def : MSAPat<(v16i8 (load addr:$addr)), (LD_B addr:$addr)>;
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def : MSAPat<(v8i16 (load addr:$addr)), (LD_H addr:$addr)>;
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def : MSAPat<(v4i32 (load addr:$addr)), (LD_W addr:$addr)>;
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@ -91,6 +91,8 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
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addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
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addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
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setTargetDAGCombine(ISD::AND);
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setTargetDAGCombine(ISD::SRA);
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setTargetDAGCombine(ISD::XOR);
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}
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@ -161,6 +163,8 @@ addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
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setOperationAction(ISD::BITCAST, Ty, Legal);
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setOperationAction(ISD::LOAD, Ty, Legal);
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setOperationAction(ISD::STORE, Ty, Legal);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
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setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
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setOperationAction(ISD::ADD, Ty, Legal);
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@ -190,6 +194,7 @@ addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
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setOperationAction(ISD::LOAD, Ty, Legal);
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setOperationAction(ISD::STORE, Ty, Legal);
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setOperationAction(ISD::BITCAST, Ty, Legal);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);
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if (Ty != MVT::v8f16) {
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setOperationAction(ISD::FADD, Ty, Legal);
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@ -233,6 +238,7 @@ SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
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case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
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case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
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case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
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case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
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case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
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}
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@ -404,6 +410,56 @@ static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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// Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
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//
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// Performs the following transformations:
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// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
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// sign/zero-extension is completely overwritten by the new one performed by
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// the ISD::AND.
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// - Removes redundant zero extensions performed by an ISD::AND.
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static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const MipsSubtarget *Subtarget) {
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if (!Subtarget->hasMSA())
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return SDValue();
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SDValue Op0 = N->getOperand(0);
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SDValue Op1 = N->getOperand(1);
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unsigned Op0Opcode = Op0->getOpcode();
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// (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
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// where $d + 1 == 2^n and n == 32
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// or $d + 1 == 2^n and n <= 32 and ZExt
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// -> (MipsVExtractZExt $a, $b, $c)
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if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
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Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
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ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
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if (!Mask)
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return SDValue();
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int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
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if (Log2IfPositive <= 0)
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return SDValue(); // Mask+1 is not a power of 2
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SDValue Op0Op2 = Op0->getOperand(2);
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EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
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unsigned ExtendTySize = ExtendTy.getSizeInBits();
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unsigned Log2 = Log2IfPositive;
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if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
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Log2 == ExtendTySize) {
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SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
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DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT,
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Op0->getVTList(), Ops, Op0->getNumOperands());
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return Op0;
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}
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}
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return SDValue();
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}
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static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const MipsSubtarget *Subtarget) {
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@ -500,11 +556,53 @@ static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
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return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
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}
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// Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
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// constant splats into MipsISD::SHRA_DSP for DSPr2.
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//
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// Performs the following transformations:
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// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
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// sign/zero-extension is completely overwritten by the new one performed by
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// the ISD::SRA and ISD::SHL nodes.
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// - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
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// sequence.
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//
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// See performDSPShiftCombine for more information about the transformation
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// used for DSPr2.
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static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const MipsSubtarget *Subtarget) {
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EVT Ty = N->getValueType(0);
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if (Subtarget->hasMSA()) {
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SDValue Op0 = N->getOperand(0);
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SDValue Op1 = N->getOperand(1);
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// (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
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// where $d + sizeof($c) == 32
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// or $d + sizeof($c) <= 32 and SExt
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// -> (MipsVExtractSExt $a, $b, $c)
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if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
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SDValue Op0Op0 = Op0->getOperand(0);
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ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
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if (!ShAmount)
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return SDValue();
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EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
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unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
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if (TotalBits == 32 ||
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(Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
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TotalBits <= 32)) {
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SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
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Op0Op0->getOperand(2) };
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DAG.MorphNodeTo(Op0Op0.getNode(), MipsISD::VEXTRACT_SEXT_ELT,
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Op0Op0->getVTList(), Ops, Op0Op0->getNumOperands());
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return Op0Op0;
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}
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}
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}
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|
||||
if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2()))
|
||||
return SDValue();
|
||||
|
||||
@ -616,6 +714,9 @@ MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
|
||||
switch (N->getOpcode()) {
|
||||
case ISD::ADDE:
|
||||
return performADDECombine(N, DAG, DCI, Subtarget);
|
||||
case ISD::AND:
|
||||
Val = performANDCombine(N, DAG, DCI, Subtarget);
|
||||
break;
|
||||
case ISD::SUBE:
|
||||
return performSUBECombine(N, DAG, DCI, Subtarget);
|
||||
case ISD::MUL:
|
||||
@ -889,6 +990,33 @@ static SDValue lowerMSABranchIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
|
||||
return Result;
|
||||
}
|
||||
|
||||
// Lower an MSA copy intrinsic into the specified SelectionDAG node
|
||||
static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
|
||||
SDLoc DL(Op);
|
||||
SDValue Vec = Op->getOperand(1);
|
||||
SDValue Idx = Op->getOperand(2);
|
||||
EVT ResTy = Op->getValueType(0);
|
||||
EVT EltTy = Vec->getValueType(0).getVectorElementType();
|
||||
|
||||
SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
|
||||
DAG.getValueType(EltTy));
|
||||
|
||||
return Result;
|
||||
}
|
||||
|
||||
// Lower an MSA insert intrinsic into the specified SelectionDAG node
|
||||
static SDValue lowerMSAInsertIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
|
||||
SDLoc DL(Op);
|
||||
SDValue Op0 = Op->getOperand(1);
|
||||
SDValue Op1 = Op->getOperand(2);
|
||||
SDValue Op2 = Op->getOperand(3);
|
||||
EVT ResTy = Op->getValueType(0);
|
||||
|
||||
SDValue Result = DAG.getNode(Opc, DL, ResTy, Op0, Op2, Op1);
|
||||
|
||||
return Result;
|
||||
}
|
||||
|
||||
static SDValue lowerMSAUnaryIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
|
||||
SDLoc DL(Op);
|
||||
SDValue Value = Op->getOperand(1);
|
||||
@ -957,6 +1085,14 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
|
||||
return lowerMSABranchIntr(Op, DAG, MipsISD::VALL_ZERO);
|
||||
case Intrinsic::mips_bz_v:
|
||||
return lowerMSABranchIntr(Op, DAG, MipsISD::VANY_ZERO);
|
||||
case Intrinsic::mips_copy_s_b:
|
||||
case Intrinsic::mips_copy_s_h:
|
||||
case Intrinsic::mips_copy_s_w:
|
||||
return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
|
||||
case Intrinsic::mips_copy_u_b:
|
||||
case Intrinsic::mips_copy_u_h:
|
||||
case Intrinsic::mips_copy_u_w:
|
||||
return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
|
||||
case Intrinsic::mips_div_s_b:
|
||||
case Intrinsic::mips_div_s_h:
|
||||
case Intrinsic::mips_div_s_w:
|
||||
@ -992,6 +1128,10 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
|
||||
case Intrinsic::mips_fsub_w:
|
||||
case Intrinsic::mips_fsub_d:
|
||||
return lowerMSABinaryIntr(Op, DAG, ISD::FSUB);
|
||||
case Intrinsic::mips_insert_b:
|
||||
case Intrinsic::mips_insert_h:
|
||||
case Intrinsic::mips_insert_w:
|
||||
return lowerMSAInsertIntr(Op, DAG, ISD::INSERT_VECTOR_ELT);
|
||||
case Intrinsic::mips_ldi_b:
|
||||
case Intrinsic::mips_ldi_h:
|
||||
case Intrinsic::mips_ldi_w:
|
||||
@ -1165,6 +1305,24 @@ static bool isSplatVector(const BuildVectorSDNode *N) {
|
||||
return true;
|
||||
}
|
||||
|
||||
// Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
|
||||
//
|
||||
// The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
|
||||
// choose to sign-extend but we could have equally chosen zero-extend. The
|
||||
// DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
|
||||
// result into this node later (possibly changing it to a zero-extend in the
|
||||
// process).
|
||||
SDValue MipsSETargetLowering::
|
||||
lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
|
||||
SDLoc DL(Op);
|
||||
EVT ResTy = Op->getValueType(0);
|
||||
SDValue Op0 = Op->getOperand(0);
|
||||
SDValue Op1 = Op->getOperand(1);
|
||||
EVT EltTy = Op0->getValueType(0).getVectorElementType();
|
||||
return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
|
||||
DAG.getValueType(EltTy));
|
||||
}
|
||||
|
||||
// Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
|
||||
// backend.
|
||||
//
|
||||
|
||||
@ -73,6 +73,7 @@ namespace llvm {
|
||||
SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
|
||||
|
||||
MachineBasicBlock *emitBPOSGE32(MachineInstr *MI,
|
||||
|
||||
@ -118,3 +118,229 @@ define void @const_v2i64() nounwind {
|
||||
ret void
|
||||
; MIPS32: .size const_v2i64
|
||||
}
|
||||
|
||||
define i32 @extract_sext_v16i8() nounwind {
|
||||
; MIPS32: extract_sext_v16i8:
|
||||
|
||||
%1 = load <16 x i8>* @v16i8
|
||||
; MIPS32-DAG: ld.b [[R1:\$w[0-9]+]],
|
||||
|
||||
%2 = add <16 x i8> %1, %1
|
||||
; MIPS32-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
|
||||
|
||||
%3 = extractelement <16 x i8> %2, i32 1
|
||||
%4 = sext i8 %3 to i32
|
||||
; MIPS32-DAG: copy_s.b [[R3:\$[0-9]+]], [[R1]][1]
|
||||
; MIPS32-NOT: sll
|
||||
; MIPS32-NOT: sra
|
||||
|
||||
ret i32 %4
|
||||
; MIPS32: .size extract_sext_v16i8
|
||||
}
|
||||
|
||||
define i32 @extract_sext_v8i16() nounwind {
|
||||
; MIPS32: extract_sext_v8i16:
|
||||
|
||||
%1 = load <8 x i16>* @v8i16
|
||||
; MIPS32-DAG: ld.h [[R1:\$w[0-9]+]],
|
||||
|
||||
%2 = add <8 x i16> %1, %1
|
||||
; MIPS32-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
|
||||
|
||||
%3 = extractelement <8 x i16> %2, i32 1
|
||||
%4 = sext i16 %3 to i32
|
||||
; MIPS32-DAG: copy_s.h [[R3:\$[0-9]+]], [[R1]][1]
|
||||
; MIPS32-NOT: sll
|
||||
; MIPS32-NOT: sra
|
||||
|
||||
ret i32 %4
|
||||
; MIPS32: .size extract_sext_v8i16
|
||||
}
|
||||
|
||||
define i32 @extract_sext_v4i32() nounwind {
|
||||
; MIPS32: extract_sext_v4i32:
|
||||
|
||||
%1 = load <4 x i32>* @v4i32
|
||||
; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
|
||||
|
||||
%2 = add <4 x i32> %1, %1
|
||||
; MIPS32-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
|
||||
|
||||
%3 = extractelement <4 x i32> %2, i32 1
|
||||
; MIPS32-DAG: copy_s.w [[R3:\$[0-9]+]], [[R1]][1]
|
||||
|
||||
ret i32 %3
|
||||
; MIPS32: .size extract_sext_v4i32
|
||||
}
|
||||
|
||||
define i64 @extract_sext_v2i64() nounwind {
|
||||
; MIPS32: extract_sext_v2i64:
|
||||
|
||||
%1 = load <2 x i64>* @v2i64
|
||||
; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
|
||||
|
||||
%2 = add <2 x i64> %1, %1
|
||||
; MIPS32-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
|
||||
|
||||
%3 = extractelement <2 x i64> %2, i32 1
|
||||
; MIPS32-DAG: copy_s.w [[R3:\$[0-9]+]], [[R1]][2]
|
||||
; MIPS32-DAG: copy_s.w [[R4:\$[0-9]+]], [[R1]][3]
|
||||
; MIPS32-NOT: sll
|
||||
; MIPS32-NOT: sra
|
||||
|
||||
ret i64 %3
|
||||
; MIPS32: .size extract_sext_v2i64
|
||||
}
|
||||
|
||||
define i32 @extract_zext_v16i8() nounwind {
|
||||
; MIPS32: extract_zext_v16i8:
|
||||
|
||||
%1 = load <16 x i8>* @v16i8
|
||||
; MIPS32-DAG: ld.b [[R1:\$w[0-9]+]],
|
||||
|
||||
%2 = add <16 x i8> %1, %1
|
||||
; MIPS32-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
|
||||
|
||||
%3 = extractelement <16 x i8> %2, i32 1
|
||||
%4 = zext i8 %3 to i32
|
||||
; MIPS32-DAG: copy_u.b [[R3:\$[0-9]+]], [[R1]][1]
|
||||
; MIPS32-NOT: andi
|
||||
|
||||
ret i32 %4
|
||||
; MIPS32: .size extract_zext_v16i8
|
||||
}
|
||||
|
||||
define i32 @extract_zext_v8i16() nounwind {
|
||||
; MIPS32: extract_zext_v8i16:
|
||||
|
||||
%1 = load <8 x i16>* @v8i16
|
||||
; MIPS32-DAG: ld.h [[R1:\$w[0-9]+]],
|
||||
|
||||
%2 = add <8 x i16> %1, %1
|
||||
; MIPS32-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
|
||||
|
||||
%3 = extractelement <8 x i16> %2, i32 1
|
||||
%4 = zext i16 %3 to i32
|
||||
; MIPS32-DAG: copy_u.h [[R3:\$[0-9]+]], [[R1]][1]
|
||||
; MIPS32-NOT: andi
|
||||
|
||||
ret i32 %4
|
||||
; MIPS32: .size extract_zext_v8i16
|
||||
}
|
||||
|
||||
define i32 @extract_zext_v4i32() nounwind {
|
||||
; MIPS32: extract_zext_v4i32:
|
||||
|
||||
%1 = load <4 x i32>* @v4i32
|
||||
; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
|
||||
|
||||
%2 = add <4 x i32> %1, %1
|
||||
; MIPS32-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
|
||||
|
||||
%3 = extractelement <4 x i32> %2, i32 1
|
||||
; MIPS32-DAG: copy_{{[su]}}.w [[R3:\$[0-9]+]], [[R1]][1]
|
||||
|
||||
ret i32 %3
|
||||
; MIPS32: .size extract_zext_v4i32
|
||||
}
|
||||
|
||||
define i64 @extract_zext_v2i64() nounwind {
|
||||
; MIPS32: extract_zext_v2i64:
|
||||
|
||||
%1 = load <2 x i64>* @v2i64
|
||||
; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
|
||||
|
||||
%2 = add <2 x i64> %1, %1
|
||||
; MIPS32-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
|
||||
|
||||
%3 = extractelement <2 x i64> %2, i32 1
|
||||
; MIPS32-DAG: copy_{{[su]}}.w [[R3:\$[0-9]+]], [[R1]][2]
|
||||
; MIPS32-DAG: copy_{{[su]}}.w [[R4:\$[0-9]+]], [[R1]][3]
|
||||
; MIPS32-NOT: andi
|
||||
|
||||
ret i64 %3
|
||||
; MIPS32: .size extract_zext_v2i64
|
||||
}
|
||||
|
||||
define void @insert_v16i8(i32 %a) nounwind {
|
||||
; MIPS32: insert_v16i8:
|
||||
|
||||
%1 = load <16 x i8>* @v16i8
|
||||
; MIPS32-DAG: ld.b [[R1:\$w[0-9]+]],
|
||||
|
||||
%a2 = trunc i32 %a to i8
|
||||
%a3 = sext i8 %a2 to i32
|
||||
%a4 = trunc i32 %a3 to i8
|
||||
; MIPS32-NOT: andi
|
||||
; MIPS32-NOT: sra
|
||||
|
||||
%2 = insertelement <16 x i8> %1, i8 %a4, i32 1
|
||||
; MIPS32-DAG: insert.b [[R1]][1], $4
|
||||
|
||||
store <16 x i8> %2, <16 x i8>* @v16i8
|
||||
; MIPS32-DAG: st.b [[R1]]
|
||||
|
||||
ret void
|
||||
; MIPS32: .size insert_v16i8
|
||||
}
|
||||
|
||||
define void @insert_v8i16(i32 %a) nounwind {
|
||||
; MIPS32: insert_v8i16:
|
||||
|
||||
%1 = load <8 x i16>* @v8i16
|
||||
; MIPS32-DAG: ld.h [[R1:\$w[0-9]+]],
|
||||
|
||||
%a2 = trunc i32 %a to i16
|
||||
%a3 = sext i16 %a2 to i32
|
||||
%a4 = trunc i32 %a3 to i16
|
||||
; MIPS32-NOT: andi
|
||||
; MIPS32-NOT: sra
|
||||
|
||||
%2 = insertelement <8 x i16> %1, i16 %a4, i32 1
|
||||
; MIPS32-DAG: insert.h [[R1]][1], $4
|
||||
|
||||
store <8 x i16> %2, <8 x i16>* @v8i16
|
||||
; MIPS32-DAG: st.h [[R1]]
|
||||
|
||||
ret void
|
||||
; MIPS32: .size insert_v8i16
|
||||
}
|
||||
|
||||
define void @insert_v4i32(i32 %a) nounwind {
|
||||
; MIPS32: insert_v4i32:
|
||||
|
||||
%1 = load <4 x i32>* @v4i32
|
||||
; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
|
||||
|
||||
; MIPS32-NOT: andi
|
||||
; MIPS32-NOT: sra
|
||||
|
||||
%2 = insertelement <4 x i32> %1, i32 %a, i32 1
|
||||
; MIPS32-DAG: insert.w [[R1]][1], $4
|
||||
|
||||
store <4 x i32> %2, <4 x i32>* @v4i32
|
||||
; MIPS32-DAG: st.w [[R1]]
|
||||
|
||||
ret void
|
||||
; MIPS32: .size insert_v4i32
|
||||
}
|
||||
|
||||
define void @insert_v2i64(i64 %a) nounwind {
|
||||
; MIPS32: insert_v2i64:
|
||||
|
||||
%1 = load <2 x i64>* @v2i64
|
||||
; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
|
||||
|
||||
; MIPS32-NOT: andi
|
||||
; MIPS32-NOT: sra
|
||||
|
||||
%2 = insertelement <2 x i64> %1, i64 %a, i32 1
|
||||
; MIPS32-DAG: insert.w [[R1]][2], $4
|
||||
; MIPS32-DAG: insert.w [[R1]][3], $5
|
||||
|
||||
store <2 x i64> %2, <2 x i64>* @v2i64
|
||||
; MIPS32-DAG: st.w [[R1]]
|
||||
|
||||
ret void
|
||||
; MIPS32: .size insert_v2i64
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user