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Remove all traces of the "Opcode Mask" field in the MachineInstr class

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4359 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2002-10-28 21:17:20 +00:00
parent b98a53f201
commit 9a8e4121aa
6 changed files with 3 additions and 30 deletions
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9
include/llvm/CodeGen/MachineInstr.h
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@ -17,7 +17,6 @@ class Value;
class Function;
typedef int MachineOpCode;
typedef int OpCodeMask;
//---------------------------------------------------------------------------
// class MachineOperand
@ -185,13 +184,6 @@ private:
// MachineOpCode must be an enum, defined separately for each target.
// E.g., It is defined in SparcInstructionSelection.h for the SPARC.
//
// opCodeMask is used to record variants of an instruction.
// E.g., each branch instruction on SPARC has 2 flags (i.e., 4 variants):
// ANNUL: if 1: Annul delay slot instruction.
// PREDICT-NOT-TAKEN: if 1: predict branch not taken.
// Instead of creating 4 different opcodes for BNZ, we create a single
// opcode and set bits in opCodeMask for each of these flags.
//
// There are 2 kinds of operands:
//
// (1) Explicit operands of the machine instruction in vector operands[]
@ -204,7 +196,6 @@ private:
class MachineInstr : public Annotable, // MachineInstrs are annotable
public NonCopyable { // Disable copy operations
MachineOpCode opCode; // the opcode
OpCodeMask opCodeMask; // extra bits for variants of an opcode
std::vector<MachineOperand> operands; // the operands
struct ImplicitRef {

1
include/llvm/Target/MachineInstrInfo.h
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@ -25,7 +25,6 @@ class MachineCodeForInstruction;
//---------------------------------------------------------------------------
typedef int MachineOpCode;
typedef int OpCodeMask;
typedef unsigned InstrSchedClass;
const MachineOpCode INVALID_MACHINE_OPCODE = -1;

1
include/llvm/Target/TargetInstrInfo.h
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@ -25,7 +25,6 @@ class MachineCodeForInstruction;
//---------------------------------------------------------------------------
typedef int MachineOpCode;
typedef int OpCodeMask;
typedef unsigned InstrSchedClass;
const MachineOpCode INVALID_MACHINE_OPCODE = -1;

7
lib/CodeGen/MachineInstr.cpp
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@ -10,18 +10,18 @@ using std::cerr;
// Constructor for instructions with fixed #operands (nearly all)
MachineInstr::MachineInstr(MachineOpCode _opCode)
: opCode(_opCode), opCodeMask(0),
: opCode(_opCode),
operands(TargetInstrDescriptors[_opCode].numOperands, MachineOperand()) {
assert(TargetInstrDescriptors[_opCode].numOperands >= 0);
}
// Constructor for instructions with variable #operands
MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned numOperands)
: opCode(OpCode), opCodeMask(0), operands(numOperands, MachineOperand()) {
: opCode(OpCode), operands(numOperands, MachineOperand()) {
}
MachineInstr::MachineInstr(MachineOpCode Opcode, unsigned numOperands,
bool XX, bool YY) : opCode(Opcode), opCodeMask(0) {
bool XX, bool YY) : opCode(Opcode) {
operands.reserve(numOperands);
}
@ -41,7 +41,6 @@ bool MachineInstr::OperandsComplete() const {
//
void MachineInstr::replace(MachineOpCode Opcode, unsigned numOperands) {
opCode = Opcode;
opCodeMask = 0;
operands.clear();
operands.resize(numOperands, MachineOperand());
}

8
lib/Target/SparcV9/SparcV9Instr.def
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@ -52,14 +52,12 @@ I(SETX, "setx", 3, 2, 0, true, 0, 2, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_
I(SETHI, "sethi", 2, 1, B22, false, 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG | M_ARITH_FLAG)
// Add or add with carry.
// Immed bit specifies if second operand is immediate(1) or register(0)
I(ADD , "add", 3, 2, B12, true , 0, 1, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG)
I(ADDcc , "addcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_INT_FLAG | M_ARITH_FLAG | M_CC_FLAG )
I(ADDC , "addc", 3, 2, B12, true , 0, 1, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG)
I(ADDCcc, "addccc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_INT_FLAG | M_ARITH_FLAG | M_CC_FLAG )
// Subtract or subtract with carry.
// Immed bit specifies if second operand is immediate(1) or register(0)
I(SUB , "sub", 3, 2, B12, true , 0, 1, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG)
I(SUBcc , "subcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_INT_FLAG | M_ARITH_FLAG | M_CC_FLAG )
I(SUBC , "subc", 3, 2, B12, true , 0, 1, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG)
@ -157,8 +155,6 @@ I(FITOD, "fitod", 2, 1, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLA
I(FITOQ, "fitoq", 2, 1, 0, false, 0, 0, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG)
// Branch on integer comparison with zero.
// Annul bit specifies if intruction in delay slot is annulled(1) or not(0).
// PredictTaken bit hints if branch should be predicted taken(1) or not(0).
// Latency excludes the delay slot since it can be issued in same cycle.
I(BRZ , "brz", 2, -1, B15, true , 1, 1, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG)
I(BRLEZ, "brlez", 2, -1, B15, true , 1, 1, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG)
@ -170,8 +166,6 @@ I(BRGEZ, "brgez", 2, -1, B15, true , 1, 1, SPARC_CTI, M_INT_FLAG | M_BRANCH_FL
// Branch on integer condition code.
// The first argument specifies the ICC register: %icc or %xcc
// Latency includes the delay slot.
// Annul bit specifies if intruction in delay slot is annulled(1) or not(0).
// PredictTaken bit hints if branch should be predicted taken(1) or not(0).
I(BA , "ba", 1, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
I(BN , "bn", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
I(BNE , "bne", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
@ -190,8 +184,6 @@ I(BVC , "bvc", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
I(BVS , "bvs", 2, -1, B21, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)
// Branch on floating point condition code.
// Annul bit specifies if intruction in delay slot is annulled(1) or not(0).
// PredictTaken bit hints if branch should be predicted taken(1) or not(0).
// The first argument is the FCCn register (0 <= n <= 3).
// Latency includes the delay slot.
I(FBA , "fba", 2, -1, B18, true , 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG)

7
lib/Target/SparcV9/SparcV9Internals.h
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@ -22,13 +22,6 @@ class UltraSparc;
class PhyRegAlloc;
class Pass;
// OpCodeMask definitions for the Sparc V9
//
const OpCodeMask Immed = 0x00002000; // immed or reg operand?
const OpCodeMask Annul = 0x20000000; // annul delay instr?
const OpCodeMask PredictTaken = 0x00080000; // predict branch taken?
enum SparcInstrSchedClass {
SPARC_NONE, /* Instructions with no scheduling restrictions */
SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */