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[mips] Print instructions "beq", "bne" and "or" using assembler pseudo
instructions "beqz", "bnez" and "move", when possible. beq $2, $zero, $L1 => beqz $2, $L1 bne $2, $zero, $L1 => bnez $2, $L1 or $2, $3, $zero => move $2, $3 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187229 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
b390abce16
commit
9b06dd6ca2
@ -26,6 +26,12 @@ using namespace llvm;
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#define PRINT_ALIAS_INSTR
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#include "MipsGenAsmWriter.inc"
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template<unsigned R>
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static bool isReg(const MCInst &MI, unsigned OpNo) {
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assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
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return MI.getOperand(OpNo).getReg() == R;
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}
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const char* Mips::MipsFCCToString(Mips::CondCode CC) {
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switch (CC) {
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case FCOND_F:
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@ -80,7 +86,7 @@ void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
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}
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// Try to print any aliases first.
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if (!printAliasInstr(MI, O))
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if (!printAliasInstr(MI, O) && !printAlias(*MI, O))
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printInstruction(MI, O);
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printAnnotation(O, Annot);
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@ -209,3 +215,47 @@ printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) {
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const MCOperand& MO = MI->getOperand(opNum);
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O << MipsFCCToString((Mips::CondCode)MO.getImm());
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}
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bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
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unsigned OpNo, raw_ostream &OS) {
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OS << "\t" << Str << "\t";
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printOperand(&MI, OpNo, OS);
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return true;
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}
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bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
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unsigned OpNo0, unsigned OpNo1,
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raw_ostream &OS) {
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printAlias(Str, MI, OpNo0, OS);
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OS << ", ";
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printOperand(&MI, OpNo1, OS);
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return true;
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}
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bool MipsInstPrinter::printAlias(const MCInst &MI, raw_ostream &OS) {
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switch (MI.getOpcode()) {
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case Mips::BEQ:
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if (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS))
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return true;
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break;
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case Mips::BEQ64:
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if (isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS))
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return true;
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break;
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case Mips::BNE:
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if (isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS))
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return true;
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break;
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case Mips::BNE64:
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if (isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS))
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return true;
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break;
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case Mips::OR:
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if (isReg<Mips::ZERO>(MI, 2) && printAlias("move", MI, 0, 1, OS))
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return true;
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break;
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default: return false;
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}
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return false;
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}
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@ -97,6 +97,12 @@ private:
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void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O);
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void printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O);
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void printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O);
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bool printAlias(const char *Str, const MCInst &MI, unsigned OpNo,
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raw_ostream &OS);
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bool printAlias(const char *Str, const MCInst &MI, unsigned OpNo0,
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unsigned OpNo1, raw_ostream &OS);
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bool printAlias(const MCInst &MI, raw_ostream &OS);
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};
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} // end namespace llvm
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@ -14,7 +14,7 @@ entry:
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; CHECK-EL: ll $[[R1:[0-9]+]], 0($[[R0]])
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; CHECK-EL: addu $[[R2:[0-9]+]], $[[R1]], $4
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; CHECK-EL: sc $[[R2]], 0($[[R0]])
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; CHECK-EL: beq $[[R2]], $zero, $[[BB0]]
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; CHECK-EL: beqz $[[R2]], $[[BB0]]
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; CHECK-EB-LABEL: AtomicLoadAdd32:
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; CHECK-EB: lw $[[R0:[0-9]+]], %got(x)
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@ -22,7 +22,7 @@ entry:
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; CHECK-EB: ll $[[R1:[0-9]+]], 0($[[R0]])
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; CHECK-EB: addu $[[R2:[0-9]+]], $[[R1]], $4
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; CHECK-EB: sc $[[R2]], 0($[[R0]])
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; CHECK-EB: beq $[[R2]], $zero, $[[BB0]]
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; CHECK-EB: beqz $[[R2]], $[[BB0]]
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}
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define i32 @AtomicLoadNand32(i32 %incr) nounwind {
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@ -37,7 +37,7 @@ entry:
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; CHECK-EL: and $[[R3:[0-9]+]], $[[R1]], $4
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; CHECK-EL: nor $[[R2:[0-9]+]], $zero, $[[R3]]
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; CHECK-EL: sc $[[R2]], 0($[[R0]])
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; CHECK-EL: beq $[[R2]], $zero, $[[BB0]]
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; CHECK-EL: beqz $[[R2]], $[[BB0]]
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; CHECK-EB-LABEL: AtomicLoadNand32:
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; CHECK-EB: lw $[[R0:[0-9]+]], %got(x)
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@ -46,7 +46,7 @@ entry:
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; CHECK-EB: and $[[R3:[0-9]+]], $[[R1]], $4
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; CHECK-EB: nor $[[R2:[0-9]+]], $zero, $[[R3]]
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; CHECK-EB: sc $[[R2]], 0($[[R0]])
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; CHECK-EB: beq $[[R2]], $zero, $[[BB0]]
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; CHECK-EB: beqz $[[R2]], $[[BB0]]
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}
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define i32 @AtomicSwap32(i32 %newval) nounwind {
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@ -62,14 +62,14 @@ entry:
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; CHECK-EL: $[[BB0:[A-Z_0-9]+]]:
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; CHECK-EL: ll ${{[0-9]+}}, 0($[[R0]])
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; CHECK-EL: sc $[[R2:[0-9]+]], 0($[[R0]])
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; CHECK-EL: beq $[[R2]], $zero, $[[BB0]]
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; CHECK-EL: beqz $[[R2]], $[[BB0]]
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; CHECK-EB-LABEL: AtomicSwap32:
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; CHECK-EB: lw $[[R0:[0-9]+]], %got(x)
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; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:
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; CHECK-EB: ll ${{[0-9]+}}, 0($[[R0]])
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; CHECK-EB: sc $[[R2:[0-9]+]], 0($[[R0]])
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; CHECK-EB: beq $[[R2]], $zero, $[[BB0]]
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; CHECK-EB: beqz $[[R2]], $[[BB0]]
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}
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define i32 @AtomicCmpSwap32(i32 %oldval, i32 %newval) nounwind {
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@ -86,7 +86,7 @@ entry:
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; CHECK-EL: ll $2, 0($[[R0]])
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; CHECK-EL: bne $2, $4, $[[BB1:[A-Z_0-9]+]]
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; CHECK-EL: sc $[[R2:[0-9]+]], 0($[[R0]])
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; CHECK-EL: beq $[[R2]], $zero, $[[BB0]]
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; CHECK-EL: beqz $[[R2]], $[[BB0]]
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; CHECK-EL: $[[BB1]]:
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; CHECK-EB-LABEL: AtomicCmpSwap32:
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@ -95,7 +95,7 @@ entry:
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; CHECK-EB: ll $2, 0($[[R0]])
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; CHECK-EB: bne $2, $4, $[[BB1:[A-Z_0-9]+]]
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; CHECK-EB: sc $[[R2:[0-9]+]], 0($[[R0]])
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; CHECK-EB: beq $[[R2]], $zero, $[[BB0]]
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; CHECK-EB: beqz $[[R2]], $[[BB0]]
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; CHECK-EB: $[[BB1]]:
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}
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@ -126,7 +126,7 @@ entry:
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; CHECK-EL: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
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; CHECK-EL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
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; CHECK-EL: sc $[[R14]], 0($[[R2]])
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; CHECK-EL: beq $[[R14]], $zero, $[[BB0]]
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; CHECK-EL: beqz $[[R14]], $[[BB0]]
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; CHECK-EL: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
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; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
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@ -152,7 +152,7 @@ entry:
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; CHECK-EB: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
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; CHECK-EB: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
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; CHECK-EB: sc $[[R14]], 0($[[R2]])
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; CHECK-EB: beq $[[R14]], $zero, $[[BB0]]
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; CHECK-EB: beqz $[[R14]], $[[BB0]]
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; CHECK-EB: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
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; CHECK-EB: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
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@ -183,7 +183,7 @@ entry:
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; CHECK-EL: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
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; CHECK-EL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
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; CHECK-EL: sc $[[R14]], 0($[[R2]])
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; CHECK-EL: beq $[[R14]], $zero, $[[BB0]]
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; CHECK-EL: beqz $[[R14]], $[[BB0]]
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; CHECK-EL: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
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; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
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@ -209,7 +209,7 @@ entry:
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; CHECK-EB: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
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; CHECK-EB: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
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; CHECK-EB: sc $[[R14]], 0($[[R2]])
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; CHECK-EB: beq $[[R14]], $zero, $[[BB0]]
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; CHECK-EB: beqz $[[R14]], $[[BB0]]
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; CHECK-EB: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
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; CHECK-EB: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
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@ -241,7 +241,7 @@ entry:
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; CHECK-EL: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
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; CHECK-EL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
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; CHECK-EL: sc $[[R14]], 0($[[R2]])
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; CHECK-EL: beq $[[R14]], $zero, $[[BB0]]
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; CHECK-EL: beqz $[[R14]], $[[BB0]]
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; CHECK-EL: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
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; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
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@ -268,7 +268,7 @@ entry:
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; CHECK-EB: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
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; CHECK-EB: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
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; CHECK-EB: sc $[[R14]], 0($[[R2]])
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; CHECK-EB: beq $[[R14]], $zero, $[[BB0]]
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; CHECK-EB: beqz $[[R14]], $[[BB0]]
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; CHECK-EB: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
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; CHECK-EB: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
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@ -298,7 +298,7 @@ entry:
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; CHECK-EL: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
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; CHECK-EL: or $[[R14:[0-9]+]], $[[R13]], $[[R18]]
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; CHECK-EL: sc $[[R14]], 0($[[R2]])
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; CHECK-EL: beq $[[R14]], $zero, $[[BB0]]
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; CHECK-EL: beqz $[[R14]], $[[BB0]]
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; CHECK-EL: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
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; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
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@ -323,7 +323,7 @@ entry:
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; CHECK-EB: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
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; CHECK-EB: or $[[R14:[0-9]+]], $[[R13]], $[[R18]]
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; CHECK-EB: sc $[[R14]], 0($[[R2]])
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; CHECK-EB: beq $[[R14]], $zero, $[[BB0]]
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; CHECK-EB: beqz $[[R14]], $[[BB0]]
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; CHECK-EB: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
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; CHECK-EB: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
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@ -358,7 +358,7 @@ entry:
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; CHECK-EL: and $[[R14:[0-9]+]], $[[R12]], $[[R7]]
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; CHECK-EL: or $[[R15:[0-9]+]], $[[R14]], $[[R11]]
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; CHECK-EL: sc $[[R15]], 0($[[R2]])
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; CHECK-EL: beq $[[R15]], $zero, $[[BB0]]
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; CHECK-EL: beqz $[[R15]], $[[BB0]]
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; CHECK-EL: $[[BB1]]:
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; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R13]], $[[R4]]
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@ -388,7 +388,7 @@ entry:
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; CHECK-EB: and $[[R15:[0-9]+]], $[[R13]], $[[R8]]
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; CHECK-EB: or $[[R16:[0-9]+]], $[[R15]], $[[R12]]
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; CHECK-EB: sc $[[R16]], 0($[[R2]])
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; CHECK-EB: beq $[[R16]], $zero, $[[BB0]]
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; CHECK-EB: beqz $[[R16]], $[[BB0]]
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; CHECK-EB: $[[BB1]]:
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; CHECK-EB: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]]
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@ -133,7 +133,7 @@ declare void @foo11()
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; SUCCBB-LABEL: succbbs_loop1:
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; SUCCBB: blez $5, $BB
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; SUCCBB-NEXT: addiu
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; SUCCBB: bne ${{[0-9]+}}, $zero, $BB
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; SUCCBB: bnez ${{[0-9]+}}, $BB
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; SUCCBB-NEXT: addiu
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define i32 @succbbs_loop1(i32* nocapture %a, i32 %n) {
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@ -159,7 +159,7 @@ for.end: ; preds = %for.body, %entry
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; Check that the first branch has its slot filled.
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;
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; SUCCBB-LABEL: succbbs_br1:
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; SUCCBB: beq ${{[0-9]+}}, $zero, $BB
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; SUCCBB: beqz ${{[0-9]+}}, $BB
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; SUCCBB-NEXT: lw $25, %call16(foo100)
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define void @succbbs_br1(i32 %a) {
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@ -24,7 +24,7 @@ entry:
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; CHECK-LABEL: slti_beq0:
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; CHECK: slti $[[R0:[0-9]+]], $4, -32768
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; CHECK: beq $[[R0]], $zero
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; CHECK: beqz $[[R0]]
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define void @slti_beq0(i32 %a) {
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entry:
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@ -57,7 +57,7 @@ if.end:
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; CHECK-LABEL: slti_beq2:
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; CHECK: slti $[[R0:[0-9]+]], $4, 32767
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; CHECK: beq $[[R0]], $zero
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; CHECK: beqz $[[R0]]
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define void @slti_beq2(i32 %a) {
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entry:
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@ -90,7 +90,7 @@ if.end:
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; CHECK-LABEL: sltiu_beq0:
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; CHECK: sltiu $[[R0:[0-9]+]], $4, 32767
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; CHECK: beq $[[R0]], $zero
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; CHECK: beqz $[[R0]]
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define void @sltiu_beq0(i32 %a) {
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entry:
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@ -123,7 +123,7 @@ if.end:
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; CHECK-LABEL: sltiu_beq2:
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; CHECK: sltiu $[[R0:[0-9]+]], $4, -32768
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; CHECK: beq $[[R0]], $zero
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; CHECK: beqz $[[R0]]
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define void @sltiu_beq2(i32 %a) {
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entry:
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@ -260,6 +260,12 @@
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# CHECK: mov.s $f6, $f7
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0x86 0x39 0x00 0x46
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# CHECK: move $7, $8
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0x21,0x38,0x00,0x01
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# CHECK: move $3, $2
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0x25,0x18,0x40,0x00
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# CHECK: msub $6, $7
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0x04 0x00 0xc7 0x70
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@ -13,7 +13,6 @@
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# CHECK: ins $19, $9, 6, 7 # encoding: [0x84,0x61,0x33,0x7d]
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# CHECK: nor $9, $6, $7 # encoding: [0x27,0x48,0xc7,0x00]
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# CHECK: or $3, $3, $5 # encoding: [0x25,0x18,0x65,0x00]
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# CHECK: or $3, $2, $zero # encoding: [0x25,0x18,0x40,0x00]
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# CHECK: ori $4, $5, 17767 # encoding: [0x67,0x45,0xa4,0x34]
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# CHECK: ori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x34]
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# CHECK: ori $11, $11, 128 # encoding: [0x80,0x00,0x6b,0x35]
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@ -45,7 +44,6 @@
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ins $19, $9, 6,7
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nor $9, $6, $7
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or $3, $3, $5
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or $3, $2, $zero
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or $4, $5, 17767
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ori $9, $6, 17767
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ori $11, 128
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@ -1,6 +1,6 @@
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# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | \
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# RUN: FileCheck -check-prefix=CHECK32 %s
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# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips64r2 | \
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# RUN: llvm-mc %s -triple=mips64el-unknown-linux -show-encoding -mcpu=mips64r2 | \
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# RUN: FileCheck -check-prefix=CHECK64 %s
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# Check that the assembler can handle the documented syntax
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@ -28,9 +28,9 @@
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# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
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# CHECK32: bal 1332 # encoding: [0x4d,0x01,0x11,0x04]
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# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK32: bne $11, $zero, 1332 # encoding: [0x4d,0x01,0x60,0x15]
|
||||
# CHECK32: bnez $11, 1332 # encoding: [0x4d,0x01,0x60,0x15]
|
||||
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK32: beq $11, $zero, 1332 # encoding: [0x4d,0x01,0x60,0x11]
|
||||
# CHECK32: beqz $11, 1332 # encoding: [0x4d,0x01,0x60,0x11]
|
||||
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
|
||||
# CHECK64: b 1332 # encoding: [0x4d,0x01,0x00,0x10]
|
||||
@ -53,9 +53,9 @@
|
||||
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK64: bal 1332 # encoding: [0x4d,0x01,0x11,0x04]
|
||||
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK64: bne $11, $zero, 1332 # encoding: [0x4d,0x01,0x60,0x15]
|
||||
# CHECK64: bnez $11, 1332 # encoding: [0x4d,0x01,0x60,0x15]
|
||||
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK64: beq $11, $zero, 1332 # encoding: [0x4d,0x01,0x60,0x11]
|
||||
# CHECK64: beqz $11, 1332 # encoding: [0x4d,0x01,0x60,0x11]
|
||||
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
|
||||
.set noreorder
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user