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[PowerPC] Preparatory refactoring for making prologue and epilogue
safe on PPC32 SVR4 ABI [Patch and following text by Mark Minich; committing on his behalf.] There are FIXME's in PowerPC/PPCFrameLowering.cpp, method PPCFrameLowering::emitPrologue() related to "negative offsets of R1" on PPC32 SVR4. They're true, but the real issue is that on PPC32 SVR4 (and any ABI without a Red Zone), no spills may be made until after the stackframe is claimed, which also includes the LR spill which is at a positive offset. The same problem exists in emitEpilogue(), though there's no FIXME for it. I intend to fix this issue, making LLVM-compiled code finally safe for use on SVR4/EABI/e500 32-bit platforms (including in particular, OS-free embedded systems & kernel code, where interrupts may share the same stack as user code). In preparation for making these changes, to make the diffs for the functional changes less cluttered, I am providing the non-functional refactorings in two stages: Stage 1 does some minor fluffy refactorings to pull multiple method calls up into a single bool, creating named bools for repeated uses of obscure logic, moving some code up earlier because either stage 2 or my final version will require it earlier, and rewording/adding some comments. My stage 1 changes can be characterized as primarily fluffy cleanup, the purpose of which may be unclear until the stage 2 or final changes are made. My stage 2 refactorings combine the separate PPC32 & PPC64 logic, which is currently performed by largely duplicate code, into a single flow, with the differences handled by a group of constants initialized early in the methods. This submission is for my stage 1 changes. There should be no functional changes whatsoever; this is a pure refactoring. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188573 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Schmidt
parent
b0f7929885
commit
9bb6c81683
@ -204,10 +204,9 @@ unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF,
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unsigned FrameSize =
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UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize();
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// Get the alignments provided by the target, and the maximum alignment
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// (if any) of the fixed frame objects.
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unsigned TargetAlign = getStackAlignment();
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unsigned MaxAlign = MFI->getMaxAlignment();
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// Get stack alignments. The frame must be aligned to the greatest of these:
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unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI
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unsigned MaxAlign = MFI->getMaxAlignment(); // algmt required by data in frame
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unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1;
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const PPCRegisterInfo *RegInfo =
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@ -346,12 +345,20 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
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bool needsFrameMoves = MMI.hasDebugInfo() ||
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MF.getFunction()->needsUnwindTableEntry();
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// Get processor type.
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bool isPPC64 = Subtarget.isPPC64();
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// Get the ABI.
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bool isDarwinABI = Subtarget.isDarwinABI();
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bool isSVR4ABI = Subtarget.isSVR4ABI();
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assert((isDarwinABI || isSVR4ABI) &&
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"Currently only Darwin and SVR4 ABIs are supported for PowerPC.");
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// Prepare for frame info.
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MCSymbol *FrameLabel = 0;
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// Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
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// process it.
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if (!Subtarget.isSVR4ABI())
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if (!isSVR4ABI)
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for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
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if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
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HandleVRSaveUpdate(MBBI, TII);
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@ -371,10 +378,6 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
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if (MFI->isFrameAddressTaken())
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replaceFPWithRealFP(MF);
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// Get processor type.
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bool isPPC64 = Subtarget.isPPC64();
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// Get operating system
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bool isDarwinABI = Subtarget.isDarwinABI();
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// Check if the link register (LR) must be saved.
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PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
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bool MustSaveLR = FI->mustSaveLR();
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@ -383,11 +386,18 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
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bool HasFP = hasFP(MF);
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bool HasBP = RegInfo->hasBasePointer(MF);
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// Regarding this assert: Even though LR is saved in the caller's frame (i.e.,
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// LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no
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// Red Zone, an asynchronous event (a form of "callee") could claim a frame &
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// overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR.
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assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&
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"FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
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int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
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int FPOffset = 0;
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if (HasFP) {
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if (Subtarget.isSVR4ABI()) {
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if (isSVR4ABI) {
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MachineFrameInfo *FFI = MF.getFrameInfo();
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int FPIndex = FI->getFramePointerSaveIndex();
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assert(FPIndex && "No Frame Pointer Save Slot!");
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@ -399,7 +409,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
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int BPOffset = 0;
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if (HasBP) {
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if (Subtarget.isSVR4ABI()) {
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if (isSVR4ABI) {
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MachineFrameInfo *FFI = MF.getFrameInfo();
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int BPIndex = FI->getBasePointerSaveIndex();
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assert(BPIndex && "No Base Pointer Save Slot!");
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@ -410,6 +420,16 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
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}
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}
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// Get stack alignments.
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unsigned MaxAlign = MFI->getMaxAlignment();
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if (HasBP && MaxAlign > 1)
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assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
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"Invalid alignment!");
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// Frames of 32KB & larger require special handling because they cannot be
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// indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
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bool isLargeFrame = !isInt<16>(NegFrameSize);
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if (isPPC64) {
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if (MustSaveLR)
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BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0);
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@ -444,21 +464,19 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
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.addReg(PPC::X12, getKillRegState(true))
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.addImm(8)
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.addReg(PPC::X1);
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} else {
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} else { // PPC32...
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if (MustSaveLR)
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BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0);
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if (HasFP)
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// FIXME: On PPC32 SVR4, FPOffset is negative and access to negative
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// offsets of R1 is not allowed.
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// FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
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.addReg(PPC::R31)
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.addImm(FPOffset)
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.addReg(PPC::R1);
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if (HasBP)
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// FIXME: On PPC32 SVR4, FPOffset is negative and access to negative
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// offsets of R1 is not allowed.
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// FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
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.addReg(PPC::R30)
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.addImm(BPOffset)
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@ -468,23 +486,19 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
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"Prologue CR saving supported only in 64-bit mode");
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if (MustSaveLR)
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// FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
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.addReg(PPC::R0)
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.addImm(LROffset)
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.addReg(PPC::R1);
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}
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// Skip if a leaf routine.
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// Skip the rest if this is a leaf function & all spills fit in the Red Zone.
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if (!FrameSize) return;
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// Get stack alignments.
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unsigned MaxAlign = MFI->getMaxAlignment();
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// Adjust stack pointer: r1 += NegFrameSize.
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// If there is a preferred stack alignment, align R1 now
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if (!isPPC64) {
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// PPC32.
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if (!isPPC64) { // PPC32...
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if (HasBP) {
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// Save a copy of r1 as the base pointer.
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BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R30)
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@ -493,15 +507,12 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
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}
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if (HasBP && MaxAlign > 1) {
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assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
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"Invalid alignment!");
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BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0)
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.addReg(PPC::R1)
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.addImm(0)
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.addImm(32 - Log2_32(MaxAlign))
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.addImm(31);
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if (isInt<16>(NegFrameSize)) {
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if (!isLargeFrame) {
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BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC), PPC::R0)
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.addReg(PPC::R0, RegState::Kill)
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.addImm(NegFrameSize);
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@ -519,11 +530,13 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
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.addReg(PPC::R1, RegState::Kill)
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.addReg(PPC::R1)
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.addReg(PPC::R0);
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} else if (isInt<16>(NegFrameSize)) {
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} else if (!isLargeFrame) {
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1)
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.addReg(PPC::R1)
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.addImm(NegFrameSize)
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.addReg(PPC::R1);
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} else {
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BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
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.addImm(NegFrameSize >> 16);
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@ -535,7 +548,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
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.addReg(PPC::R1)
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.addReg(PPC::R0);
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}
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} else { // PPC64.
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} else { // PPC64...
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if (HasBP) {
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// Save a copy of r1 as the base pointer.
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BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X30)
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@ -544,14 +557,11 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
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}
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if (HasBP && MaxAlign > 1) {
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assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
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"Invalid alignment!");
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BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0)
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.addReg(PPC::X1)
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.addImm(0)
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.addImm(64 - Log2_32(MaxAlign));
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if (isInt<16>(NegFrameSize)) {
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if (!isLargeFrame) {
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BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0)
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.addReg(PPC::X0, RegState::Kill)
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.addImm(NegFrameSize);
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@ -569,11 +579,13 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
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.addReg(PPC::X1, RegState::Kill)
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.addReg(PPC::X1)
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.addReg(PPC::X0);
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} else if (isInt<16>(NegFrameSize)) {
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} else if (!isLargeFrame) {
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1)
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.addReg(PPC::X1)
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.addImm(NegFrameSize)
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.addReg(PPC::X1);
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} else {
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BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
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.addImm(NegFrameSize >> 16);
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@ -625,11 +637,11 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
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// If there is a frame pointer, copy R1 into R31
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if (HasFP) {
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if (!isPPC64) {
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if (!isPPC64) { // PPC32...
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BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31)
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.addReg(PPC::R1)
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.addReg(PPC::R1);
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} else {
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} else { // PPC64...
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BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31)
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.addReg(PPC::X1)
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.addReg(PPC::X1);
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@ -641,8 +653,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
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// Mark effective beginning of when frame pointer is ready.
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BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel);
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unsigned Reg = HasFP ? (isPPC64 ? PPC::X31 : PPC::R31)
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: (isPPC64 ? PPC::X1 : PPC::R1);
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unsigned Reg = isPPC64 ? PPC::X31 : PPC::R31;
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Reg = MRI->getDwarfRegNum(Reg, true);
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MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(ReadyLabel, Reg));
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}
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@ -664,19 +675,16 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
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// For SVR4, don't emit a move for the CR spill slot if we haven't
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// spilled CRs.
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if (Subtarget.isSVR4ABI()
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&& (PPC::CR2 <= Reg && Reg <= PPC::CR4)
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&& MustSaveCRs.empty())
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continue;
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if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
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&& MustSaveCRs.empty())
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continue;
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// For 64-bit SVR4 when we have spilled CRs, the spill location
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// is SP+8, not a frame-relative slot.
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if (Subtarget.isSVR4ABI()
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&& Subtarget.isPPC64()
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&& (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
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if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
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MMI.addFrameInst(MCCFIInstruction::createOffset(
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Label, MRI->getDwarfRegNum(PPC::CR2, true), 8));
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continue;
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continue;
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}
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int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
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@ -707,7 +715,7 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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RetOpcode == PPC::TCRETURNai8) &&
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"Can only insert epilog into returning blocks");
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// Get alignment info so we know how to restore r1
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// Get alignment info so we know how to restore the SP.
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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// Get the number of bytes allocated from the FrameInfo.
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@ -715,8 +723,10 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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// Get processor type.
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bool isPPC64 = Subtarget.isPPC64();
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// Get operating system
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// Get the ABI.
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bool isDarwinABI = Subtarget.isDarwinABI();
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bool isSVR4ABI = Subtarget.isSVR4ABI();
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// Check if the link register (LR) has been saved.
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PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
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bool MustSaveLR = FI->mustSaveLR();
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@ -729,7 +739,7 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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int FPOffset = 0;
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if (HasFP) {
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if (Subtarget.isSVR4ABI()) {
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if (isSVR4ABI) {
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MachineFrameInfo *FFI = MF.getFrameInfo();
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int FPIndex = FI->getFramePointerSaveIndex();
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assert(FPIndex && "No Frame Pointer Save Slot!");
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@ -741,7 +751,7 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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int BPOffset = 0;
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if (HasBP) {
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if (Subtarget.isSVR4ABI()) {
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if (isSVR4ABI) {
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MachineFrameInfo *FFI = MF.getFrameInfo();
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int BPIndex = FI->getBasePointerSaveIndex();
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assert(BPIndex && "No Base Pointer Save Slot!");
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@ -773,30 +783,35 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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FrameSize += StackAdj;
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}
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// Frames of 32KB & larger require special handling because they cannot be
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// indexed into with a simple LD/LWZ immediate offset operand.
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bool isLargeFrame = !isInt<16>(FrameSize);
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if (FrameSize) {
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// The loaded (or persistent) stack pointer value is offset by the 'stwu'
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// on entry to the function. Add this offset back now.
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// In the prologue, the loaded (or persistent) stack pointer value is offset
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// by the STDU/STDUX/STWU/STWUX instruction. Add this offset back now.
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if (!isPPC64) {
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// If this function contained a fastcc call and GuaranteedTailCallOpt is
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// enabled (=> hasFastCall()==true) the fastcc call might contain a tail
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// call which invalidates the stack pointer value in SP(0). So we use the
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// value of R31 in this case.
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if (FI->hasFastCall() && isInt<16>(FrameSize)) {
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assert(hasFP(MF) && "Expecting a valid the frame pointer.");
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BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
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.addReg(PPC::R31).addImm(FrameSize);
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} else if(FI->hasFastCall()) {
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BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
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.addImm(FrameSize >> 16);
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BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
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.addReg(PPC::R0, RegState::Kill)
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.addImm(FrameSize & 0xFFFF);
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BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4))
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.addReg(PPC::R1)
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.addReg(PPC::R31)
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.addReg(PPC::R0);
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} else if (isInt<16>(FrameSize) &&
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!HasBP &&
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if (FI->hasFastCall()) {
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assert(HasFP && "Expecting a valid frame pointer.");
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if (!isLargeFrame) {
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BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
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.addReg(PPC::R31).addImm(FrameSize);
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} else {
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BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
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.addImm(FrameSize >> 16);
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BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
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.addReg(PPC::R0, RegState::Kill)
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.addImm(FrameSize & 0xFFFF);
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BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4))
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.addReg(PPC::R1)
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.addReg(PPC::R31)
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.addReg(PPC::R0);
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}
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} else if (!isLargeFrame && !HasBP &&
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!MFI->hasVarSizedObjects()) {
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BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
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.addReg(PPC::R1).addImm(FrameSize);
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@ -804,22 +819,24 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
|
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BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1)
|
||||
.addImm(0).addReg(PPC::R1);
|
||||
}
|
||||
} else {
|
||||
if (FI->hasFastCall() && isInt<16>(FrameSize)) {
|
||||
assert(hasFP(MF) && "Expecting a valid the frame pointer.");
|
||||
BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
|
||||
.addReg(PPC::X31).addImm(FrameSize);
|
||||
} else if(FI->hasFastCall()) {
|
||||
BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
|
||||
.addImm(FrameSize >> 16);
|
||||
BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
|
||||
.addReg(PPC::X0, RegState::Kill)
|
||||
.addImm(FrameSize & 0xFFFF);
|
||||
BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8))
|
||||
.addReg(PPC::X1)
|
||||
.addReg(PPC::X31)
|
||||
.addReg(PPC::X0);
|
||||
} else if (isInt<16>(FrameSize) && !HasBP &&
|
||||
} else { // PPC64...
|
||||
if (FI->hasFastCall()) {
|
||||
if (!isLargeFrame) {
|
||||
assert(HasFP && "Expecting a valid frame pointer.");
|
||||
BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
|
||||
.addReg(PPC::X31).addImm(FrameSize);
|
||||
} else {
|
||||
BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
|
||||
.addImm(FrameSize >> 16);
|
||||
BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
|
||||
.addReg(PPC::X0, RegState::Kill)
|
||||
.addImm(FrameSize & 0xFFFF);
|
||||
BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8))
|
||||
.addReg(PPC::X1)
|
||||
.addReg(PPC::X31)
|
||||
.addReg(PPC::X0);
|
||||
}
|
||||
} else if (!isLargeFrame && !HasBP &&
|
||||
!MFI->hasVarSizedObjects()) {
|
||||
BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
|
||||
.addReg(PPC::X1).addImm(FrameSize);
|
||||
@ -854,7 +871,7 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
|
||||
|
||||
if (MustSaveLR)
|
||||
BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0);
|
||||
} else {
|
||||
} else { // PPC32...
|
||||
if (MustSaveLR)
|
||||
BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0)
|
||||
.addImm(LROffset).addReg(PPC::R1);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user