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[PowerPC] fix latency for simple integer instructions in POWER9 scheduler

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In the POWER9 instruction scheduler, SchedWriteRes for the simple integer instructions are misconfigured to use that of (costly) DFU instructions.
This results in surprisingly long instruction latency estimation and causes misbehavior in some optimizers such as if-conversion.

Differential Revision: https://reviews.llvm.org/D34869



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307624 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hiroshi Inoue 2017-07-11 05:37:16 +00:00
parent 2ff5ec7b05
commit 9c82670849
1 changed files with 1 additions and 1 deletions
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2
lib/Target/PowerPC/PPCScheduleP9.td
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@ -260,7 +260,7 @@ let SchedModel = P9Model in {
// ***************** Defining Itinerary Class Resources *****************
def : ItinRW<[P9_DFU_76C, IP_EXEC_1C, DISP_1C, DISP_1C], [IIC_IntSimple,
def : ItinRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C], [IIC_IntSimple,
IIC_IntGeneral]>;
def : ItinRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],