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ARM: add correct kill flags when combining stm instructions

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When the store sequence being combined actually stores the base register, we
should not mark it as killed until the end.

rdar://21504262

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241003 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2015-06-29 21:42:16 +00:00
parent 7839b00d43
commit 9cbdfb5c05
2 changed files with 49 additions and 0 deletions
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6
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
View File

@ -743,6 +743,12 @@ void ARMLoadStoreOpt::MergeOpsUpdate(MachineBasicBlock &MBB,
}
}
for (unsigned i = memOpsBegin; i < memOpsEnd; ++i) {
MachineOperand &TransferOp = memOps[i].MBBI->getOperand(0);
if (TransferOp.isUse() && TransferOp.getReg() == Base)
BaseKill = false;
}
SmallVector<std::pair<unsigned, bool>, 8> Regs;
SmallVector<unsigned, 8> ImpDefs;
SmallVector<MachineOperand *, 8> UsesOfImpDefs;

43
test/CodeGen/ARM/load-store-flags.ll Normal file
View File

@ -0,0 +1,43 @@
; RUN: llc -mtriple=thumbv7-apple-ios7.0 -o - %s -verify-machineinstrs | FileCheck %s
; The base register for the store is killed by the last instruction, but is
; actually also used during as part of the store itself. If an extra ADD is
; inserted, it should not kill the base.
define void @test_base_kill(i32 %v0, i32 %v1, i32* %addr) {
; CHECK-LABEL: test_base_kill:
; CHECK: adds [[NEWBASE:r[0-9]+]], r2, #4
; CHECK: stm.w [[NEWBASE]], {r0, r1, r2}
%addr.1 = getelementptr i32, i32* %addr, i32 1
store i32 %v0, i32* %addr.1
%addr.2 = getelementptr i32, i32* %addr, i32 2
store i32 %v1, i32* %addr.2
%addr.3 = getelementptr i32, i32* %addr, i32 3
%val = ptrtoint i32* %addr to i32
store i32 %val, i32* %addr.3
ret void
}
; Similar, but it's not sufficient to look at just the last instruction (where
; liveness of the base is determined). An intervening instruction might be moved
; past it to form the STM.
define void @test_base_kill_mid(i32 %v0, i32* %addr, i32 %v1) {
; CHECK-LABEL: test_base_kill_mid:
; CHECK: adds [[NEWBASE:r[0-9]+]], r1, #4
; CHECK: stm.w [[NEWBASE]], {r0, r1, r2}
%addr.1 = getelementptr i32, i32* %addr, i32 1
store i32 %v0, i32* %addr.1
%addr.2 = getelementptr i32, i32* %addr, i32 2
%val = ptrtoint i32* %addr to i32
store i32 %val, i32* %addr.2
%addr.3 = getelementptr i32, i32* %addr, i32 3
store i32 %v1, i32* %addr.3
ret void
}