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Move pass configuration out of pass constructors: MachineLICM.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150099 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2012-02-08 21:23:03 +00:00
parent 9f17cf625d
commit 9d41bd5c78
3 changed files with 8 additions and 6 deletions
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3
include/llvm/CodeGen/Passes.h
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@ -93,6 +93,7 @@ public:
/// Add the complete, standard set of LLVM CodeGen passes. /// Add the complete, standard set of LLVM CodeGen passes.
/// Fully developed targets will not generally override this. /// Fully developed targets will not generally override this.
virtual void addMachinePasses(); virtual void addMachinePasses();
protected: protected:
// Helper to verify the analysis is really immutable. // Helper to verify the analysis is really immutable.
void setOpt(bool &Opt, bool Val); void setOpt(bool &Opt, bool Val);
@ -323,7 +324,7 @@ namespace llvm {
/// createMachineLICMPass - This pass performs LICM on machine instructions. /// createMachineLICMPass - This pass performs LICM on machine instructions.
/// ///
FunctionPass *createMachineLICMPass(bool PreRegAlloc = true); FunctionPass *createMachineLICMPass();
/// createMachineSinkingPass - This pass performs sinking on machine /// createMachineSinkingPass - This pass performs sinking on machine
/// instructions. /// instructions.

9
lib/CodeGen/MachineLICM.cpp
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@ -60,8 +60,6 @@ STATISTIC(NumPostRAHoisted,
namespace { namespace {
class MachineLICM : public MachineFunctionPass { class MachineLICM : public MachineFunctionPass {
bool PreRegAlloc;
const TargetMachine *TM; const TargetMachine *TM;
const TargetInstrInfo *TII; const TargetInstrInfo *TII;
const TargetLowering *TLI; const TargetLowering *TLI;
@ -69,6 +67,7 @@ namespace {
const MachineFrameInfo *MFI; const MachineFrameInfo *MFI;
MachineRegisterInfo *MRI; MachineRegisterInfo *MRI;
const InstrItineraryData *InstrItins; const InstrItineraryData *InstrItins;
bool PreRegAlloc;
// Various analyses that we use... // Various analyses that we use...
AliasAnalysis *AA; // Alias analysis info. AliasAnalysis *AA; // Alias analysis info.
@ -298,8 +297,8 @@ INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
INITIALIZE_PASS_END(MachineLICM, "machinelicm", INITIALIZE_PASS_END(MachineLICM, "machinelicm",
"Machine Loop Invariant Code Motion", false, false) "Machine Loop Invariant Code Motion", false, false)
FunctionPass *llvm::createMachineLICMPass(bool PreRegAlloc) { FunctionPass *llvm::createMachineLICMPass() {
return new MachineLICM(PreRegAlloc); return new MachineLICM();
} }
/// LoopIsOuterMostWithPredecessor - Test if the given loop is the outer-most /// LoopIsOuterMostWithPredecessor - Test if the given loop is the outer-most
@ -332,6 +331,8 @@ bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
MRI = &MF.getRegInfo(); MRI = &MF.getRegInfo();
InstrItins = TM->getInstrItineraryData(); InstrItins = TM->getInstrItineraryData();
PreRegAlloc = MRI->isSSA();
if (PreRegAlloc) { if (PreRegAlloc) {
// Estimate register pressure during pre-regalloc pass. // Estimate register pressure during pre-regalloc pass.
unsigned NumRC = TRI->getNumRegClasses(); unsigned NumRC = TRI->getNumRegClasses();

2
lib/CodeGen/Passes.cpp
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@ -244,7 +244,7 @@ void TargetPassConfig::addMachinePasses() {
// Run post-ra machine LICM to hoist reloads / remats. // Run post-ra machine LICM to hoist reloads / remats.
if (!DisablePostRAMachineLICM) if (!DisablePostRAMachineLICM)
PM.add(createMachineLICMPass(false)); PM.add(createMachineLICMPass());
printAndVerify("After StackSlotColoring and postra Machine LICM"); printAndVerify("After StackSlotColoring and postra Machine LICM");
} }