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Fix a regression in 403.gcc and 186.crafty introduced in 47383. To test

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that a value is >= 32, check that all of the high bits are zero, not
just one or more.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47467 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-02-22 01:12:31 +00:00
parent 95cb2ad919
commit 9e255b7df5
2 changed files with 30 additions and 28 deletions
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10
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -5147,8 +5147,8 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
APInt KnownZero, KnownOne;
DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
// If we know that the high bit of the shift amount is one, then we can do
// this as a couple of simple shifts.
// If we know that if any of the high bits of the shift amount are one, then
// we can do this as a couple of simple shifts.
if (KnownOne.intersects(Mask)) {
// Mask out the high bit, which we know is set.
Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
@ -5174,9 +5174,9 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
}
}
// If we know that the high bit of the shift amount is zero, then we can do
// this as a couple of simple shifts.
if (KnownZero.intersects(Mask)) {
// If we know that the high bits of the shift amount are all zero, then we can
// do this as a couple of simple shifts.
if ((KnownZero & Mask) == Mask) {
// Compute 32-amt.
SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
DAG.getConstant(NVTBits, Amt.getValueType()),

48
lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp
View File

@ -760,7 +760,7 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
APInt KnownZero, KnownOne;
DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
// If we don't know anything about the high bit, exit.
// If we don't know anything about the high bits, exit.
if (((KnownZero|KnownOne) & HighBitMask) == 0)
return false;
@ -768,8 +768,8 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
SDOperand InL, InH;
GetExpandedOp(N->getOperand(0), InL, InH);
// If we know that the high bit of the shift amount is one, then we can do
// this as a couple of simple shifts.
// If we know that any of the high bits of the shift amount are one, then we
// can do this as a couple of simple shifts.
if (KnownOne.intersects(HighBitMask)) {
// Mask out the high bit, which we know is set.
Amt = DAG.getNode(ISD::AND, ShTy, Amt,
@ -793,27 +793,29 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
}
}
// If we know that the high bit of the shift amount is zero, then we can do
// this as a couple of simple shifts.
assert(KnownZero.intersects(HighBitMask) && "Bad mask computation above");
// Compute 32-amt.
SDOperand Amt2 = DAG.getNode(ISD::SUB, ShTy,
DAG.getConstant(NVTBits, ShTy),
Amt);
unsigned Op1, Op2;
switch (N->getOpcode()) {
default: assert(0 && "Unknown shift");
case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
case ISD::SRL:
case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
}
// If we know that all of the high bits of the shift amount are zero, then we
// can do this as a couple of simple shifts.
if ((KnownZero & HighBitMask) == HighBitMask) {
// Compute 32-amt.
SDOperand Amt2 = DAG.getNode(ISD::SUB, ShTy,
DAG.getConstant(NVTBits, ShTy),
Amt);
unsigned Op1, Op2;
switch (N->getOpcode()) {
default: assert(0 && "Unknown shift");
case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
case ISD::SRL:
case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
}
Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
Hi = DAG.getNode(ISD::OR, NVT,
DAG.getNode(Op1, NVT, InH, Amt),
DAG.getNode(Op2, NVT, InL, Amt2));
return true;
Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
Hi = DAG.getNode(ISD::OR, NVT,
DAG.getNode(Op1, NVT, InH, Amt),
DAG.getNode(Op2, NVT, InL, Amt2));
return true;
}
return false;
}