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Implement next round of Pattern ISel fixes
1. void returns 2. multiplies 3. calls git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20822 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman
parent
7ca541b75a
commit
9e3e1b5d44
@ -221,10 +221,16 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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// Promote the integer to 32 bits. If the input type is signed use a
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// sign extend, otherwise use a zero extend.
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if (Args[i].second->isSigned())
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Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
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else
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Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
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break;
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case MVT::i32:
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case MVT::i64:
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case MVT::f64:
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case MVT::f32:
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case MVT::f64:
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break;
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}
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args_to_use.push_back(Args[i].first);
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@ -438,14 +444,33 @@ unsigned ISel::SelectExpr(SDOperand N) {
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unsigned &Reg = ExprMap[N];
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if (Reg) return Reg;
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if (DestType == MVT::f64 || DestType == MVT::f32)
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return SelectExprFP(N, Result);
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if (N.getOpcode() != ISD::CALL)
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if (N.getOpcode() != ISD::CALL && N.getOpcode() != ISD::ADD_PARTS &&
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N.getOpcode() != ISD::SUB_PARTS)
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Reg = Result = (N.getValueType() != MVT::Other) ?
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MakeReg(N.getValueType()) : 1;
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else
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abort(); // FIXME: Implement Call
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else {
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// If this is a call instruction, make sure to prepare ALL of the result
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// values as well as the chain.
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if (N.getOpcode() == ISD::CALL) {
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if (Node->getNumValues() == 1)
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Reg = Result = 1; // Void call, just a chain.
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else {
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Result = MakeReg(Node->getValueType(0));
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ExprMap[N.getValue(0)] = Result;
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for (unsigned i = 1, e = N.Val->getNumValues()-1; i != e; ++i)
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ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
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ExprMap[SDOperand(Node, Node->getNumValues()-1)] = 1;
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}
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} else {
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Result = MakeReg(Node->getValueType(0));
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ExprMap[N.getValue(0)] = Result;
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for (unsigned i = 1, e = N.Val->getNumValues(); i != e; ++i)
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ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
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}
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}
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if (DestType == MVT::f64 || DestType == MVT::f32)
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return SelectExprFP(N, Result);
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switch (opcode) {
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default:
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@ -482,10 +507,24 @@ unsigned ISel::SelectExpr(SDOperand N) {
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case ISD::FrameIndex:
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abort();
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case ISD::GlobalAddress: {
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GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
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unsigned Tmp1 = MakeReg(MVT::i32);
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// FIXME: R1 is incorrect, we need the getGlobalBaseReg() functionality
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// from the simple isel
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BuildMI(BB, PPC::LOADHiAddr, 2, Tmp1).addReg(PPC::R1).addGlobalAddress(GV);
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if (GV->hasWeakLinkage() || GV->isExternal()) {
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BuildMI(BB, PPC::LWZ, 2, Result).addGlobalAddress(GV).addReg(Tmp1);
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} else {
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BuildMI(BB, PPC::LA, 2, Result).addReg(Tmp1).addGlobalAddress(GV);
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}
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return Result;
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}
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case ISD::LOAD:
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case ISD::EXTLOAD:
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case ISD::ZEXTLOAD:
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{
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case ISD::SEXTLOAD: {
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// Make sure we generate both values.
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if (Result != 1)
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ExprMap[N.getValue(1)] = 1; // Generate the token
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@ -498,22 +537,13 @@ unsigned ISel::SelectExpr(SDOperand N) {
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switch (Node->getValueType(0)) {
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default: assert(0 && "Cannot load this type!");
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case MVT::i1:
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case MVT::i8: Opc = PPC::LBZ; break;
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case MVT::i16: Opc = PPC::LHZ; break;
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case MVT::i32: Opc = PPC::LWZ; break;
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case MVT::i1: Opc = PPC::LBZ; Tmp3 = 0; break;
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case MVT::i8: Opc = PPC::LBZ; Tmp3 = 1; break;
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case MVT::i16: Opc = PPC::LHZ; Tmp3 = 0; break;
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case MVT::i32: Opc = PPC::LWZ; Tmp3 = 0; break;
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}
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if (Address.getOpcode() == ISD::GlobalAddress) { // FIXME
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BuildMI(BB, Opc, 2, Result)
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.addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal())
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.addReg(PPC::R1);
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}
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else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
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BuildMI(BB, Opc, 2, Result).addConstantPoolIndex(CP->getIndex())
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.addReg(PPC::R1);
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}
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else if(Address.getOpcode() == ISD::FrameIndex) {
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if(Address.getOpcode() == ISD::FrameIndex) {
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BuildMI(BB, Opc, 2, Result)
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.addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
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.addReg(PPC::R1);
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@ -525,10 +555,93 @@ unsigned ISel::SelectExpr(SDOperand N) {
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return Result;
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}
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case ISD::SEXTLOAD:
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case ISD::GlobalAddress:
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case ISD::CALL:
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abort();
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case ISD::CALL: {
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// Lower the chain for this call.
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Select(N.getOperand(0));
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ExprMap[N.getValue(Node->getNumValues()-1)] = 1;
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// get the virtual reg for each argument
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std::vector<unsigned> VRegs;
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for(int i = 2, e = Node->getNumOperands(); i < e; ++i)
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VRegs.push_back(SelectExpr(N.getOperand(i)));
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// The ABI specifies that the first 32 bytes of args may be passed in GPRs,
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// and that 13 FPRs may also be used for passing any floating point args.
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int GPR_remaining = 8, FPR_remaining = 13;
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unsigned GPR_idx = 0, FPR_idx = 0;
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static const unsigned GPR[] = {
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PPC::R3, PPC::R4, PPC::R5, PPC::R6,
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PPC::R7, PPC::R8, PPC::R9, PPC::R10,
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};
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static const unsigned FPR[] = {
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PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6,
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PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12,
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PPC::F13
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};
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// move the vregs into the appropriate architected register or stack slot
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for(int i = 0, e = VRegs.size(); i < e; ++i) {
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unsigned OperandType = N.getOperand(i+2).getValueType();
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switch(OperandType) {
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default:
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Node->dump();
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N.getOperand(i).Val->dump();
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std::cerr << "Type for " << i << " is: " <<
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N.getOperand(i+2).getValueType() << "\n";
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assert(0 && "Unknown value type for call");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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if (GPR_remaining > 0)
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BuildMI(BB, PPC::OR, 2, GPR[GPR_idx]).addReg(VRegs[i])
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.addReg(VRegs[i]);
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break;
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case MVT::f32:
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case MVT::f64:
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if (FPR_remaining > 0) {
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BuildMI(BB, PPC::FMR, 1, FPR[FPR_idx]).addReg(VRegs[i]);
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--FPR_remaining;
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}
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break;
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}
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// All arguments consume GPRs available for argument passing
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if (GPR_remaining > 0) --GPR_remaining;
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if (MVT::f64 == OperandType && GPR_remaining > 0) --GPR_remaining;
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}
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// Emit the correct call instruction based on the type of symbol called.
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if (GlobalAddressSDNode *GASD =
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dyn_cast<GlobalAddressSDNode>(N.getOperand(1))) {
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BuildMI(BB, PPC::CALLpcrel, 1).addGlobalAddress(GASD->getGlobal(), true);
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} else if (ExternalSymbolSDNode *ESSDN =
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dyn_cast<ExternalSymbolSDNode>(N.getOperand(1))) {
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BuildMI(BB, PPC::CALLpcrel, 1).addExternalSymbol(ESSDN->getSymbol(), true);
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} else {
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Tmp1 = SelectExpr(N.getOperand(1));
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BuildMI(BB, PPC::OR, 2, PPC::R12).addReg(Tmp1).addReg(Tmp1);
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BuildMI(BB, PPC::MTCTR, 1).addReg(PPC::R12);
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BuildMI(BB, PPC::CALLindirect, 3).addImm(20).addImm(0).addReg(PPC::R12);
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}
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switch (Node->getValueType(0)) {
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default: assert(0 && "Unknown value type for call result!");
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case MVT::Other: return 1;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R3);
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if (Node->getValueType(1) == MVT::i32)
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BuildMI(BB, PPC::OR, 2, Result+1).addReg(PPC::R4);
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break;
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case MVT::f32:
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case MVT::f64:
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BuildMI(BB, PPC::FMR, 1, Result).addReg(PPC::F1);
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break;
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}
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return Result+N.ResNo;
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}
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case ISD::SIGN_EXTEND:
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case ISD::SIGN_EXTEND_INREG:
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@ -551,9 +664,6 @@ unsigned ISel::SelectExpr(SDOperand N) {
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.addImm(Tmp2).addImm(31);
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return Result;
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case ISD::SETCC:
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abort();
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case ISD::CopyFromReg:
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if (Result == 1)
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Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
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@ -614,13 +724,6 @@ unsigned ISel::SelectExpr(SDOperand N) {
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}
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return Result;
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case ISD::SUB:
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assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, PPC::SUBF, 2, Result).addReg(Tmp2).addReg(Tmp1);
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return Result;
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case ISD::AND:
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case ISD::OR:
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case ISD::XOR:
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@ -656,7 +759,22 @@ unsigned ISel::SelectExpr(SDOperand N) {
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}
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return Result;
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case ISD::SUB:
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assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, PPC::SUBF, 2, Result).addReg(Tmp2).addReg(Tmp1);
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return Result;
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case ISD::MUL:
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assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, PPC::MULLW, 2, Result).addReg(Tmp2).addReg(Tmp1);
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return Result;
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case ISD::ADD_PARTS:
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case ISD::SUB_PARTS:
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case ISD::UREM:
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case ISD::SREM:
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case ISD::SDIV:
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@ -667,6 +785,9 @@ unsigned ISel::SelectExpr(SDOperand N) {
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case ISD::FP_TO_SINT:
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abort();
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case ISD::SETCC:
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abort();
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case ISD::SELECT:
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abort();
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@ -776,6 +897,9 @@ void ISel::Select(SDOperand N) {
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BuildMI(BB, PPC::OR, 2, PPC::R3).addReg(Tmp1).addReg(Tmp1);
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break;
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}
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case 1:
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Select(N.getOperand(0));
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break;
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}
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BuildMI(BB, PPC::BLR, 0); // Just emit a 'ret' instruction
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return;
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