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ARM assembly parsing two operand forms for shift instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144713 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-11-15 22:27:54 +00:00
parent 7b95c38813
commit 9f302c4fb3
2 changed files with 18 additions and 0 deletions
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10
lib/Target/ARM/ARMInstrInfo.td
View File

@ -5023,6 +5023,16 @@ def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
(ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
cc_out:$s)>;
// shifter instructions also support a two-operand form.
def : ARMInstAlias<"asr${s}${p} $Rm, $imm",
(ASRi GPR:$Rm, GPR:$Rm, imm0_32:$imm, pred:$p, cc_out:$s)>;
def : ARMInstAlias<"lsr${s}${p} $Rm, $imm",
(LSRi GPR:$Rm, GPR:$Rm, imm0_32:$imm, pred:$p, cc_out:$s)>;
def : ARMInstAlias<"lsl${s}${p} $Rm, $imm",
(LSLi GPR:$Rm, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s)>;
def : ARMInstAlias<"ror${s}${p} $Rm, $imm",
(RORi GPR:$Rm, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s)>;
// 'mul' instruction can be specified with only two operands.
def : ARMInstAlias<"mul${s}${p} $Rn, $Rm",

8
test/MC/ARM/basic-arm-instructions.s
View File

@ -262,10 +262,12 @@ Lforward:
asr r2, r4, #32
asr r2, r4, #2
asr r2, r4, #0
asr r4, #2
@ CHECK: asr r2, r4, #32 @ encoding: [0x44,0x20,0xa0,0xe1]
@ CHECK: asr r2, r4, #2 @ encoding: [0x44,0x21,0xa0,0xe1]
@ CHECK: mov r2, r4 @ encoding: [0x04,0x20,0xa0,0xe1]
@ CHECK: asr r4, r4, #2 @ encoding: [0x44,0x41,0xa0,0xe1]
@------------------------------------------------------------------------------
@ -794,10 +796,12 @@ Lforward:
lsl r2, r4, #31
lsl r2, r4, #1
lsl r2, r4, #0
lsl r4, #1
@ CHECK: lsl r2, r4, #31 @ encoding: [0x84,0x2f,0xa0,0xe1]
@ CHECK: lsl r2, r4, #1 @ encoding: [0x84,0x20,0xa0,0xe1]
@ CHECK: mov r2, r4 @ encoding: [0x04,0x20,0xa0,0xe1]
@ CHECK: lsl r4, r4, #1 @ encoding: [0x84,0x40,0xa0,0xe1]
@------------------------------------------------------------------------------
@ -806,10 +810,12 @@ Lforward:
lsr r2, r4, #32
lsr r2, r4, #2
lsr r2, r4, #0
lsr r4, #2
@ CHECK: lsr r2, r4, #32 @ encoding: [0x24,0x20,0xa0,0xe1]
@ CHECK: lsr r2, r4, #2 @ encoding: [0x24,0x21,0xa0,0xe1]
@ CHECK: mov r2, r4 @ encoding: [0x04,0x20,0xa0,0xe1]
@ CHECK: lsr r4, r4, #2 @ encoding: [0x24,0x41,0xa0,0xe1]
@------------------------------------------------------------------------------
@ -1346,10 +1352,12 @@ Lforward:
ror r2, r4, #31
ror r2, r4, #1
ror r2, r4, #0
ror r4, #1
@ CHECK: ror r2, r4, #31 @ encoding: [0xe4,0x2f,0xa0,0xe1]
@ CHECK: ror r2, r4, #1 @ encoding: [0xe4,0x20,0xa0,0xe1]
@ CHECK: mov r2, r4 @ encoding: [0x04,0x20,0xa0,0xe1]
@ CHECK: ror r4, r4, #1 @ encoding: [0xe4,0x40,0xa0,0xe1]
@------------------------------------------------------------------------------