From 9f782d4dcf580ae508cc83f412884cd3c5f9207d Mon Sep 17 00:00:00 2001 From: Eric Christopher Date: Tue, 24 Aug 2010 22:03:02 +0000 Subject: [PATCH] Fix thumb2 mode loads to have the correct operand ordering. Add a todo to fix this in the port. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111973 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMFastISel.cpp | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp index 55fb7c26d5a..81ecdb50edf 100644 --- a/lib/Target/ARM/ARMFastISel.cpp +++ b/lib/Target/ARM/ARMFastISel.cpp @@ -419,10 +419,15 @@ bool ARMFastISel::ARMSelectLoad(const Instruction *I) { // TODO: Verify the additions above work, otherwise we'll need to add the // offset instead of 0 and do all sorts of operand munging. unsigned ResultReg = createResultReg(FixedRC); - unsigned Opc = AFI->isThumb2Function() ? ARM::tLDR : ARM::LDR; - AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, - TII.get(Opc), ResultReg) - .addReg(Reg).addReg(0).addImm(0)); + // TODO: Fix the Addressing modes so that these can share some code. + if (AFI->isThumb2Function()) + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(ARM::tLDR), ResultReg) + .addReg(Reg).addImm(0).addReg(0)); + else + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(ARM::LDR), ResultReg) + .addReg(Reg).addReg(0).addImm(0)); UpdateValueMap(I, ResultReg); return true;