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Merging r327651:

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r327651 | carrot | 2018-03-15 10:49:12 -0700 (Thu, 15 Mar 2018) | 9 lines

[PPC] Avoid non-simple MVT in STBRX optimization

PR35402 triggered this case. It bswap and stores a 48bit value, current STBRX optimization transforms it into STBRX. Unfortunately 48bit is not a simple MVT, there is no PPC instruction to support it, and it can't be automatically expanded by llvm, so caused a crash.

This patch detects the non-simple MVT and returns early.

Differential Revision: https://reviews.llvm.org/D44500

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@329641 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2018-04-09 23:19:44 +00:00
parent 7e48926dae
commit 9fa366d3c1
2 changed files with 23 additions and 1 deletions
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6
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -12264,6 +12264,11 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
N->getOperand(1).getValueType() == MVT::i16 || N->getOperand(1).getValueType() == MVT::i16 ||
(Subtarget.hasLDBRX() && Subtarget.isPPC64() && (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
N->getOperand(1).getValueType() == MVT::i64))) { N->getOperand(1).getValueType() == MVT::i64))) {
// STBRX can only handle simple types.
EVT mVT = cast<StoreSDNode>(N)->getMemoryVT();
if (mVT.isExtended())
break;
SDValue BSwapOp = N->getOperand(1).getOperand(0); SDValue BSwapOp = N->getOperand(1).getOperand(0);
// Do an any-extend to 32-bits if this is a half-word input. // Do an any-extend to 32-bits if this is a half-word input.
if (BSwapOp.getValueType() == MVT::i16) if (BSwapOp.getValueType() == MVT::i16)
@ -12271,7 +12276,6 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
// If the type of BSWAP operand is wider than stored memory width // If the type of BSWAP operand is wider than stored memory width
// it need to be shifted to the right side before STBRX. // it need to be shifted to the right side before STBRX.
EVT mVT = cast<StoreSDNode>(N)->getMemoryVT();
if (Op1VT.bitsGT(mVT)) { if (Op1VT.bitsGT(mVT)) {
int Shift = Op1VT.getSizeInBits() - mVT.getSizeInBits(); int Shift = Op1VT.getSizeInBits() - mVT.getSizeInBits();
BSwapOp = DAG.getNode(ISD::SRL, dl, Op1VT, BSwapOp, BSwapOp = DAG.getNode(ISD::SRL, dl, Op1VT, BSwapOp,

18
test/CodeGen/PowerPC/pr35402.ll Normal file
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@ -0,0 +1,18 @@
; RUN: llc -O2 < %s | FileCheck %s
target triple = "powerpc64le-linux-gnu"
define void @test(i8* %p, i64 %data) {
entry:
%0 = tail call i64 @llvm.bswap.i64(i64 %data)
%ptr = bitcast i8* %p to i48*
%val = trunc i64 %0 to i48
store i48 %val, i48* %ptr, align 1
ret void
; CHECK: sth
; CHECK: stw
; CHECK-NOT: stdbrx
}
declare i64 @llvm.bswap.i64(i64)