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Fix an issue where the ordering of blocks within a function could lead to different constraint

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graphs being produced.  The cause was that we were incorrectly marking sigma instructions as
processed after handling the sigma-specific constraints for them, potentially neglecting to
process them as normal instructions as well.

Unfortunately, the testcase that inspired this still doesn't work because of a bug in the solver,
which is next on the list to debug.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86486 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2009-11-08 22:36:55 +00:00
parent 7e3089d3c6
commit 9feeeaf9ed
1 changed files with 4 additions and 2 deletions
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6
lib/Transforms/Scalar/ABCD.cpp
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@ -796,13 +796,15 @@ void ABCD::createConstraintSigInst(Instruction *I_op, BasicBlock *BB_succ_t,
int32_t width = cast<IntegerType>((*SIG_op_t)->getType())->getBitWidth();
inequality_graph.addEdge(I_op, *SIG_op_t, APInt(width, 0), true);
inequality_graph.addEdge(*SIG_op_t, I_op, APInt(width, 0), false);
created.insert(*SIG_op_t);
if (created.insert(*SIG_op_t))
createConstraintPHINode(cast<PHINode>(*SIG_op_t));
}
if (*SIG_op_f) {
int32_t width = cast<IntegerType>((*SIG_op_f)->getType())->getBitWidth();
inequality_graph.addEdge(I_op, *SIG_op_f, APInt(width, 0), true);
inequality_graph.addEdge(*SIG_op_f, I_op, APInt(width, 0), false);
created.insert(*SIG_op_f);
if (created.insert(*SIG_op_f))
createConstraintPHINode(cast<PHINode>(*SIG_op_f));
}
}