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Remove an argument-less call to getSubtargetImpl from TargetLoweringBase.

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This required plumbing a TargetRegisterInfo through computeRegisterProperties
and into findRepresentativeClass which uses it for register class
iteration. This required passing a subtarget into a few target specific
initializations of TargetLowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230583 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2015-02-26 00:00:24 +00:00
parent e9a49d61ac
commit a01bc6a59f
23 changed files with 48 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
include/llvm/Target/TargetLowering.h
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@ -1225,12 +1225,12 @@ protected:
/// Return the largest legal super-reg register class of the register class
/// for the specified type and its associated "cost".
virtual std::pair<const TargetRegisterClass*, uint8_t>
findRepresentativeClass(MVT VT) const;
virtual std::pair<const TargetRegisterClass *, uint8_t>
findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
/// Once all of the register classes are added, this allows us to compute
/// derived properties we expose.
void computeRegisterProperties();
void computeRegisterProperties(const TargetRegisterInfo *TRI);
/// Indicate that the specified operation does not work with the specified
/// type and indicate what to do about it.

12
lib/CodeGen/TargetLoweringBase.cpp
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@ -1144,10 +1144,9 @@ TargetLoweringBase::emitPatchPoint(MachineInstr *MI,
/// findRepresentativeClass - Return the largest legal super-reg register class
/// of the register class for the specified type and its associated "cost".
std::pair<const TargetRegisterClass*, uint8_t>
TargetLoweringBase::findRepresentativeClass(MVT VT) const {
const TargetRegisterInfo *TRI =
getTargetMachine().getSubtargetImpl()->getRegisterInfo();
std::pair<const TargetRegisterClass *, uint8_t>
TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI,
MVT VT) const {
const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
if (!RC)
return std::make_pair(RC, 0);
@ -1173,7 +1172,8 @@ TargetLoweringBase::findRepresentativeClass(MVT VT) const {
/// computeRegisterProperties - Once all of the register classes are added,
/// this allows us to compute derived properties we expose.
void TargetLoweringBase::computeRegisterProperties() {
void TargetLoweringBase::computeRegisterProperties(
const TargetRegisterInfo *TRI) {
static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE,
"Too many value types for ValueTypeActions to hold!");
@ -1355,7 +1355,7 @@ void TargetLoweringBase::computeRegisterProperties() {
for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
const TargetRegisterClass* RRC;
uint8_t Cost;
std::tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i);
RepRegClassForVT[i] = RRC;
RepRegClassCostForVT[i] = Cost;
}

2
lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -111,7 +111,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
}
// Compute derived properties from the register classes
computeRegisterProperties();
computeRegisterProperties(Subtarget->getRegisterInfo());
// Provide all sorts of operation actions
setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);

9
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -618,7 +618,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
}
computeRegisterProperties();
computeRegisterProperties(Subtarget->getRegisterInfo());
// ARM does not have floating-point extending loads.
for (MVT VT : MVT::fp_valuetypes()) {
@ -967,13 +967,14 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
// of the difficulty prior to coalescing of modeling operand register classes
// due to the common occurrence of cross class copies and subregister insertions
// and extractions.
std::pair<const TargetRegisterClass*, uint8_t>
ARMTargetLowering::findRepresentativeClass(MVT VT) const{
std::pair<const TargetRegisterClass *, uint8_t>
ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
MVT VT) const {
const TargetRegisterClass *RRC = nullptr;
uint8_t Cost = 1;
switch (VT.SimpleTy) {
default:
return TargetLowering::findRepresentativeClass(VT);
return TargetLowering::findRepresentativeClass(TRI, VT);
// Use DPR as representative register class for all floating point
// and vector types. Since there are 32 SPR registers and 32 DPR registers so
// the cost is 1 for both f32 and f64.

5
lib/Target/ARM/ARMISelLowering.h
View File

@ -411,8 +411,9 @@ namespace llvm {
unsigned &Cost) const override;
protected:
std::pair<const TargetRegisterClass*, uint8_t>
findRepresentativeClass(MVT VT) const override;
std::pair<const TargetRegisterClass *, uint8_t>
findRepresentativeClass(const TargetRegisterInfo *TRI,
MVT VT) const override;
private:
/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can

5
lib/Target/BPF/BPFISelLowering.cpp
View File

@ -88,14 +88,15 @@ public:
int DiagnosticInfoUnsupported::KindID = 0;
}
BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM)
BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM,
const BPFSubtarget &STI)
: TargetLowering(TM) {
// Set up the register classes.
addRegisterClass(MVT::i64, &BPF::GPRRegClass);
// Compute derived properties from the register classes
computeRegisterProperties();
computeRegisterProperties(STI.getRegisterInfo());
setStackPointerRegisterToSaveRestore(BPF::R11);

2
lib/Target/BPF/BPFISelLowering.h
View File

@ -33,7 +33,7 @@ enum {
class BPFTargetLowering : public TargetLowering {
public:
explicit BPFTargetLowering(const TargetMachine &TM);
explicit BPFTargetLowering(const TargetMachine &TM, const BPFSubtarget &STI);
// Provide custom lowering hooks for some operations.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;

2
lib/Target/BPF/BPFSubtarget.cpp
View File

@ -28,4 +28,4 @@ void BPFSubtarget::anchor() {}
BPFSubtarget::BPFSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, const TargetMachine &TM)
: BPFGenSubtargetInfo(TT, CPU, FS), InstrInfo(), FrameLowering(*this),
TLInfo(TM), TSInfo(TM.getDataLayout()) {}
TLInfo(TM, *this), TSInfo(TM.getDataLayout()) {}

2
lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@ -1055,7 +1055,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
computeRegisterProperties();
computeRegisterProperties(Subtarget->getRegisterInfo());
// Align loop entry
setPrefLoopAlignment(4);

5
lib/Target/MSP430/MSP430ISelLowering.cpp
View File

@ -57,7 +57,8 @@ HWMultMode("msp430-hwmult-mode", cl::Hidden,
"Assume hardware multiplier cannot be used inside interrupts"),
clEnumValEnd));
MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM)
MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM,
const MSP430Subtarget &STI)
: TargetLowering(TM) {
// Set up the register classes.
@ -65,7 +66,7 @@ MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM)
addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
// Compute derived properties from the register classes
computeRegisterProperties();
computeRegisterProperties(STI.getRegisterInfo());
// Provide all sorts of operation actions

4
lib/Target/MSP430/MSP430ISelLowering.h
View File

@ -66,9 +66,11 @@ namespace llvm {
};
}
class MSP430Subtarget;
class MSP430TargetLowering : public TargetLowering {
public:
explicit MSP430TargetLowering(const TargetMachine &TM);
explicit MSP430TargetLowering(const TargetMachine &TM,
const MSP430Subtarget &STI);
MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i8; }

2
lib/Target/MSP430/MSP430Subtarget.cpp
View File

@ -33,5 +33,5 @@ MSP430Subtarget &MSP430Subtarget::initializeSubtargetDependencies(StringRef CPU,
MSP430Subtarget::MSP430Subtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, const TargetMachine &TM)
: MSP430GenSubtargetInfo(TT, CPU, FS), FrameLowering(),
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM),
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
TSInfo(*TM.getDataLayout()) {}

2
lib/Target/Mips/Mips16ISelLowering.cpp
View File

@ -149,7 +149,7 @@ Mips16TargetLowering::Mips16TargetLowering(const MipsTargetMachine &TM,
setOperationAction(ISD::BSWAP, MVT::i32, Expand);
setOperationAction(ISD::BSWAP, MVT::i64, Expand);
computeRegisterProperties();
computeRegisterProperties(STI.getRegisterInfo());
}
const MipsTargetLowering *

2
lib/Target/Mips/MipsSEISelLowering.cpp
View File

@ -224,7 +224,7 @@ MipsSETargetLowering::MipsSETargetLowering(const MipsTargetMachine &TM,
setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
}
computeRegisterProperties();
computeRegisterProperties(Subtarget.getRegisterInfo());
}
const MipsTargetLowering *

2
lib/Target/NVPTX/NVPTXISelLowering.cpp
View File

@ -271,7 +271,7 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
// Now deduce the information based on the above mentioned
// actions
computeRegisterProperties();
computeRegisterProperties(STI.getRegisterInfo());
}
const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {

2
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -880,7 +880,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
else
setSchedulingPreference(Sched::Hybrid);
computeRegisterProperties();
computeRegisterProperties(STI.getRegisterInfo());
// The Freescale cores do better with aggressive inlining of memcpy and
// friends. GCC uses same threshold of 128 bytes (= 32 word stores).

2
lib/Target/R600/R600ISelLowering.cpp
View File

@ -40,7 +40,7 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM,
addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass);
addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass);
computeRegisterProperties();
computeRegisterProperties(STI.getRegisterInfo());
// Set condition code actions
setCondCodeAction(ISD::SETO, MVT::f32, Expand);

2
lib/Target/R600/SIISelLowering.cpp
View File

@ -60,7 +60,7 @@ SITargetLowering::SITargetLowering(TargetMachine &TM,
addRegisterClass(MVT::v16i32, &AMDGPU::SReg_512RegClass);
addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
computeRegisterProperties();
computeRegisterProperties(STI.getRegisterInfo());
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);

2
lib/Target/Sparc/SparcISelLowering.cpp
View File

@ -1669,7 +1669,7 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM,
setMinFunctionAlignment(2);
computeRegisterProperties();
computeRegisterProperties(Subtarget->getRegisterInfo());
}
const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {

2
lib/Target/SystemZ/SystemZISelLowering.cpp
View File

@ -96,7 +96,7 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &tm,
addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
// Compute derived properties from the register classes
computeRegisterProperties();
computeRegisterProperties(Subtarget.getRegisterInfo());
// Set up special registers.
setExceptionPointerRegister(SystemZ::R6D);

9
lib/Target/X86/X86ISelLowering.cpp
View File

@ -1694,7 +1694,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setTargetDAGCombine(ISD::MUL);
setTargetDAGCombine(ISD::XOR);
computeRegisterProperties();
computeRegisterProperties(Subtarget->getRegisterInfo());
// On Darwin, -Os means optimize for size without hurting performance,
// do not reduce the limit.
@ -1931,13 +1931,14 @@ getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
}
// FIXME: Why this routine is here? Move to RegInfo!
std::pair<const TargetRegisterClass*, uint8_t>
X86TargetLowering::findRepresentativeClass(MVT VT) const{
std::pair<const TargetRegisterClass *, uint8_t>
X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
MVT VT) const {
const TargetRegisterClass *RRC = nullptr;
uint8_t Cost = 1;
switch (VT.SimpleTy) {
default:
return TargetLowering::findRepresentativeClass(VT);
return TargetLowering::findRepresentativeClass(TRI, VT);
case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
break;

5
lib/Target/X86/X86ISelLowering.h
View File

@ -850,8 +850,9 @@ namespace llvm {
LegalizeTypeAction getPreferredVectorAction(EVT VT) const override;
protected:
std::pair<const TargetRegisterClass*, uint8_t>
findRepresentativeClass(MVT VT) const override;
std::pair<const TargetRegisterClass *, uint8_t>
findRepresentativeClass(const TargetRegisterInfo *TRI,
MVT VT) const override;
private:
/// Keep a pointer to the X86Subtarget around so that we can

2
lib/Target/XCore/XCoreISelLowering.cpp
View File

@ -76,7 +76,7 @@ XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM,
addRegisterClass(MVT::i32, &XCore::GRRegsRegClass);
// Compute derived properties from the register classes
computeRegisterProperties();
computeRegisterProperties(Subtarget.getRegisterInfo());
// Division is expensive
setIntDivIsCheap(false);