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[mips] Fix delay slot filler so that instructions with register operand $1 are

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allowed in branch delay slot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168131 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2012-11-16 02:39:34 +00:00
parent 96952bd3b1
commit a032dbd62f
2 changed files with 67 additions and 18 deletions
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53
lib/Target/Mips/MipsDelaySlotFiller.cpp
View File

@ -231,31 +231,48 @@ bool Filler::delayHasHazard(InstrIter candidate,
return false; return false;
} }
// Helper function for getting a MachineOperand's register number and adding it
// to RegDefs or RegUses.
static void insertDefUse(const MachineOperand &MO,
SmallSet<unsigned, 32> &RegDefs,
SmallSet<unsigned, 32> &RegUses,
unsigned ExcludedReg = 0) {
unsigned Reg;
if (!MO.isReg() || !(Reg = MO.getReg()) || (Reg == ExcludedReg))
return;
if (MO.isDef())
RegDefs.insert(Reg);
else if (MO.isUse())
RegUses.insert(Reg);
}
// Insert Defs and Uses of MI into the sets RegDefs and RegUses. // Insert Defs and Uses of MI into the sets RegDefs and RegUses.
void Filler::insertDefsUses(InstrIter MI, void Filler::insertDefsUses(InstrIter MI,
SmallSet<unsigned, 32> &RegDefs, SmallSet<unsigned, 32> &RegDefs,
SmallSet<unsigned, 32> &RegUses) { SmallSet<unsigned, 32> &RegUses) {
// If MI is a call or return, just examine the explicit non-variadic operands. unsigned I, E = MI->getDesc().getNumOperands();
MCInstrDesc MCID = MI->getDesc();
unsigned e = MI->isCall() || MI->isReturn() ? MCID.getNumOperands() :
MI->getNumOperands();
// Add RA to RegDefs to prevent users of RA from going into delay slot. for (I = 0; I != E; ++I)
if (MI->isCall()) insertDefUse(MI->getOperand(I), RegDefs, RegUses);
// If MI is a call, add RA to RegDefs to prevent users of RA from going into
// delay slot.
if (MI->isCall()) {
RegDefs.insert(Mips::RA); RegDefs.insert(Mips::RA);
return;
for (unsigned i = 0; i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
unsigned Reg;
if (!MO.isReg() || !(Reg = MO.getReg()))
continue;
if (MO.isDef())
RegDefs.insert(Reg);
else if (MO.isUse())
RegUses.insert(Reg);
} }
// Return if MI is a return.
if (MI->isReturn())
return;
// Examine the implicit operands. Exclude register AT which is in the list of
// clobbered registers of branch instructions.
E = MI->getNumOperands();
for (; I != E; ++I)
insertDefUse(MI->getOperand(I), RegDefs, RegUses, Mips::AT);
} }
//returns true if the Reg or its alias is in the RegSet. //returns true if the Reg or its alias is in the RegSet.

32
test/CodeGen/Mips/brdelayslot.ll
View File

@ -35,3 +35,35 @@ entry:
declare void @foo4(double) declare void @foo4(double)
@g2 = external global i32
@g1 = external global i32
@g3 = external global i32
; Check that branch delay slot can be filled with an instruction with operand
; $1.
;
; Default: foo5:
; Default-NOT: nop
define void @foo5(i32 %a) nounwind {
entry:
%0 = load i32* @g2, align 4
%tobool = icmp eq i32 %a, 0
br i1 %tobool, label %if.else, label %if.then
if.then:
%1 = load i32* @g1, align 4
%add = add nsw i32 %1, %0
store i32 %add, i32* @g1, align 4
br label %if.end
if.else:
%2 = load i32* @g3, align 4
%sub = sub nsw i32 %2, %0
store i32 %sub, i32* @g3, align 4
br label %if.end
if.end:
ret void
}