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AArch64: print NEON lists with a space.

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This matches ARM64 behaviour, which I think is clearer. It also puts all the
churn from that difference into one easily ignored commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207116 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2014-04-24 14:06:20 +00:00
parent 23a4885f59
commit a05d37e1f4
15 changed files with 1515 additions and 1515 deletions
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4
lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
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@ -520,7 +520,7 @@ void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
unsigned Reg = MI->getOperand(OpNum).getReg();
std::string LayoutStr = A64VectorLayoutToString(Layout);
O << "{";
O << "{ ";
if (Count > 1) { // Print sub registers separately
bool IsVec64 = (Layout < A64Layout::VL_16B);
unsigned SubRegIdx = IsVec64 ? AArch64::dsub_0 : AArch64::qsub_0;
@ -536,5 +536,5 @@ void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
Name[0] = 'v';
O << Name << LayoutStr;
}
O << "}";
O << " }";
}

6
test/CodeGen/AArch64/neon-copyPhysReg-tuple.ll
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@ -5,7 +5,7 @@ define <4 x i32> @copyTuple.QPair(i8* %a, i8* %b) {
; CHECK-LABEL: copyTuple.QPair:
; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
; CHECK: ld2 {{{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x{{[0-9]+|sp}}]
; CHECK: ld2 { {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x{{[0-9]+|sp}}]
entry:
%vld = tail call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2lane.v4i32(i8* %a, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 2, i32 2, i32 2, i32 2>, i32 0, i32 4)
%extract = extractvalue { <4 x i32>, <4 x i32> } %vld, 0
@ -19,7 +19,7 @@ define <4 x i32> @copyTuple.QTriple(i8* %a, i8* %b, <4 x i32> %c) {
; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
; CHECK: ld3 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x{{[0-9]+|sp}}]
; CHECK: ld3 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x{{[0-9]+|sp}}]
entry:
%vld = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld3lane.v4i32(i8* %a, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %c, <4 x i32> %c, i32 0, i32 4)
%extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld, 0
@ -34,7 +34,7 @@ define <4 x i32> @copyTuple.QQuad(i8* %a, i8* %b, <4 x i32> %c) {
; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
; CHECK: ld4 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x{{[0-9]+|sp}}]
; CHECK: ld4 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x{{[0-9]+|sp}}]
entry:
%vld = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld4lane.v4i32(i8* %a, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %c, <4 x i32> %c, <4 x i32> %c, i32 0, i32 4)
%extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %vld, 0

420
test/CodeGen/AArch64/neon-simd-ldst-multi-elem.ll
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File diff suppressed because it is too large Load Diff

294
test/CodeGen/AArch64/neon-simd-ldst-one.ll
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File diff suppressed because it is too large Load Diff

24
test/CodeGen/AArch64/neon-simd-ldst.ll
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@ -3,8 +3,8 @@
define void @test_ldstq_4v(i8* noalias %io, i32 %count) {
; CHECK-LABEL: test_ldstq_4v
; CHECK: ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0]
; CHECK: st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0]
; CHECK: ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]
; CHECK: st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]
entry:
%tobool62 = icmp eq i32 %count, 0
br i1 %tobool62, label %while.end, label %while.body
@ -31,8 +31,8 @@ declare void @llvm.arm.neon.vst4.v16i8(i8*, <16 x i8>, <16 x i8>, <16 x i8>, <16
define void @test_ldstq_3v(i8* noalias %io, i32 %count) {
; CHECK-LABEL: test_ldstq_3v
; CHECK: ld3 {v0.16b, v1.16b, v2.16b}, [x0]
; CHECK: st3 {v0.16b, v1.16b, v2.16b}, [x0]
; CHECK: ld3 { v0.16b, v1.16b, v2.16b }, [x0]
; CHECK: st3 { v0.16b, v1.16b, v2.16b }, [x0]
entry:
%tobool47 = icmp eq i32 %count, 0
br i1 %tobool47, label %while.end, label %while.body
@ -58,8 +58,8 @@ declare void @llvm.arm.neon.vst3.v16i8(i8*, <16 x i8>, <16 x i8>, <16 x i8>, i32
define void @test_ldstq_2v(i8* noalias %io, i32 %count) {
; CHECK-LABEL: test_ldstq_2v
; CHECK: ld2 {v0.16b, v1.16b}, [x0]
; CHECK: st2 {v0.16b, v1.16b}, [x0]
; CHECK: ld2 { v0.16b, v1.16b }, [x0]
; CHECK: st2 { v0.16b, v1.16b }, [x0]
entry:
%tobool22 = icmp eq i32 %count, 0
br i1 %tobool22, label %while.end, label %while.body
@ -84,8 +84,8 @@ declare void @llvm.arm.neon.vst2.v16i8(i8*, <16 x i8>, <16 x i8>, i32)
define void @test_ldst_4v(i8* noalias %io, i32 %count) {
; CHECK-LABEL: test_ldst_4v
; CHECK: ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0]
; CHECK: st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0]
; CHECK: ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]
; CHECK: st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]
entry:
%tobool42 = icmp eq i32 %count, 0
br i1 %tobool42, label %while.end, label %while.body
@ -112,8 +112,8 @@ declare void @llvm.arm.neon.vst4.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8
define void @test_ldst_3v(i8* noalias %io, i32 %count) {
; CHECK-LABEL: test_ldst_3v
; CHECK: ld3 {v0.8b, v1.8b, v2.8b}, [x0]
; CHECK: st3 {v0.8b, v1.8b, v2.8b}, [x0]
; CHECK: ld3 { v0.8b, v1.8b, v2.8b }, [x0]
; CHECK: st3 { v0.8b, v1.8b, v2.8b }, [x0]
entry:
%tobool32 = icmp eq i32 %count, 0
br i1 %tobool32, label %while.end, label %while.body
@ -139,8 +139,8 @@ declare void @llvm.arm.neon.vst3.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32)
define void @test_ldst_2v(i8* noalias %io, i32 %count) {
; CHECK-LABEL: test_ldst_2v
; CHECK: ld2 {v0.8b, v1.8b}, [x0]
; CHECK: st2 {v0.8b, v1.8b}, [x0]
; CHECK: ld2 { v0.8b, v1.8b }, [x0]
; CHECK: st2 { v0.8b, v1.8b }, [x0]
entry:
%tobool22 = icmp eq i32 %count, 0
br i1 %tobool22, label %while.end, label %while.body

56
test/CodeGen/AArch64/neon-simd-post-ldst-multi-elem.ll
View File

@ -3,7 +3,7 @@
;Check for a post-increment updating load.
define <4 x i16> @test_vld1_fx_update(i16** %ptr) nounwind {
; CHECK: test_vld1_fx_update
; CHECK: ld1 {v{{[0-9]+}}.4h}, [x{{[0-9]+|sp}}], #8
; CHECK: ld1 { v{{[0-9]+}}.4h }, [x{{[0-9]+|sp}}], #8
%A = load i16** %ptr
%tmp0 = bitcast i16* %A to i8*
%tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0, i32 2)
@ -15,7 +15,7 @@ define <4 x i16> @test_vld1_fx_update(i16** %ptr) nounwind {
;Check for a post-increment updating load with register increment.
define <2 x i32> @test_vld1_reg_update(i32** %ptr, i32 %inc) nounwind {
; CHECK: test_vld1_reg_update
; CHECK: ld1 {v{{[0-9]+}}.2s}, [x{{[0-9]+|sp}}], x{{[0-9]+}}
; CHECK: ld1 { v{{[0-9]+}}.2s }, [x{{[0-9]+|sp}}], x{{[0-9]+}}
%A = load i32** %ptr
%tmp0 = bitcast i32* %A to i8*
%tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0, i32 4)
@ -26,7 +26,7 @@ define <2 x i32> @test_vld1_reg_update(i32** %ptr, i32 %inc) nounwind {
define <2 x float> @test_vld2_fx_update(float** %ptr) nounwind {
; CHECK: test_vld2_fx_update
; CHECK: ld2 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, [x{{[0-9]+|sp}}], #16
; CHECK: ld2 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, [x{{[0-9]+|sp}}], #16
%A = load float** %ptr
%tmp0 = bitcast float* %A to i8*
%tmp1 = call { <2 x float>, <2 x float> } @llvm.arm.neon.vld2.v2f32(i8* %tmp0, i32 4)
@ -38,7 +38,7 @@ define <2 x float> @test_vld2_fx_update(float** %ptr) nounwind {
define <16 x i8> @test_vld2_reg_update(i8** %ptr, i32 %inc) nounwind {
; CHECK: test_vld2_reg_update
; CHECK: ld2 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [x{{[0-9]+|sp}}], x{{[0-9]+}}
; CHECK: ld2 { v{{[0-9]+}}.16b, v{{[0-9]+}}.16b }, [x{{[0-9]+|sp}}], x{{[0-9]+}}
%A = load i8** %ptr
%tmp0 = call { <16 x i8>, <16 x i8> } @llvm.arm.neon.vld2.v16i8(i8* %A, i32 1)
%tmp1 = extractvalue { <16 x i8>, <16 x i8> } %tmp0, 0
@ -49,7 +49,7 @@ define <16 x i8> @test_vld2_reg_update(i8** %ptr, i32 %inc) nounwind {
define <4 x i32> @test_vld3_fx_update(i32** %ptr) nounwind {
; CHECK: test_vld3_fx_update
; CHECK: ld3 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [x{{[0-9]+|sp}}], #48
; CHECK: ld3 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [x{{[0-9]+|sp}}], #48
%A = load i32** %ptr
%tmp0 = bitcast i32* %A to i8*
%tmp1 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld3.v4i32(i8* %tmp0, i32 4)
@ -61,7 +61,7 @@ define <4 x i32> @test_vld3_fx_update(i32** %ptr) nounwind {
define <4 x i16> @test_vld3_reg_update(i16** %ptr, i32 %inc) nounwind {
; CHECK: test_vld3_reg_update
; CHECK: ld3 {v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h}, [x{{[0-9]+|sp}}], x{{[0-9]+}}
; CHECK: ld3 { v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h }, [x{{[0-9]+|sp}}], x{{[0-9]+}}
%A = load i16** %ptr
%tmp0 = bitcast i16* %A to i8*
%tmp1 = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld3.v4i16(i8* %tmp0, i32 2)
@ -73,7 +73,7 @@ define <4 x i16> @test_vld3_reg_update(i16** %ptr, i32 %inc) nounwind {
define <8 x i16> @test_vld4_fx_update(i16** %ptr) nounwind {
; CHECK: test_vld4_fx_update
; CHECK: ld4 {v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h}, [x{{[0-9]+|sp}}], #64
; CHECK: ld4 { v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h }, [x{{[0-9]+|sp}}], #64
%A = load i16** %ptr
%tmp0 = bitcast i16* %A to i8*
%tmp1 = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld4.v8i16(i8* %tmp0, i32 8)
@ -85,7 +85,7 @@ define <8 x i16> @test_vld4_fx_update(i16** %ptr) nounwind {
define <8 x i8> @test_vld4_reg_update(i8** %ptr, i32 %inc) nounwind {
; CHECK: test_vld4_reg_update
; CHECK: ld4 {v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b}, [x{{[0-9]+|sp}}], x{{[0-9]+}}
; CHECK: ld4 { v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b }, [x{{[0-9]+|sp}}], x{{[0-9]+}}
%A = load i8** %ptr
%tmp0 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld4.v8i8(i8* %A, i32 1)
%tmp1 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %tmp0, 0
@ -96,7 +96,7 @@ define <8 x i8> @test_vld4_reg_update(i8** %ptr, i32 %inc) nounwind {
define void @test_vst1_fx_update(float** %ptr, <2 x float> %B) nounwind {
; CHECK: test_vst1_fx_update
; CHECK: st1 {v{{[0-9]+}}.2s}, [{{x[0-9]+|sp}}], #8
; CHECK: st1 { v{{[0-9]+}}.2s }, [{{x[0-9]+|sp}}], #8
%A = load float** %ptr
%tmp0 = bitcast float* %A to i8*
call void @llvm.arm.neon.vst1.v2f32(i8* %tmp0, <2 x float> %B, i32 4)
@ -107,7 +107,7 @@ define void @test_vst1_fx_update(float** %ptr, <2 x float> %B) nounwind {
define void @test_vst1_reg_update(i16** %ptr, <8 x i16> %B, i32 %inc) nounwind {
; CHECK: test_vst1_reg_update
; CHECK: st1 {v{{[0-9]+}}.8h}, [{{x[0-9]+|sp}}], x{{[0-9]+}}
; CHECK: st1 { v{{[0-9]+}}.8h }, [{{x[0-9]+|sp}}], x{{[0-9]+}}
%A = load i16** %ptr
%tmp0 = bitcast i16* %A to i8*
call void @llvm.arm.neon.vst1.v8i16(i8* %tmp0, <8 x i16> %B, i32 2)
@ -118,7 +118,7 @@ define void @test_vst1_reg_update(i16** %ptr, <8 x i16> %B, i32 %inc) nounwind {
define void @test_vst2_fx_update(i64** %ptr, <1 x i64> %B) nounwind {
; CHECK: test_vst2_fx_update
; CHECK: st1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d}, [{{x[0-9]+|sp}}], #16
; CHECK: st1 { v{{[0-9]+}}.1d, v{{[0-9]+}}.1d }, [{{x[0-9]+|sp}}], #16
%A = load i64** %ptr
%tmp0 = bitcast i64* %A to i8*
call void @llvm.arm.neon.vst2.v1i64(i8* %tmp0, <1 x i64> %B, <1 x i64> %B, i32 8)
@ -129,7 +129,7 @@ define void @test_vst2_fx_update(i64** %ptr, <1 x i64> %B) nounwind {
define void @test_vst2_reg_update(i8** %ptr, <8 x i8> %B, i32 %inc) nounwind {
; CHECK: test_vst2_reg_update
; CHECK: st2 {v{{[0-9]+}}.8b, v{{[0-9]+}}.8b}, [{{x[0-9]+|sp}}], x{{[0-9]+}}
; CHECK: st2 { v{{[0-9]+}}.8b, v{{[0-9]+}}.8b }, [{{x[0-9]+|sp}}], x{{[0-9]+}}
%A = load i8** %ptr
call void @llvm.arm.neon.vst2.v8i8(i8* %A, <8 x i8> %B, <8 x i8> %B, i32 4)
%tmp0 = getelementptr i8* %A, i32 %inc
@ -139,7 +139,7 @@ define void @test_vst2_reg_update(i8** %ptr, <8 x i8> %B, i32 %inc) nounwind {
define void @test_vst3_fx_update(i32** %ptr, <2 x i32> %B) nounwind {
; CHECK: test_vst3_fx_update
; CHECK: st3 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, [{{x[0-9]+|sp}}], #24
; CHECK: st3 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, [{{x[0-9]+|sp}}], #24
%A = load i32** %ptr
%tmp0 = bitcast i32* %A to i8*
call void @llvm.arm.neon.vst3.v2i32(i8* %tmp0, <2 x i32> %B, <2 x i32> %B, <2 x i32> %B, i32 4)
@ -150,7 +150,7 @@ define void @test_vst3_fx_update(i32** %ptr, <2 x i32> %B) nounwind {
define void @test_vst3_reg_update(i16** %ptr, <8 x i16> %B, i32 %inc) nounwind {
; CHECK: test_vst3_reg_update
; CHECK: st3 {v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h}, [{{x[0-9]+|sp}}], x{{[0-9]+}}
; CHECK: st3 { v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h }, [{{x[0-9]+|sp}}], x{{[0-9]+}}
%A = load i16** %ptr
%tmp0 = bitcast i16* %A to i8*
call void @llvm.arm.neon.vst3.v8i16(i8* %tmp0, <8 x i16> %B, <8 x i16> %B, <8 x i16> %B, i32 2)
@ -161,7 +161,7 @@ define void @test_vst3_reg_update(i16** %ptr, <8 x i16> %B, i32 %inc) nounwind {
define void @test_vst4_fx_update(float** %ptr, <4 x float> %B) nounwind {
; CHECK: test_vst4_fx_update
; CHECK: st4 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [{{x[0-9]+|sp}}], #64
; CHECK: st4 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [{{x[0-9]+|sp}}], #64
%A = load float** %ptr
%tmp0 = bitcast float* %A to i8*
call void @llvm.arm.neon.vst4.v4f32(i8* %tmp0, <4 x float> %B, <4 x float> %B, <4 x float> %B, <4 x float> %B, i32 4)
@ -172,7 +172,7 @@ define void @test_vst4_fx_update(float** %ptr, <4 x float> %B) nounwind {
define void @test_vst4_reg_update(i8** %ptr, <8 x i8> %B, i32 %inc) nounwind {
; CHECK: test_vst4_reg_update
; CHECK: st4 {v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b}, [{{x[0-9]+|sp}}], x{{[0-9]+}}
; CHECK: st4 { v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b }, [{{x[0-9]+|sp}}], x{{[0-9]+}}
%A = load i8** %ptr
call void @llvm.arm.neon.vst4.v8i8(i8* %A, <8 x i8> %B, <8 x i8> %B, <8 x i8> %B, <8 x i8> %B, i32 1)
%tmp0 = getelementptr i8* %A, i32 %inc
@ -201,7 +201,7 @@ declare void @llvm.arm.neon.vst4.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8
define <16 x i8> @test_vld1x2_fx_update(i8* %a, i8** %ptr) {
; CHECK: test_vld1x2_fx_update
; CHECK: ld1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [x{{[0-9]+|sp}}], #32
; CHECK: ld1 { v{{[0-9]+}}.16b, v{{[0-9]+}}.16b }, [x{{[0-9]+|sp}}], #32
%1 = call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.vld1x2.v16i8(i8* %a, i32 1)
%2 = extractvalue { <16 x i8>, <16 x i8> } %1, 0
%tmp1 = getelementptr i8* %a, i32 32
@ -211,7 +211,7 @@ define <16 x i8> @test_vld1x2_fx_update(i8* %a, i8** %ptr) {
define <8 x i16> @test_vld1x2_reg_update(i16* %a, i16** %ptr, i32 %inc) {
; CHECK: test_vld1x2_reg_update
; CHECK: ld1 {v{{[0-9]+}}.8h, v{{[0-9]+}}.8h}, [x{{[0-9]+|sp}}], x{{[0-9]+}}
; CHECK: ld1 { v{{[0-9]+}}.8h, v{{[0-9]+}}.8h }, [x{{[0-9]+|sp}}], x{{[0-9]+}}
%1 = bitcast i16* %a to i8*
%2 = tail call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.vld1x2.v8i16(i8* %1, i32 2)
%3 = extractvalue { <8 x i16>, <8 x i16> } %2, 0
@ -222,7 +222,7 @@ define <8 x i16> @test_vld1x2_reg_update(i16* %a, i16** %ptr, i32 %inc) {
define <2 x i64> @test_vld1x3_fx_update(i64* %a, i64** %ptr) {
; CHECK: test_vld1x3_fx_update
; CHECK: ld1 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d}, [x{{[0-9]+|sp}}], #48
; CHECK: ld1 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [x{{[0-9]+|sp}}], #48
%1 = bitcast i64* %a to i8*
%2 = tail call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.vld1x3.v2i64(i8* %1, i32 8)
%3 = extractvalue { <2 x i64>, <2 x i64>, <2 x i64> } %2, 0
@ -233,7 +233,7 @@ define <2 x i64> @test_vld1x3_fx_update(i64* %a, i64** %ptr) {
define <8 x i16> @test_vld1x3_reg_update(i16* %a, i16** %ptr, i32 %inc) {
; CHECK: test_vld1x3_reg_update
; CHECK: ld1 {v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h}, [x{{[0-9]+|sp}}], x{{[0-9]+}}
; CHECK: ld1 { v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h }, [x{{[0-9]+|sp}}], x{{[0-9]+}}
%1 = bitcast i16* %a to i8*
%2 = tail call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.vld1x3.v8i16(i8* %1, i32 2)
%3 = extractvalue { <8 x i16>, <8 x i16>, <8 x i16> } %2, 0
@ -244,7 +244,7 @@ define <8 x i16> @test_vld1x3_reg_update(i16* %a, i16** %ptr, i32 %inc) {
define <4 x float> @test_vld1x4_fx_update(float* %a, float** %ptr) {
; CHECK: test_vld1x4_fx_update
; CHECK: ld1 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [x{{[0-9]+|sp}}], #64
; CHECK: ld1 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [x{{[0-9]+|sp}}], #64
%1 = bitcast float* %a to i8*
%2 = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.vld1x4.v4f32(i8* %1, i32 4)
%3 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %2, 0
@ -255,7 +255,7 @@ define <4 x float> @test_vld1x4_fx_update(float* %a, float** %ptr) {
define <8 x i8> @test_vld1x4_reg_update(i8* readonly %a, i8** %ptr, i32 %inc) #0 {
; CHECK: test_vld1x4_reg_update
; CHECK: ld1 {v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b}, [x{{[0-9]+|sp}}], x{{[0-9]+}}
; CHECK: ld1 { v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b }, [x{{[0-9]+|sp}}], x{{[0-9]+}}
%1 = tail call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.vld1x4.v8i8(i8* %a, i32 1)
%2 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 0
%tmp1 = getelementptr i8* %a, i32 %inc
@ -265,7 +265,7 @@ define <8 x i8> @test_vld1x4_reg_update(i8* readonly %a, i8** %ptr, i32 %inc) #0
define void @test_vst1x2_fx_update(i8* %a, [2 x <16 x i8>] %b.coerce, i8** %ptr) #2 {
; CHECK: test_vst1x2_fx_update
; CHECK: st1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [x{{[0-9]+|sp}}], #32
; CHECK: st1 { v{{[0-9]+}}.16b, v{{[0-9]+}}.16b }, [x{{[0-9]+|sp}}], #32
%1 = extractvalue [2 x <16 x i8>] %b.coerce, 0
%2 = extractvalue [2 x <16 x i8>] %b.coerce, 1
tail call void @llvm.aarch64.neon.vst1x2.v16i8(i8* %a, <16 x i8> %1, <16 x i8> %2, i32 1)
@ -276,7 +276,7 @@ define void @test_vst1x2_fx_update(i8* %a, [2 x <16 x i8>] %b.coerce, i8** %ptr)
define void @test_vst1x2_reg_update(i16* %a, [2 x <8 x i16>] %b.coerce, i16** %ptr, i32 %inc) #2 {
; CHECK: test_vst1x2_reg_update
; CHECK: st1 {v{{[0-9]+}}.8h, v{{[0-9]+}}.8h}, [x{{[0-9]+|sp}}], x{{[0-9]+}}
; CHECK: st1 { v{{[0-9]+}}.8h, v{{[0-9]+}}.8h }, [x{{[0-9]+|sp}}], x{{[0-9]+}}
%1 = extractvalue [2 x <8 x i16>] %b.coerce, 0
%2 = extractvalue [2 x <8 x i16>] %b.coerce, 1
%3 = bitcast i16* %a to i8*
@ -288,7 +288,7 @@ define void @test_vst1x2_reg_update(i16* %a, [2 x <8 x i16>] %b.coerce, i16** %p
define void @test_vst1x3_fx_update(i32* %a, [3 x <2 x i32>] %b.coerce, i32** %ptr) #2 {
; CHECK: test_vst1x3_fx_update
; CHECK: st1 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, [x{{[0-9]+|sp}}], #24
; CHECK: st1 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, [x{{[0-9]+|sp}}], #24
%1 = extractvalue [3 x <2 x i32>] %b.coerce, 0
%2 = extractvalue [3 x <2 x i32>] %b.coerce, 1
%3 = extractvalue [3 x <2 x i32>] %b.coerce, 2
@ -301,7 +301,7 @@ define void @test_vst1x3_fx_update(i32* %a, [3 x <2 x i32>] %b.coerce, i32** %pt
define void @test_vst1x3_reg_update(i64* %a, [3 x <1 x i64>] %b.coerce, i64** %ptr, i32 %inc) #2 {
; CHECK: test_vst1x3_reg_update
; CHECK: st1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d}, [x{{[0-9]+|sp}}], x{{[0-9]+}}
; CHECK: st1 { v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d }, [x{{[0-9]+|sp}}], x{{[0-9]+}}
%1 = extractvalue [3 x <1 x i64>] %b.coerce, 0
%2 = extractvalue [3 x <1 x i64>] %b.coerce, 1
%3 = extractvalue [3 x <1 x i64>] %b.coerce, 2
@ -314,7 +314,7 @@ define void @test_vst1x3_reg_update(i64* %a, [3 x <1 x i64>] %b.coerce, i64** %p
define void @test_vst1x4_fx_update(float* %a, [4 x <4 x float>] %b.coerce, float** %ptr) #2 {
; CHECK: test_vst1x4_fx_update
; CHECK: st1 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [x{{[0-9]+|sp}}], #64
; CHECK: st1 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [x{{[0-9]+|sp}}], #64
%1 = extractvalue [4 x <4 x float>] %b.coerce, 0
%2 = extractvalue [4 x <4 x float>] %b.coerce, 1
%3 = extractvalue [4 x <4 x float>] %b.coerce, 2
@ -328,7 +328,7 @@ define void @test_vst1x4_fx_update(float* %a, [4 x <4 x float>] %b.coerce, float
define void @test_vst1x4_reg_update(double* %a, [4 x <2 x double>] %b.coerce, double** %ptr, i32 %inc) #2 {
; CHECK: test_vst1x4_reg_update
; CHECK: st1 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d}, [x{{[0-9]+|sp}}], x{{[0-9]+}}
; CHECK: st1 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [x{{[0-9]+|sp}}], x{{[0-9]+}}
%1 = extractvalue [4 x <2 x double>] %b.coerce, 0
%2 = extractvalue [4 x <2 x double>] %b.coerce, 1
%3 = extractvalue [4 x <2 x double>] %b.coerce, 2

36
test/CodeGen/AArch64/neon-simd-post-ldst-one.ll
View File

@ -2,7 +2,7 @@
define { [2 x <16 x i8>] } @test_vld2q_dup_fx_update(i8* %a, i8** %ptr) {
; CHECK-LABEL: test_vld2q_dup_fx_update
; CHECK: ld2r {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [x{{[0-9]+|sp}}], #2
; CHECK: ld2r { v{{[0-9]+}}.16b, v{{[0-9]+}}.16b }, [x{{[0-9]+|sp}}], #2
%1 = tail call { <16 x i8>, <16 x i8> } @llvm.arm.neon.vld2lane.v16i8(i8* %a, <16 x i8> undef, <16 x i8> undef, i32 0, i32 1)
%2 = extractvalue { <16 x i8>, <16 x i8> } %1, 0
%3 = shufflevector <16 x i8> %2, <16 x i8> undef, <16 x i32> zeroinitializer
@ -17,7 +17,7 @@ define { [2 x <16 x i8>] } @test_vld2q_dup_fx_update(i8* %a, i8** %ptr) {
define { [2 x <4 x i32>] } @test_vld2q_dup_reg_update(i32* %a, i32** %ptr, i32 %inc) {
; CHECK-LABEL: test_vld2q_dup_reg_update
; CHECK: ld2r {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [x{{[0-9]+|sp}}], x{{[0-9]+}}
; CHECK: ld2r { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [x{{[0-9]+|sp}}], x{{[0-9]+}}
%1 = bitcast i32* %a to i8*
%2 = tail call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2lane.v4i32(i8* %1, <4 x i32> undef, <4 x i32> undef, i32 0, i32 4)
%3 = extractvalue { <4 x i32>, <4 x i32> } %2, 0
@ -33,7 +33,7 @@ define { [2 x <4 x i32>] } @test_vld2q_dup_reg_update(i32* %a, i32** %ptr, i32 %
define { [3 x <4 x i16>] } @test_vld3_dup_fx_update(i16* %a, i16** %ptr) {
; CHECK-LABEL: test_vld3_dup_fx_update
; CHECK: ld3r {v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h}, [x{{[0-9]+|sp}}], #6
; CHECK: ld3r { v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h }, [x{{[0-9]+|sp}}], #6
%1 = bitcast i16* %a to i8*
%2 = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld3lane.v4i16(i8* %1, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 2)
%3 = extractvalue { <4 x i16>, <4 x i16>, <4 x i16> } %2, 0
@ -52,7 +52,7 @@ define { [3 x <4 x i16>] } @test_vld3_dup_fx_update(i16* %a, i16** %ptr) {
define { [3 x <8 x i8>] } @test_vld3_dup_reg_update(i8* %a, i8** %ptr, i32 %inc) {
; CHECK-LABEL: test_vld3_dup_reg_update
; CHECK: ld3r {v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b}, [x{{[0-9]+|sp}}], x{{[0-9]+}}
; CHECK: ld3r { v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b }, [x{{[0-9]+|sp}}], x{{[0-9]+}}
%1 = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld3lane.v8i8(i8* %a, <8 x i8> undef, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1)
%2 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %1, 0
%3 = shufflevector <8 x i8> %2, <8 x i8> undef, <8 x i32> zeroinitializer
@ -70,7 +70,7 @@ define { [3 x <8 x i8>] } @test_vld3_dup_reg_update(i8* %a, i8** %ptr, i32 %inc)
define { [4 x <2 x i32>] } @test_vld4_dup_fx_update(i32* %a, i32** %ptr) #0 {
; CHECK-LABEL: test_vld4_dup_fx_update
; CHECK: ld4r {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, [x{{[0-9]+|sp}}], #16
; CHECK: ld4r { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, [x{{[0-9]+|sp}}], #16
%1 = bitcast i32* %a to i8*
%2 = tail call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld4lane.v2i32(i8* %1, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, i32 0, i32 4)
%3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %2, 0
@ -92,7 +92,7 @@ define { [4 x <2 x i32>] } @test_vld4_dup_fx_update(i32* %a, i32** %ptr) #0 {
define { [4 x <2 x double>] } @test_vld4_dup_reg_update(double* %a, double** %ptr, i32 %inc) {
; CHECK-LABEL: test_vld4_dup_reg_update
; CHECK: ld4r {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d}, [x{{[0-9]+|sp}}], x{{[0-9]+}}
; CHECK: ld4r { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [x{{[0-9]+|sp}}], x{{[0-9]+}}
%1 = bitcast double* %a to i8*
%2 = tail call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.arm.neon.vld4lane.v2f64(i8* %1, <2 x double> undef, <2 x double> undef, <2 x double> undef, <2 x double> undef, i32 0, i32 8)
%3 = extractvalue { <2 x double>, <2 x double>, <2 x double>, <2 x double> } %2, 0
@ -114,7 +114,7 @@ define { [4 x <2 x double>] } @test_vld4_dup_reg_update(double* %a, double** %pt
define { [2 x <8 x i8>] } @test_vld2_lane_fx_update(i8* %a, [2 x <8 x i8>] %b, i8** %ptr) {
; CHECK-LABEL: test_vld2_lane_fx_update
; CHECK: ld2 {v{{[0-9]+}}.b, v{{[0-9]+}}.b}[7], [x{{[0-9]+|sp}}], #2
; CHECK: ld2 { v{{[0-9]+}}.b, v{{[0-9]+}}.b }[7], [x{{[0-9]+|sp}}], #2
%1 = extractvalue [2 x <8 x i8>] %b, 0
%2 = extractvalue [2 x <8 x i8>] %b, 1
%3 = tail call { <8 x i8>, <8 x i8> } @llvm.arm.neon.vld2lane.v8i8(i8* %a, <8 x i8> %1, <8 x i8> %2, i32 7, i32 1)
@ -129,7 +129,7 @@ define { [2 x <8 x i8>] } @test_vld2_lane_fx_update(i8* %a, [2 x <8 x i8>] %b,
define { [2 x <8 x i8>] } @test_vld2_lane_reg_update(i8* %a, [2 x <8 x i8>] %b, i8** %ptr, i32 %inc) {
; CHECK-LABEL: test_vld2_lane_reg_update
; CHECK: ld2 {v{{[0-9]+}}.b, v{{[0-9]+}}.b}[6], [x{{[0-9]+|sp}}], x{{[0-9]+}}
; CHECK: ld2 { v{{[0-9]+}}.b, v{{[0-9]+}}.b }[6], [x{{[0-9]+|sp}}], x{{[0-9]+}}
%1 = extractvalue [2 x <8 x i8>] %b, 0
%2 = extractvalue [2 x <8 x i8>] %b, 1
%3 = tail call { <8 x i8>, <8 x i8> } @llvm.arm.neon.vld2lane.v8i8(i8* %a, <8 x i8> %1, <8 x i8> %2, i32 6, i32 1)
@ -144,7 +144,7 @@ define { [2 x <8 x i8>] } @test_vld2_lane_reg_update(i8* %a, [2 x <8 x i8>] %b,
define { [3 x <2 x float>] } @test_vld3_lane_fx_update(float* %a, [3 x <2 x float>] %b, float** %ptr) {
; CHECK-LABEL: test_vld3_lane_fx_update
; CHECK: ld3 {v{{[0-9]+}}.s, v{{[0-9]+}}.s, v{{[0-9]+}}.s}[1], [x{{[0-9]+|sp}}], #12
; CHECK: ld3 { v{{[0-9]+}}.s, v{{[0-9]+}}.s, v{{[0-9]+}}.s }[1], [x{{[0-9]+|sp}}], #12
%1 = extractvalue [3 x <2 x float>] %b, 0
%2 = extractvalue [3 x <2 x float>] %b, 1
%3 = extractvalue [3 x <2 x float>] %b, 2
@ -163,7 +163,7 @@ define { [3 x <2 x float>] } @test_vld3_lane_fx_update(float* %a, [3 x <2 x floa
define { [3 x <4 x i16>] } @test_vld3_lane_reg_update(i16* %a, [3 x <4 x i16>] %b, i16** %ptr, i32 %inc) {
; CHECK-LABEL: test_vld3_lane_reg_update
; CHECK: ld3 {v{{[0-9]+}}.h, v{{[0-9]+}}.h, v{{[0-9]+}}.h}[3], [x{{[0-9]+|sp}}], x{{[0-9]+}}
; CHECK: ld3 { v{{[0-9]+}}.h, v{{[0-9]+}}.h, v{{[0-9]+}}.h }[3], [x{{[0-9]+|sp}}], x{{[0-9]+}}
%1 = extractvalue [3 x <4 x i16>] %b, 0
%2 = extractvalue [3 x <4 x i16>] %b, 1
%3 = extractvalue [3 x <4 x i16>] %b, 2
@ -182,7 +182,7 @@ define { [3 x <4 x i16>] } @test_vld3_lane_reg_update(i16* %a, [3 x <4 x i16>] %
define { [4 x <2 x i32>] } @test_vld4_lane_fx_update(i32* readonly %a, [4 x <2 x i32>] %b, i32** %ptr) {
; CHECK-LABEL: test_vld4_lane_fx_update
; CHECK: ld4 {v{{[0-9]+}}.s, v{{[0-9]+}}.s, v{{[0-9]+}}.s, v{{[0-9]+}}.s}[1], [x{{[0-9]+|sp}}], #16
; CHECK: ld4 { v{{[0-9]+}}.s, v{{[0-9]+}}.s, v{{[0-9]+}}.s, v{{[0-9]+}}.s }[1], [x{{[0-9]+|sp}}], #16
%1 = extractvalue [4 x <2 x i32>] %b, 0
%2 = extractvalue [4 x <2 x i32>] %b, 1
%3 = extractvalue [4 x <2 x i32>] %b, 2
@ -204,7 +204,7 @@ define { [4 x <2 x i32>] } @test_vld4_lane_fx_update(i32* readonly %a, [4 x <2 x
define { [4 x <2 x double>] } @test_vld4_lane_reg_update(double* readonly %a, [4 x <2 x double>] %b, double** %ptr, i32 %inc) {
; CHECK-LABEL: test_vld4_lane_reg_update
; CHECK: ld4 {v{{[0-9]+}}.d, v{{[0-9]+}}.d, v{{[0-9]+}}.d, v{{[0-9]+}}.d}[1], [x{{[0-9]+|sp}}], x{{[0-9]+}}
; CHECK: ld4 { v{{[0-9]+}}.d, v{{[0-9]+}}.d, v{{[0-9]+}}.d, v{{[0-9]+}}.d }[1], [x{{[0-9]+|sp}}], x{{[0-9]+}}
%1 = extractvalue [4 x <2 x double>] %b, 0
%2 = extractvalue [4 x <2 x double>] %b, 1
%3 = extractvalue [4 x <2 x double>] %b, 2
@ -226,7 +226,7 @@ define { [4 x <2 x double>] } @test_vld4_lane_reg_update(double* readonly %a, [4
define void @test_vst2_lane_fx_update(i8* %a, [2 x <8 x i8>] %b, i8** %ptr) {
; CHECK-LABEL: test_vst2_lane_fx_update
; CHECK: st2 {v{{[0-9]+}}.b, v{{[0-9]+}}.b}[7], [x{{[0-9]+|sp}}], #2
; CHECK: st2 { v{{[0-9]+}}.b, v{{[0-9]+}}.b }[7], [x{{[0-9]+|sp}}], #2
%1 = extractvalue [2 x <8 x i8>] %b, 0
%2 = extractvalue [2 x <8 x i8>] %b, 1
call void @llvm.arm.neon.vst2lane.v8i8(i8* %a, <8 x i8> %1, <8 x i8> %2, i32 7, i32 1)
@ -237,7 +237,7 @@ define void @test_vst2_lane_fx_update(i8* %a, [2 x <8 x i8>] %b, i8** %ptr) {
define void @test_vst2_lane_reg_update(i32* %a, [2 x <2 x i32>] %b.coerce, i32** %ptr, i32 %inc) {
; CHECK-LABEL: test_vst2_lane_reg_update
; CHECK: st2 {v{{[0-9]+}}.s, v{{[0-9]+}}.s}[1], [x{{[0-9]+|sp}}], x{{[0-9]+}}
; CHECK: st2 { v{{[0-9]+}}.s, v{{[0-9]+}}.s }[1], [x{{[0-9]+|sp}}], x{{[0-9]+}}
%1 = extractvalue [2 x <2 x i32>] %b.coerce, 0
%2 = extractvalue [2 x <2 x i32>] %b.coerce, 1
%3 = bitcast i32* %a to i8*
@ -249,7 +249,7 @@ define void @test_vst2_lane_reg_update(i32* %a, [2 x <2 x i32>] %b.coerce, i32**
define void @test_vst3_lane_fx_update(float* %a, [3 x <4 x float>] %b, float** %ptr) {
; CHECK-LABEL: test_vst3_lane_fx_update
; CHECK: st3 {v{{[0-9]+}}.s, v{{[0-9]+}}.s, v{{[0-9]+}}.s}[3], [x{{[0-9]+|sp}}], #12
; CHECK: st3 { v{{[0-9]+}}.s, v{{[0-9]+}}.s, v{{[0-9]+}}.s }[3], [x{{[0-9]+|sp}}], #12
%1 = extractvalue [3 x <4 x float>] %b, 0
%2 = extractvalue [3 x <4 x float>] %b, 1
%3 = extractvalue [3 x <4 x float>] %b, 2
@ -263,7 +263,7 @@ define void @test_vst3_lane_fx_update(float* %a, [3 x <4 x float>] %b, float** %
; Function Attrs: nounwind
define void @test_vst3_lane_reg_update(i16* %a, [3 x <4 x i16>] %b, i16** %ptr, i32 %inc) {
; CHECK-LABEL: test_vst3_lane_reg_update
; CHECK: st3 {v{{[0-9]+}}.h, v{{[0-9]+}}.h, v{{[0-9]+}}.h}[3], [x{{[0-9]+|sp}}], x{{[0-9]+}}
; CHECK: st3 { v{{[0-9]+}}.h, v{{[0-9]+}}.h, v{{[0-9]+}}.h }[3], [x{{[0-9]+|sp}}], x{{[0-9]+}}
%1 = extractvalue [3 x <4 x i16>] %b, 0
%2 = extractvalue [3 x <4 x i16>] %b, 1
%3 = extractvalue [3 x <4 x i16>] %b, 2
@ -276,7 +276,7 @@ define void @test_vst3_lane_reg_update(i16* %a, [3 x <4 x i16>] %b, i16** %ptr,
define void @test_vst4_lane_fx_update(double* %a, [4 x <2 x double>] %b.coerce, double** %ptr) {
; CHECK-LABEL: test_vst4_lane_fx_update
; CHECK: st4 {v{{[0-9]+}}.d, v{{[0-9]+}}.d, v{{[0-9]+}}.d, v{{[0-9]+}}.d}[1], [x{{[0-9]+|sp}}], #32
; CHECK: st4 { v{{[0-9]+}}.d, v{{[0-9]+}}.d, v{{[0-9]+}}.d, v{{[0-9]+}}.d }[1], [x{{[0-9]+|sp}}], #32
%1 = extractvalue [4 x <2 x double>] %b.coerce, 0
%2 = extractvalue [4 x <2 x double>] %b.coerce, 1
%3 = extractvalue [4 x <2 x double>] %b.coerce, 2
@ -291,7 +291,7 @@ define void @test_vst4_lane_fx_update(double* %a, [4 x <2 x double>] %b.coerce,
define void @test_vst4_lane_reg_update(float* %a, [4 x <2 x float>] %b.coerce, float** %ptr, i32 %inc) {
; CHECK-LABEL: test_vst4_lane_reg_update
; CHECK: st4 {v{{[0-9]+}}.s, v{{[0-9]+}}.s, v{{[0-9]+}}.s, v{{[0-9]+}}.s}[1], [x{{[0-9]+|sp}}], x{{[0-9]+}}
; CHECK: st4 { v{{[0-9]+}}.s, v{{[0-9]+}}.s, v{{[0-9]+}}.s, v{{[0-9]+}}.s }[1], [x{{[0-9]+|sp}}], x{{[0-9]+}}
%1 = extractvalue [4 x <2 x float>] %b.coerce, 0
%2 = extractvalue [4 x <2 x float>] %b.coerce, 1
%3 = extractvalue [4 x <2 x float>] %b.coerce, 2

144
test/CodeGen/AArch64/neon-simd-tbl.ll
View File

@ -37,7 +37,7 @@ declare <8 x i8> @llvm.aarch64.neon.vtbl3.v8i8(<16 x i8>, <16 x i8>, <16 x i8>,
define <8 x i8> @test_vtbl1_s8(<8 x i8> %a, <8 x i8> %b) {
; CHECK: test_vtbl1_s8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%vtbl1.i = shufflevector <8 x i8> %a, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%vtbl11.i = tail call <8 x i8> @llvm.aarch64.neon.vtbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %b)
@ -46,7 +46,7 @@ entry:
define <8 x i8> @test_vqtbl1_s8(<16 x i8> %a, <8 x i8> %b) {
; CHECK: test_vqtbl1_s8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%vtbl1.i = tail call <8 x i8> @llvm.aarch64.neon.vtbl1.v8i8(<16 x i8> %a, <8 x i8> %b)
ret <8 x i8> %vtbl1.i
@ -54,7 +54,7 @@ entry:
define <8 x i8> @test_vtbl2_s8([2 x <8 x i8>] %a.coerce, <8 x i8> %b) {
; CHECK: test_vtbl2_s8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__a.coerce.fca.0.extract.i = extractvalue [2 x <8 x i8>] %a.coerce, 0
%__a.coerce.fca.1.extract.i = extractvalue [2 x <8 x i8>] %a.coerce, 1
@ -65,7 +65,7 @@ entry:
define <8 x i8> @test_vqtbl2_s8([2 x <16 x i8>] %a.coerce, <8 x i8> %b) {
; CHECK: test_vqtbl2_s8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__a.coerce.fca.0.extract.i = extractvalue [2 x <16 x i8>] %a.coerce, 0
%__a.coerce.fca.1.extract.i = extractvalue [2 x <16 x i8>] %a.coerce, 1
@ -75,7 +75,7 @@ entry:
define <8 x i8> @test_vtbl3_s8([3 x <8 x i8>] %a.coerce, <8 x i8> %b) {
; CHECK: test_vtbl3_s8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__a.coerce.fca.0.extract.i = extractvalue [3 x <8 x i8>] %a.coerce, 0
%__a.coerce.fca.1.extract.i = extractvalue [3 x <8 x i8>] %a.coerce, 1
@ -88,7 +88,7 @@ entry:
define <8 x i8> @test_vqtbl3_s8([3 x <16 x i8>] %a.coerce, <8 x i8> %b) {
; CHECK: test_vqtbl3_s8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__a.coerce.fca.0.extract.i = extractvalue [3 x <16 x i8>] %a.coerce, 0
%__a.coerce.fca.1.extract.i = extractvalue [3 x <16 x i8>] %a.coerce, 1
@ -99,7 +99,7 @@ entry:
define <8 x i8> @test_vtbl4_s8([4 x <8 x i8>] %a.coerce, <8 x i8> %b) {
; CHECK: test_vtbl4_s8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__a.coerce.fca.0.extract.i = extractvalue [4 x <8 x i8>] %a.coerce, 0
%__a.coerce.fca.1.extract.i = extractvalue [4 x <8 x i8>] %a.coerce, 1
@ -113,7 +113,7 @@ entry:
define <8 x i8> @test_vqtbl4_s8([4 x <16 x i8>] %a.coerce, <8 x i8> %b) {
; CHECK: test_vqtbl4_s8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__a.coerce.fca.0.extract.i = extractvalue [4 x <16 x i8>] %a.coerce, 0
%__a.coerce.fca.1.extract.i = extractvalue [4 x <16 x i8>] %a.coerce, 1
@ -125,7 +125,7 @@ entry:
define <16 x i8> @test_vqtbl1q_s8(<16 x i8> %a, <16 x i8> %b) {
; CHECK: test_vqtbl1q_s8:
; CHECK: tbl {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.16b
; CHECK: tbl {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b
entry:
%vtbl1.i = tail call <16 x i8> @llvm.aarch64.neon.vtbl1.v16i8(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %vtbl1.i
@ -133,7 +133,7 @@ entry:
define <16 x i8> @test_vqtbl2q_s8([2 x <16 x i8>] %a.coerce, <16 x i8> %b) {
; CHECK: test_vqtbl2q_s8:
; CHECK: tbl {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b
; CHECK: tbl {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b
entry:
%__a.coerce.fca.0.extract.i = extractvalue [2 x <16 x i8>] %a.coerce, 0
%__a.coerce.fca.1.extract.i = extractvalue [2 x <16 x i8>] %a.coerce, 1
@ -143,7 +143,7 @@ entry:
define <16 x i8> @test_vqtbl3q_s8([3 x <16 x i8>] %a.coerce, <16 x i8> %b) {
; CHECK: test_vqtbl3q_s8:
; CHECK: tbl {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b
; CHECK: tbl {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b
entry:
%__a.coerce.fca.0.extract.i = extractvalue [3 x <16 x i8>] %a.coerce, 0
%__a.coerce.fca.1.extract.i = extractvalue [3 x <16 x i8>] %a.coerce, 1
@ -154,7 +154,7 @@ entry:
define <16 x i8> @test_vqtbl4q_s8([4 x <16 x i8>] %a.coerce, <16 x i8> %b) {
; CHECK: test_vqtbl4q_s8:
; CHECK: tbl {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b
; CHECK: tbl {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b
entry:
%__a.coerce.fca.0.extract.i = extractvalue [4 x <16 x i8>] %a.coerce, 0
%__a.coerce.fca.1.extract.i = extractvalue [4 x <16 x i8>] %a.coerce, 1
@ -166,7 +166,7 @@ entry:
define <8 x i8> @test_vtbx1_s8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
; CHECK: test_vtbx1_s8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%vtbl1.i = shufflevector <8 x i8> %b, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%vtbl11.i = tail call <8 x i8> @llvm.aarch64.neon.vtbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %c)
@ -178,7 +178,7 @@ entry:
define <8 x i8> @test_vtbx2_s8(<8 x i8> %a, [2 x <8 x i8>] %b.coerce, <8 x i8> %c) {
; CHECK: test_vtbx2_s8:
; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__b.coerce.fca.0.extract.i = extractvalue [2 x <8 x i8>] %b.coerce, 0
%__b.coerce.fca.1.extract.i = extractvalue [2 x <8 x i8>] %b.coerce, 1
@ -189,7 +189,7 @@ entry:
define <8 x i8> @test_vtbx3_s8(<8 x i8> %a, [3 x <8 x i8>] %b.coerce, <8 x i8> %c) {
; CHECK: test_vtbx3_s8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__b.coerce.fca.0.extract.i = extractvalue [3 x <8 x i8>] %b.coerce, 0
%__b.coerce.fca.1.extract.i = extractvalue [3 x <8 x i8>] %b.coerce, 1
@ -205,7 +205,7 @@ entry:
define <8 x i8> @test_vtbx4_s8(<8 x i8> %a, [4 x <8 x i8>] %b.coerce, <8 x i8> %c) {
; CHECK: test_vtbx4_s8:
; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__b.coerce.fca.0.extract.i = extractvalue [4 x <8 x i8>] %b.coerce, 0
%__b.coerce.fca.1.extract.i = extractvalue [4 x <8 x i8>] %b.coerce, 1
@ -219,7 +219,7 @@ entry:
define <8 x i8> @test_vqtbx1_s8(<8 x i8> %a, <16 x i8> %b, <8 x i8> %c) {
; CHECK: test_vqtbx1_s8:
; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%vtbx1.i = tail call <8 x i8> @llvm.aarch64.neon.vtbx1.v8i8(<8 x i8> %a, <16 x i8> %b, <8 x i8> %c)
ret <8 x i8> %vtbx1.i
@ -227,7 +227,7 @@ entry:
define <8 x i8> @test_vqtbx2_s8(<8 x i8> %a, [2 x <16 x i8>] %b.coerce, <8 x i8> %c) {
; CHECK: test_vqtbx2_s8:
; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__b.coerce.fca.0.extract.i = extractvalue [2 x <16 x i8>] %b.coerce, 0
%__b.coerce.fca.1.extract.i = extractvalue [2 x <16 x i8>] %b.coerce, 1
@ -237,7 +237,7 @@ entry:
define <8 x i8> @test_vqtbx3_s8(<8 x i8> %a, [3 x <16 x i8>] %b.coerce, <8 x i8> %c) {
; CHECK: test_vqtbx3_s8:
; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__b.coerce.fca.0.extract.i = extractvalue [3 x <16 x i8>] %b.coerce, 0
%__b.coerce.fca.1.extract.i = extractvalue [3 x <16 x i8>] %b.coerce, 1
@ -248,7 +248,7 @@ entry:
define <8 x i8> @test_vqtbx4_s8(<8 x i8> %a, [4 x <16 x i8>] %b.coerce, <8 x i8> %c) {
; CHECK: test_vqtbx4_s8:
; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__b.coerce.fca.0.extract.i = extractvalue [4 x <16 x i8>] %b.coerce, 0
%__b.coerce.fca.1.extract.i = extractvalue [4 x <16 x i8>] %b.coerce, 1
@ -260,7 +260,7 @@ entry:
define <16 x i8> @test_vqtbx1q_s8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; CHECK: test_vqtbx1q_s8:
; CHECK: tbx {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.16b
; CHECK: tbx {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b
entry:
%vtbx1.i = tail call <16 x i8> @llvm.aarch64.neon.vtbx1.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c)
ret <16 x i8> %vtbx1.i
@ -268,7 +268,7 @@ entry:
define <16 x i8> @test_vqtbx2q_s8(<16 x i8> %a, [2 x <16 x i8>] %b.coerce, <16 x i8> %c) {
; CHECK: test_vqtbx2q_s8:
; CHECK: tbx {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b
; CHECK: tbx {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b
entry:
%__b.coerce.fca.0.extract.i = extractvalue [2 x <16 x i8>] %b.coerce, 0
%__b.coerce.fca.1.extract.i = extractvalue [2 x <16 x i8>] %b.coerce, 1
@ -278,7 +278,7 @@ entry:
define <16 x i8> @test_vqtbx3q_s8(<16 x i8> %a, [3 x <16 x i8>] %b.coerce, <16 x i8> %c) {
; CHECK: test_vqtbx3q_s8:
; CHECK: tbx {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b
; CHECK: tbx {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b
entry:
%__b.coerce.fca.0.extract.i = extractvalue [3 x <16 x i8>] %b.coerce, 0
%__b.coerce.fca.1.extract.i = extractvalue [3 x <16 x i8>] %b.coerce, 1
@ -289,7 +289,7 @@ entry:
define <16 x i8> @test_vqtbx4q_s8(<16 x i8> %a, [4 x <16 x i8>] %b.coerce, <16 x i8> %c) {
; CHECK: test_vqtbx4q_s8:
; CHECK: tbx {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b
; CHECK: tbx {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b
entry:
%__b.coerce.fca.0.extract.i = extractvalue [4 x <16 x i8>] %b.coerce, 0
%__b.coerce.fca.1.extract.i = extractvalue [4 x <16 x i8>] %b.coerce, 1
@ -301,7 +301,7 @@ entry:
define <8 x i8> @test_vtbl1_u8(<8 x i8> %a, <8 x i8> %b) {
; CHECK: test_vtbl1_u8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%vtbl1.i = shufflevector <8 x i8> %a, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%vtbl11.i = tail call <8 x i8> @llvm.aarch64.neon.vtbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %b)
@ -310,7 +310,7 @@ entry:
define <8 x i8> @test_vqtbl1_u8(<16 x i8> %a, <8 x i8> %b) {
; CHECK: test_vqtbl1_u8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%vtbl1.i = tail call <8 x i8> @llvm.aarch64.neon.vtbl1.v8i8(<16 x i8> %a, <8 x i8> %b)
ret <8 x i8> %vtbl1.i
@ -318,7 +318,7 @@ entry:
define <8 x i8> @test_vtbl2_u8([2 x <8 x i8>] %a.coerce, <8 x i8> %b) {
; CHECK: test_vtbl2_u8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__a.coerce.fca.0.extract.i = extractvalue [2 x <8 x i8>] %a.coerce, 0
%__a.coerce.fca.1.extract.i = extractvalue [2 x <8 x i8>] %a.coerce, 1
@ -329,7 +329,7 @@ entry:
define <8 x i8> @test_vqtbl2_u8([2 x <16 x i8>] %a.coerce, <8 x i8> %b) {
; CHECK: test_vqtbl2_u8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__a.coerce.fca.0.extract.i = extractvalue [2 x <16 x i8>] %a.coerce, 0
%__a.coerce.fca.1.extract.i = extractvalue [2 x <16 x i8>] %a.coerce, 1
@ -339,7 +339,7 @@ entry:
define <8 x i8> @test_vtbl3_u8([3 x <8 x i8>] %a.coerce, <8 x i8> %b) {
; CHECK: test_vtbl3_u8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__a.coerce.fca.0.extract.i = extractvalue [3 x <8 x i8>] %a.coerce, 0
%__a.coerce.fca.1.extract.i = extractvalue [3 x <8 x i8>] %a.coerce, 1
@ -352,7 +352,7 @@ entry:
define <8 x i8> @test_vqtbl3_u8([3 x <16 x i8>] %a.coerce, <8 x i8> %b) {
; CHECK: test_vqtbl3_u8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__a.coerce.fca.0.extract.i = extractvalue [3 x <16 x i8>] %a.coerce, 0
%__a.coerce.fca.1.extract.i = extractvalue [3 x <16 x i8>] %a.coerce, 1
@ -363,7 +363,7 @@ entry:
define <8 x i8> @test_vtbl4_u8([4 x <8 x i8>] %a.coerce, <8 x i8> %b) {
; CHECK: test_vtbl4_u8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__a.coerce.fca.0.extract.i = extractvalue [4 x <8 x i8>] %a.coerce, 0
%__a.coerce.fca.1.extract.i = extractvalue [4 x <8 x i8>] %a.coerce, 1
@ -377,7 +377,7 @@ entry:
define <8 x i8> @test_vqtbl4_u8([4 x <16 x i8>] %a.coerce, <8 x i8> %b) {
; CHECK: test_vqtbl4_u8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__a.coerce.fca.0.extract.i = extractvalue [4 x <16 x i8>] %a.coerce, 0
%__a.coerce.fca.1.extract.i = extractvalue [4 x <16 x i8>] %a.coerce, 1
@ -389,7 +389,7 @@ entry:
define <16 x i8> @test_vqtbl1q_u8(<16 x i8> %a, <16 x i8> %b) {
; CHECK: test_vqtbl1q_u8:
; CHECK: tbl {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.16b
; CHECK: tbl {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b
entry:
%vtbl1.i = tail call <16 x i8> @llvm.aarch64.neon.vtbl1.v16i8(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %vtbl1.i
@ -397,7 +397,7 @@ entry:
define <16 x i8> @test_vqtbl2q_u8([2 x <16 x i8>] %a.coerce, <16 x i8> %b) {
; CHECK: test_vqtbl2q_u8:
; CHECK: tbl {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b
; CHECK: tbl {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b
entry:
%__a.coerce.fca.0.extract.i = extractvalue [2 x <16 x i8>] %a.coerce, 0
%__a.coerce.fca.1.extract.i = extractvalue [2 x <16 x i8>] %a.coerce, 1
@ -407,7 +407,7 @@ entry:
define <16 x i8> @test_vqtbl3q_u8([3 x <16 x i8>] %a.coerce, <16 x i8> %b) {
; CHECK: test_vqtbl3q_u8:
; CHECK: tbl {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b
; CHECK: tbl {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b
entry:
%__a.coerce.fca.0.extract.i = extractvalue [3 x <16 x i8>] %a.coerce, 0
%__a.coerce.fca.1.extract.i = extractvalue [3 x <16 x i8>] %a.coerce, 1
@ -418,7 +418,7 @@ entry:
define <16 x i8> @test_vqtbl4q_u8([4 x <16 x i8>] %a.coerce, <16 x i8> %b) {
; CHECK: test_vqtbl4q_u8:
; CHECK: tbl {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b
; CHECK: tbl {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b
entry:
%__a.coerce.fca.0.extract.i = extractvalue [4 x <16 x i8>] %a.coerce, 0
%__a.coerce.fca.1.extract.i = extractvalue [4 x <16 x i8>] %a.coerce, 1
@ -430,7 +430,7 @@ entry:
define <8 x i8> @test_vtbx1_u8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
; CHECK: test_vtbx1_u8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%vtbl1.i = shufflevector <8 x i8> %b, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%vtbl11.i = tail call <8 x i8> @llvm.aarch64.neon.vtbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %c)
@ -442,7 +442,7 @@ entry:
define <8 x i8> @test_vtbx2_u8(<8 x i8> %a, [2 x <8 x i8>] %b.coerce, <8 x i8> %c) {
; CHECK: test_vtbx2_u8:
; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__b.coerce.fca.0.extract.i = extractvalue [2 x <8 x i8>] %b.coerce, 0
%__b.coerce.fca.1.extract.i = extractvalue [2 x <8 x i8>] %b.coerce, 1
@ -453,7 +453,7 @@ entry:
define <8 x i8> @test_vtbx3_u8(<8 x i8> %a, [3 x <8 x i8>] %b.coerce, <8 x i8> %c) {
; CHECK: test_vtbx3_u8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__b.coerce.fca.0.extract.i = extractvalue [3 x <8 x i8>] %b.coerce, 0
%__b.coerce.fca.1.extract.i = extractvalue [3 x <8 x i8>] %b.coerce, 1
@ -469,7 +469,7 @@ entry:
define <8 x i8> @test_vtbx4_u8(<8 x i8> %a, [4 x <8 x i8>] %b.coerce, <8 x i8> %c) {
; CHECK: test_vtbx4_u8:
; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__b.coerce.fca.0.extract.i = extractvalue [4 x <8 x i8>] %b.coerce, 0
%__b.coerce.fca.1.extract.i = extractvalue [4 x <8 x i8>] %b.coerce, 1
@ -483,7 +483,7 @@ entry:
define <8 x i8> @test_vqtbx1_u8(<8 x i8> %a, <16 x i8> %b, <8 x i8> %c) {
; CHECK: test_vqtbx1_u8:
; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%vtbx1.i = tail call <8 x i8> @llvm.aarch64.neon.vtbx1.v8i8(<8 x i8> %a, <16 x i8> %b, <8 x i8> %c)
ret <8 x i8> %vtbx1.i
@ -491,7 +491,7 @@ entry:
define <8 x i8> @test_vqtbx2_u8(<8 x i8> %a, [2 x <16 x i8>] %b.coerce, <8 x i8> %c) {
; CHECK: test_vqtbx2_u8:
; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__b.coerce.fca.0.extract.i = extractvalue [2 x <16 x i8>] %b.coerce, 0
%__b.coerce.fca.1.extract.i = extractvalue [2 x <16 x i8>] %b.coerce, 1
@ -501,7 +501,7 @@ entry:
define <8 x i8> @test_vqtbx3_u8(<8 x i8> %a, [3 x <16 x i8>] %b.coerce, <8 x i8> %c) {
; CHECK: test_vqtbx3_u8:
; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__b.coerce.fca.0.extract.i = extractvalue [3 x <16 x i8>] %b.coerce, 0
%__b.coerce.fca.1.extract.i = extractvalue [3 x <16 x i8>] %b.coerce, 1
@ -512,7 +512,7 @@ entry:
define <8 x i8> @test_vqtbx4_u8(<8 x i8> %a, [4 x <16 x i8>] %b.coerce, <8 x i8> %c) {
; CHECK: test_vqtbx4_u8:
; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__b.coerce.fca.0.extract.i = extractvalue [4 x <16 x i8>] %b.coerce, 0
%__b.coerce.fca.1.extract.i = extractvalue [4 x <16 x i8>] %b.coerce, 1
@ -524,7 +524,7 @@ entry:
define <16 x i8> @test_vqtbx1q_u8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; CHECK: test_vqtbx1q_u8:
; CHECK: tbx {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.16b
; CHECK: tbx {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b
entry:
%vtbx1.i = tail call <16 x i8> @llvm.aarch64.neon.vtbx1.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c)
ret <16 x i8> %vtbx1.i
@ -532,7 +532,7 @@ entry:
define <16 x i8> @test_vqtbx2q_u8(<16 x i8> %a, [2 x <16 x i8>] %b.coerce, <16 x i8> %c) {
; CHECK: test_vqtbx2q_u8:
; CHECK: tbx {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b
; CHECK: tbx {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b
entry:
%__b.coerce.fca.0.extract.i = extractvalue [2 x <16 x i8>] %b.coerce, 0
%__b.coerce.fca.1.extract.i = extractvalue [2 x <16 x i8>] %b.coerce, 1
@ -542,7 +542,7 @@ entry:
define <16 x i8> @test_vqtbx3q_u8(<16 x i8> %a, [3 x <16 x i8>] %b.coerce, <16 x i8> %c) {
; CHECK: test_vqtbx3q_u8:
; CHECK: tbx {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b
; CHECK: tbx {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b
entry:
%__b.coerce.fca.0.extract.i = extractvalue [3 x <16 x i8>] %b.coerce, 0
%__b.coerce.fca.1.extract.i = extractvalue [3 x <16 x i8>] %b.coerce, 1
@ -553,7 +553,7 @@ entry:
define <16 x i8> @test_vqtbx4q_u8(<16 x i8> %a, [4 x <16 x i8>] %b.coerce, <16 x i8> %c) {
; CHECK: test_vqtbx4q_u8:
; CHECK: tbx {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b
; CHECK: tbx {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b
entry:
%__b.coerce.fca.0.extract.i = extractvalue [4 x <16 x i8>] %b.coerce, 0
%__b.coerce.fca.1.extract.i = extractvalue [4 x <16 x i8>] %b.coerce, 1
@ -565,7 +565,7 @@ entry:
define <8 x i8> @test_vtbl1_p8(<8 x i8> %a, <8 x i8> %b) {
; CHECK: test_vtbl1_p8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%vtbl1.i = shufflevector <8 x i8> %a, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%vtbl11.i = tail call <8 x i8> @llvm.aarch64.neon.vtbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %b)
@ -574,7 +574,7 @@ entry:
define <8 x i8> @test_vqtbl1_p8(<16 x i8> %a, <8 x i8> %b) {
; CHECK: test_vqtbl1_p8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%vtbl1.i = tail call <8 x i8> @llvm.aarch64.neon.vtbl1.v8i8(<16 x i8> %a, <8 x i8> %b)
ret <8 x i8> %vtbl1.i
@ -582,7 +582,7 @@ entry:
define <8 x i8> @test_vtbl2_p8([2 x <8 x i8>] %a.coerce, <8 x i8> %b) {
; CHECK: test_vtbl2_p8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__a.coerce.fca.0.extract.i = extractvalue [2 x <8 x i8>] %a.coerce, 0
%__a.coerce.fca.1.extract.i = extractvalue [2 x <8 x i8>] %a.coerce, 1
@ -593,7 +593,7 @@ entry:
define <8 x i8> @test_vqtbl2_p8([2 x <16 x i8>] %a.coerce, <8 x i8> %b) {
; CHECK: test_vqtbl2_p8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__a.coerce.fca.0.extract.i = extractvalue [2 x <16 x i8>] %a.coerce, 0
%__a.coerce.fca.1.extract.i = extractvalue [2 x <16 x i8>] %a.coerce, 1
@ -603,7 +603,7 @@ entry:
define <8 x i8> @test_vtbl3_p8([3 x <8 x i8>] %a.coerce, <8 x i8> %b) {
; CHECK: test_vtbl3_p8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__a.coerce.fca.0.extract.i = extractvalue [3 x <8 x i8>] %a.coerce, 0
%__a.coerce.fca.1.extract.i = extractvalue [3 x <8 x i8>] %a.coerce, 1
@ -616,7 +616,7 @@ entry:
define <8 x i8> @test_vqtbl3_p8([3 x <16 x i8>] %a.coerce, <8 x i8> %b) {
; CHECK: test_vqtbl3_p8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__a.coerce.fca.0.extract.i = extractvalue [3 x <16 x i8>] %a.coerce, 0
%__a.coerce.fca.1.extract.i = extractvalue [3 x <16 x i8>] %a.coerce, 1
@ -627,7 +627,7 @@ entry:
define <8 x i8> @test_vtbl4_p8([4 x <8 x i8>] %a.coerce, <8 x i8> %b) {
; CHECK: test_vtbl4_p8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__a.coerce.fca.0.extract.i = extractvalue [4 x <8 x i8>] %a.coerce, 0
%__a.coerce.fca.1.extract.i = extractvalue [4 x <8 x i8>] %a.coerce, 1
@ -641,7 +641,7 @@ entry:
define <8 x i8> @test_vqtbl4_p8([4 x <16 x i8>] %a.coerce, <8 x i8> %b) {
; CHECK: test_vqtbl4_p8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__a.coerce.fca.0.extract.i = extractvalue [4 x <16 x i8>] %a.coerce, 0
%__a.coerce.fca.1.extract.i = extractvalue [4 x <16 x i8>] %a.coerce, 1
@ -653,7 +653,7 @@ entry:
define <16 x i8> @test_vqtbl1q_p8(<16 x i8> %a, <16 x i8> %b) {
; CHECK: test_vqtbl1q_p8:
; CHECK: tbl {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.16b
; CHECK: tbl {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b
entry:
%vtbl1.i = tail call <16 x i8> @llvm.aarch64.neon.vtbl1.v16i8(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %vtbl1.i
@ -661,7 +661,7 @@ entry:
define <16 x i8> @test_vqtbl2q_p8([2 x <16 x i8>] %a.coerce, <16 x i8> %b) {
; CHECK: test_vqtbl2q_p8:
; CHECK: tbl {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b
; CHECK: tbl {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b
entry:
%__a.coerce.fca.0.extract.i = extractvalue [2 x <16 x i8>] %a.coerce, 0
%__a.coerce.fca.1.extract.i = extractvalue [2 x <16 x i8>] %a.coerce, 1
@ -671,7 +671,7 @@ entry:
define <16 x i8> @test_vqtbl3q_p8([3 x <16 x i8>] %a.coerce, <16 x i8> %b) {
; CHECK: test_vqtbl3q_p8:
; CHECK: tbl {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b
; CHECK: tbl {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b
entry:
%__a.coerce.fca.0.extract.i = extractvalue [3 x <16 x i8>] %a.coerce, 0
%__a.coerce.fca.1.extract.i = extractvalue [3 x <16 x i8>] %a.coerce, 1
@ -682,7 +682,7 @@ entry:
define <16 x i8> @test_vqtbl4q_p8([4 x <16 x i8>] %a.coerce, <16 x i8> %b) {
; CHECK: test_vqtbl4q_p8:
; CHECK: tbl {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b
; CHECK: tbl {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b
entry:
%__a.coerce.fca.0.extract.i = extractvalue [4 x <16 x i8>] %a.coerce, 0
%__a.coerce.fca.1.extract.i = extractvalue [4 x <16 x i8>] %a.coerce, 1
@ -694,7 +694,7 @@ entry:
define <8 x i8> @test_vtbx1_p8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
; CHECK: test_vtbx1_p8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%vtbl1.i = shufflevector <8 x i8> %b, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%vtbl11.i = tail call <8 x i8> @llvm.aarch64.neon.vtbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %c)
@ -706,7 +706,7 @@ entry:
define <8 x i8> @test_vtbx2_p8(<8 x i8> %a, [2 x <8 x i8>] %b.coerce, <8 x i8> %c) {
; CHECK: test_vtbx2_p8:
; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__b.coerce.fca.0.extract.i = extractvalue [2 x <8 x i8>] %b.coerce, 0
%__b.coerce.fca.1.extract.i = extractvalue [2 x <8 x i8>] %b.coerce, 1
@ -717,7 +717,7 @@ entry:
define <8 x i8> @test_vtbx3_p8(<8 x i8> %a, [3 x <8 x i8>] %b.coerce, <8 x i8> %c) {
; CHECK: test_vtbx3_p8:
; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__b.coerce.fca.0.extract.i = extractvalue [3 x <8 x i8>] %b.coerce, 0
%__b.coerce.fca.1.extract.i = extractvalue [3 x <8 x i8>] %b.coerce, 1
@ -733,7 +733,7 @@ entry:
define <8 x i8> @test_vtbx4_p8(<8 x i8> %a, [4 x <8 x i8>] %b.coerce, <8 x i8> %c) {
; CHECK: test_vtbx4_p8:
; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__b.coerce.fca.0.extract.i = extractvalue [4 x <8 x i8>] %b.coerce, 0
%__b.coerce.fca.1.extract.i = extractvalue [4 x <8 x i8>] %b.coerce, 1
@ -747,7 +747,7 @@ entry:
define <8 x i8> @test_vqtbx1_p8(<8 x i8> %a, <16 x i8> %b, <8 x i8> %c) {
; CHECK: test_vqtbx1_p8:
; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%vtbx1.i = tail call <8 x i8> @llvm.aarch64.neon.vtbx1.v8i8(<8 x i8> %a, <16 x i8> %b, <8 x i8> %c)
ret <8 x i8> %vtbx1.i
@ -755,7 +755,7 @@ entry:
define <8 x i8> @test_vqtbx2_p8(<8 x i8> %a, [2 x <16 x i8>] %b.coerce, <8 x i8> %c) {
; CHECK: test_vqtbx2_p8:
; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__b.coerce.fca.0.extract.i = extractvalue [2 x <16 x i8>] %b.coerce, 0
%__b.coerce.fca.1.extract.i = extractvalue [2 x <16 x i8>] %b.coerce, 1
@ -765,7 +765,7 @@ entry:
define <8 x i8> @test_vqtbx3_p8(<8 x i8> %a, [3 x <16 x i8>] %b.coerce, <8 x i8> %c) {
; CHECK: test_vqtbx3_p8:
; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__b.coerce.fca.0.extract.i = extractvalue [3 x <16 x i8>] %b.coerce, 0
%__b.coerce.fca.1.extract.i = extractvalue [3 x <16 x i8>] %b.coerce, 1
@ -776,7 +776,7 @@ entry:
define <8 x i8> @test_vqtbx4_p8(<8 x i8> %a, [4 x <16 x i8>] %b.coerce, <8 x i8> %c) {
; CHECK: test_vqtbx4_p8:
; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b
; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b
entry:
%__b.coerce.fca.0.extract.i = extractvalue [4 x <16 x i8>] %b.coerce, 0
%__b.coerce.fca.1.extract.i = extractvalue [4 x <16 x i8>] %b.coerce, 1
@ -788,7 +788,7 @@ entry:
define <16 x i8> @test_vqtbx1q_p8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; CHECK: test_vqtbx1q_p8:
; CHECK: tbx {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.16b
; CHECK: tbx {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b
entry:
%vtbx1.i = tail call <16 x i8> @llvm.aarch64.neon.vtbx1.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c)
ret <16 x i8> %vtbx1.i
@ -796,7 +796,7 @@ entry:
define <16 x i8> @test_vqtbx2q_p8(<16 x i8> %a, [2 x <16 x i8>] %b.coerce, <16 x i8> %c) {
; CHECK: test_vqtbx2q_p8:
; CHECK: tbx {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b
; CHECK: tbx {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b
entry:
%__b.coerce.fca.0.extract.i = extractvalue [2 x <16 x i8>] %b.coerce, 0
%__b.coerce.fca.1.extract.i = extractvalue [2 x <16 x i8>] %b.coerce, 1
@ -806,7 +806,7 @@ entry:
define <16 x i8> @test_vqtbx3q_p8(<16 x i8> %a, [3 x <16 x i8>] %b.coerce, <16 x i8> %c) {
; CHECK: test_vqtbx3q_p8:
; CHECK: tbx {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b
; CHECK: tbx {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b
entry:
%__b.coerce.fca.0.extract.i = extractvalue [3 x <16 x i8>] %b.coerce, 0
%__b.coerce.fca.1.extract.i = extractvalue [3 x <16 x i8>] %b.coerce, 1
@ -817,7 +817,7 @@ entry:
define <16 x i8> @test_vqtbx4q_p8(<16 x i8> %a, [4 x <16 x i8>] %b.coerce, <16 x i8> %c) {
; CHECK: test_vqtbx4q_p8:
; CHECK: tbx {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b
; CHECK: tbx {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b
entry:
%__b.coerce.fca.0.extract.i = extractvalue [4 x <16 x i8>] %b.coerce, 0
%__b.coerce.fca.1.extract.i = extractvalue [4 x <16 x i8>] %b.coerce, 1

6
test/CodeGen/AArch64/neon-truncStore-extLoad.ll
View File

@ -6,7 +6,7 @@
define void @truncStore.v2i64(<2 x i64> %a, <2 x i32>* %result) {
; CHECK-LABEL: truncStore.v2i64:
; CHECK: xtn v{{[0-9]+}}.2s, v{{[0-9]+}}.2d
; CHECK: {{st1 {v[0-9]+.2s}|str d[0-9]+}}, [x{{[0-9]+|sp}}]
; CHECK: {{st1 { v[0-9]+.2s }|str d[0-9]+}}, [x{{[0-9]+|sp}}]
%b = trunc <2 x i64> %a to <2 x i32>
store <2 x i32> %b, <2 x i32>* %result
ret void
@ -15,7 +15,7 @@ define void @truncStore.v2i64(<2 x i64> %a, <2 x i32>* %result) {
define void @truncStore.v4i32(<4 x i32> %a, <4 x i16>* %result) {
; CHECK-LABEL: truncStore.v4i32:
; CHECK: xtn v{{[0-9]+}}.4h, v{{[0-9]+}}.4s
; CHECK: {{st1 {v[0-9]+.4h}|str d[0-9]+}}, [x{{[0-9]+|sp}}]
; CHECK: {{st1 { v[0-9]+.4h }|str d[0-9]+}}, [x{{[0-9]+|sp}}]
%b = trunc <4 x i32> %a to <4 x i16>
store <4 x i16> %b, <4 x i16>* %result
ret void
@ -24,7 +24,7 @@ define void @truncStore.v4i32(<4 x i32> %a, <4 x i16>* %result) {
define void @truncStore.v8i16(<8 x i16> %a, <8 x i8>* %result) {
; CHECK-LABEL: truncStore.v8i16:
; CHECK: xtn v{{[0-9]+}}.8b, v{{[0-9]+}}.8h
; CHECK: {{st1 {v[0-9]+.8b}|str d[0-9]+}}, [x{{[0-9]+|sp}}]
; CHECK: {{st1 { v[0-9]+.8b }|str d[0-9]+}}, [x{{[0-9]+|sp}}]
%b = trunc <8 x i16> %a to <8 x i8>
store <8 x i8> %b, <8 x i8>* %result
ret void

86
test/CodeGen/AArch64/unaligned-vector-ld1-st1.ll
View File

@ -9,14 +9,14 @@
define <16 x i8> @qwordint (<16 x i8>* %head.v16i8, <8 x i16>* %head.v8i16, <4 x i32>* %head.v4i32, <2 x i64>* %head.v2i64,
<16 x i8>* %tail.v16i8, <8 x i16>* %tail.v8i16, <4 x i32>* %tail.v4i32, <2 x i64>* %tail.v2i64) {
; CHECK-LABEL: qwordint
; CHECK: ld1 {v0.16b}, [x0]
; CHECK: ld1 {v1.8h}, [x1]
; CHECK: ld1 {v2.4s}, [x2]
; CHECK: ld1 {v3.2d}, [x3]
; CHECK: st1 {v0.16b}, [x4]
; CHECK: st1 {v1.8h}, [x5]
; CHECK: st1 {v2.4s}, [x6]
; CHECK: st1 {v3.2d}, [x7]
; CHECK: ld1 { v0.16b }, [x0]
; CHECK: ld1 { v1.8h }, [x1]
; CHECK: ld1 { v2.4s }, [x2]
; CHECK: ld1 { v3.2d }, [x3]
; CHECK: st1 { v0.16b }, [x4]
; CHECK: st1 { v1.8h }, [x5]
; CHECK: st1 { v2.4s }, [x6]
; CHECK: st1 { v3.2d }, [x7]
; BE-STRICT-ALIGN-LABEL: qwordint
; BE-STRICT-ALIGN: ldrb
; BE-STRICT-ALIGN: ldrh
@ -42,10 +42,10 @@ entry:
define <4 x float> @qwordfloat (<4 x float>* %head.v4f32, <2 x double>* %head.v2f64,
<4 x float>* %tail.v4f32, <2 x double>* %tail.v2f64) {
; CHECK-LABEL: qwordfloat
; CHECK: ld1 {v0.4s}, [x0]
; CHECK: ld1 {v1.2d}, [x1]
; CHECK: st1 {v0.4s}, [x2]
; CHECK: st1 {v1.2d}, [x3]
; CHECK: ld1 { v0.4s }, [x0]
; CHECK: ld1 { v1.2d }, [x1]
; CHECK: st1 { v0.4s }, [x2]
; CHECK: st1 { v1.2d }, [x3]
; BE-STRICT-ALIGN-LABEL: qwordfloat
; BE-STRICT-ALIGN: ldr
; BE-STRICT-ALIGN: ldr
@ -63,23 +63,23 @@ entry:
define <8 x i8> @dwordint (<8 x i8>* %head.v8i8, <4 x i16>* %head.v4i16, <2 x i32>* %head.v2i32, <1 x i64>* %head.v1i64,
<8 x i8>* %tail.v8i8, <4 x i16>* %tail.v4i16, <2 x i32>* %tail.v2i32, <1 x i64>* %tail.v1i64) {
; CHECK-LABEL: dwordint
; CHECK: ld1 {v0.8b}, [x0]
; CHECK: ld1 {v1.4h}, [x1]
; CHECK: ld1 {v2.2s}, [x2]
; CHECK: ld1 {v3.1d}, [x3]
; CHECK: st1 {v0.8b}, [x4]
; CHECK: st1 {v1.4h}, [x5]
; CHECK: st1 {v2.2s}, [x6]
; CHECK: st1 {v3.1d}, [x7]
; CHECK: ld1 { v0.8b }, [x0]
; CHECK: ld1 { v1.4h }, [x1]
; CHECK: ld1 { v2.2s }, [x2]
; CHECK: ld1 { v3.1d }, [x3]
; CHECK: st1 { v0.8b }, [x4]
; CHECK: st1 { v1.4h }, [x5]
; CHECK: st1 { v2.2s }, [x6]
; CHECK: st1 { v3.1d }, [x7]
; BE-STRICT-ALIGN-LABEL: dwordint
; BE-STRICT-ALIGN: ldrb
; BE-STRICT-ALIGN: ldrh
; BE-STRICT-ALIGN: ldr
; BE-STRICT-ALIGN: ld1 {v1.1d}, [x3]
; BE-STRICT-ALIGN: ld1 { v1.1d }, [x3]
; BE-STRICT-ALIGN: strb
; BE-STRICT-ALIGN: strh
; BE-STRICT-ALIGN: str
; BE-STRICT-ALIGN: st1 {v1.1d}, [x7]
; BE-STRICT-ALIGN: st1 { v1.1d }, [x7]
entry:
%val.v8i8 = load <8 x i8>* %head.v8i8, align 1
%val.v4i16 = load <4 x i16>* %head.v4i16, align 2
@ -96,15 +96,15 @@ entry:
define <2 x float> @dwordfloat (<2 x float>* %head.v2f32, <1 x double>* %head.v1f64,
<2 x float>* %tail.v2f32, <1 x double>* %tail.v1f64) {
; CHECK-LABEL: dwordfloat
; CHECK: ld1 {v0.2s}, [x0]
; CHECK: ld1 {v1.1d}, [x1]
; CHECK: st1 {v0.2s}, [x2]
; CHECK: st1 {v1.1d}, [x3]
; CHECK: ld1 { v0.2s }, [x0]
; CHECK: ld1 { v1.1d }, [x1]
; CHECK: st1 { v0.2s }, [x2]
; CHECK: st1 { v1.1d }, [x3]
; BE-STRICT-ALIGN-LABEL: dwordfloat
; BE-STRICT-ALIGN: ldr
; BE-STRICT-ALIGN: ld1 {v1.1d}, [x1]
; BE-STRICT-ALIGN: ld1 { v1.1d }, [x1]
; BE-STRICT-ALIGN: str
; BE-STRICT-ALIGN: st1 {v1.1d}, [x3]
; BE-STRICT-ALIGN: st1 { v1.1d }, [x3]
entry:
%val.v2f32 = load <2 x float>* %head.v2f32, align 4
%val.v1f64 = load <1 x double>* %head.v1f64, align 8
@ -117,14 +117,14 @@ entry:
define <2 x i64> @align2vi64 (<2 x i64>* %head.byte, <2 x i64>* %head.half, <2 x i64>* %head.word, <2 x i64>* %head.dword,
<2 x i64>* %tail.byte, <2 x i64>* %tail.half, <2 x i64>* %tail.word, <2 x i64>* %tail.dword) {
; CHECK-LABEL: align2vi64
; CHECK: ld1 {v0.2d}, [x0]
; CHECK: ld1 {v1.2d}, [x1]
; CHECK: ld1 {v2.2d}, [x2]
; CHECK: ld1 {v3.2d}, [x3]
; CHECK: st1 {v0.2d}, [x4]
; CHECK: st1 {v1.2d}, [x5]
; CHECK: st1 {v2.2d}, [x6]
; CHECK: st1 {v3.2d}, [x7]
; CHECK: ld1 { v0.2d }, [x0]
; CHECK: ld1 { v1.2d }, [x1]
; CHECK: ld1 { v2.2d }, [x2]
; CHECK: ld1 { v3.2d }, [x3]
; CHECK: st1 { v0.2d }, [x4]
; CHECK: st1 { v1.2d }, [x5]
; CHECK: st1 { v2.2d }, [x6]
; CHECK: st1 { v3.2d }, [x7]
; BE-STRICT-ALIGN-LABEL: align2vi64
; BE-STRICT-ALIGN: ldrb
; BE-STRICT-ALIGN: ldrh
@ -142,18 +142,18 @@ entry:
store <2 x i64> %val.word, <2 x i64>* %tail.word, align 4
store <2 x i64> %val.dword, <2 x i64>* %tail.dword, align 8
ret <2 x i64> %val.byte
}
}
;; Check load/store of 64-bit vectors with less-than 8-byte alignment
define <2 x float> @align2vf32 (<2 x float>* %head.byte, <2 x float>* %head.half, <2 x float>* %head.word, <2 x float>* %head.dword,
<2 x float>* %tail.byte, <2 x float>* %tail.half, <2 x float>* %tail.word, <2 x float>* %tail.dword) {
; CHECK-LABEL: align2vf32
; CHECK: ld1 {v0.2s}, [x0]
; CHECK: ld1 {v1.2s}, [x1]
; CHECK: ld1 {v2.2s}, [x2]
; CHECK: st1 {v0.2s}, [x4]
; CHECK: st1 {v1.2s}, [x5]
; CHECK: st1 {v2.2s}, [x6]
; CHECK: ld1 { v0.2s }, [x0]
; CHECK: ld1 { v1.2s }, [x1]
; CHECK: ld1 { v2.2s }, [x2]
; CHECK: st1 { v0.2s }, [x4]
; CHECK: st1 { v1.2s }, [x5]
; CHECK: st1 { v2.2s }, [x6]
; BE-STRICT-ALIGN-LABEL: align2vf32
; BE-STRICT-ALIGN: ldrb
; BE-STRICT-ALIGN: ldrh

784
test/MC/AArch64/neon-simd-ldst-multi-elem.s
View File

@ -5,459 +5,459 @@
//------------------------------------------------------------------------------
// Store multiple 1-element structures from one register
//------------------------------------------------------------------------------
st1 {v0.16b}, [x0]
st1 {v15.8h}, [x15]
st1 {v31.4s}, [sp]
st1 {v0.2d}, [x0]
st1 {v0.8b}, [x0]
st1 {v15.4h}, [x15]
st1 {v31.2s}, [sp]
st1 {v0.1d}, [x0]
// CHECK: st1 {v0.16b}, [x0] // encoding: [0x00,0x70,0x00,0x4c]
// CHECK: st1 {v15.8h}, [x15] // encoding: [0xef,0x75,0x00,0x4c]
// CHECK: st1 {v31.4s}, [sp] // encoding: [0xff,0x7b,0x00,0x4c]
// CHECK: st1 {v0.2d}, [x0] // encoding: [0x00,0x7c,0x00,0x4c]
// CHECK: st1 {v0.8b}, [x0] // encoding: [0x00,0x70,0x00,0x0c]
// CHECK: st1 {v15.4h}, [x15] // encoding: [0xef,0x75,0x00,0x0c]
// CHECK: st1 {v31.2s}, [sp] // encoding: [0xff,0x7b,0x00,0x0c]
// CHECK: st1 {v0.1d}, [x0] // encoding: [0x00,0x7c,0x00,0x0c]
st1 { v0.16b }, [x0]
st1 { v15.8h }, [x15]
st1 { v31.4s }, [sp]
st1 { v0.2d }, [x0]
st1 { v0.8b }, [x0]
st1 { v15.4h }, [x15]
st1 { v31.2s }, [sp]
st1 { v0.1d }, [x0]
// CHECK: st1 { v0.16b }, [x0] // encoding: [0x00,0x70,0x00,0x4c]
// CHECK: st1 { v15.8h }, [x15] // encoding: [0xef,0x75,0x00,0x4c]
// CHECK: st1 { v31.4s }, [sp] // encoding: [0xff,0x7b,0x00,0x4c]
// CHECK: st1 { v0.2d }, [x0] // encoding: [0x00,0x7c,0x00,0x4c]
// CHECK: st1 { v0.8b }, [x0] // encoding: [0x00,0x70,0x00,0x0c]
// CHECK: st1 { v15.4h }, [x15] // encoding: [0xef,0x75,0x00,0x0c]
// CHECK: st1 { v31.2s }, [sp] // encoding: [0xff,0x7b,0x00,0x0c]
// CHECK: st1 { v0.1d }, [x0] // encoding: [0x00,0x7c,0x00,0x0c]
//------------------------------------------------------------------------------
// Store multiple 1-element structures from two consecutive registers
//------------------------------------------------------------------------------
st1 {v0.16b, v1.16b}, [x0]
st1 {v15.8h, v16.8h}, [x15]
st1 {v31.4s, v0.4s}, [sp]
st1 {v0.2d, v1.2d}, [x0]
st1 {v0.8b, v1.8b}, [x0]
st1 {v15.4h, v16.4h}, [x15]
st1 {v31.2s, v0.2s}, [sp]
st1 {v0.1d, v1.1d}, [x0]
// CHECK: st1 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0xa0,0x00,0x4c]
// CHECK: st1 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0xa5,0x00,0x4c]
// CHECK: st1 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0xab,0x00,0x4c]
// CHECK: st1 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0xac,0x00,0x4c]
// CHECK: st1 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0xa0,0x00,0x0c]
// CHECK: st1 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0xa5,0x00,0x0c]
// CHECK: st1 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0xab,0x00,0x0c]
// CHECK: st1 {v0.1d, v1.1d}, [x0] // encoding: [0x00,0xac,0x00,0x0c]
st1 { v0.16b, v1.16b }, [x0]
st1 { v15.8h, v16.8h }, [x15]
st1 { v31.4s, v0.4s }, [sp]
st1 { v0.2d, v1.2d }, [x0]
st1 { v0.8b, v1.8b }, [x0]
st1 { v15.4h, v16.4h }, [x15]
st1 { v31.2s, v0.2s }, [sp]
st1 { v0.1d, v1.1d }, [x0]
// CHECK: st1 { v0.16b, v1.16b }, [x0] // encoding: [0x00,0xa0,0x00,0x4c]
// CHECK: st1 { v15.8h, v16.8h }, [x15] // encoding: [0xef,0xa5,0x00,0x4c]
// CHECK: st1 { v31.4s, v0.4s }, [sp] // encoding: [0xff,0xab,0x00,0x4c]
// CHECK: st1 { v0.2d, v1.2d }, [x0] // encoding: [0x00,0xac,0x00,0x4c]
// CHECK: st1 { v0.8b, v1.8b }, [x0] // encoding: [0x00,0xa0,0x00,0x0c]
// CHECK: st1 { v15.4h, v16.4h }, [x15] // encoding: [0xef,0xa5,0x00,0x0c]
// CHECK: st1 { v31.2s, v0.2s }, [sp] // encoding: [0xff,0xab,0x00,0x0c]
// CHECK: st1 { v0.1d, v1.1d }, [x0] // encoding: [0x00,0xac,0x00,0x0c]
st1 {v0.16b-v1.16b}, [x0]
st1 {v15.8h-v16.8h}, [x15]
st1 {v31.4s-v0.4s}, [sp]
st1 {v0.2d-v1.2d}, [x0]
st1 {v0.8b-v1.8b}, [x0]
st1 {v15.4h-v16.4h}, [x15]
st1 {v31.2s-v0.2s}, [sp]
st1 {v0.1d-v1.1d}, [x0]
// CHECK: st1 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0xa0,0x00,0x4c]
// CHECK: st1 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0xa5,0x00,0x4c]
// CHECK: st1 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0xab,0x00,0x4c]
// CHECK: st1 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0xac,0x00,0x4c]
// CHECK: st1 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0xa0,0x00,0x0c]
// CHECK: st1 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0xa5,0x00,0x0c]
// CHECK: st1 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0xab,0x00,0x0c]
// CHECK: st1 {v0.1d, v1.1d}, [x0] // encoding: [0x00,0xac,0x00,0x0c]
st1 { v0.16b-v1.16b }, [x0]
st1 { v15.8h-v16.8h }, [x15]
st1 { v31.4s-v0.4s }, [sp]
st1 { v0.2d-v1.2d }, [x0]
st1 { v0.8b-v1.8b }, [x0]
st1 { v15.4h-v16.4h }, [x15]
st1 { v31.2s-v0.2s }, [sp]
st1 { v0.1d-v1.1d }, [x0]
// CHECK: st1 { v0.16b, v1.16b }, [x0] // encoding: [0x00,0xa0,0x00,0x4c]
// CHECK: st1 { v15.8h, v16.8h }, [x15] // encoding: [0xef,0xa5,0x00,0x4c]
// CHECK: st1 { v31.4s, v0.4s }, [sp] // encoding: [0xff,0xab,0x00,0x4c]
// CHECK: st1 { v0.2d, v1.2d }, [x0] // encoding: [0x00,0xac,0x00,0x4c]
// CHECK: st1 { v0.8b, v1.8b }, [x0] // encoding: [0x00,0xa0,0x00,0x0c]
// CHECK: st1 { v15.4h, v16.4h }, [x15] // encoding: [0xef,0xa5,0x00,0x0c]
// CHECK: st1 { v31.2s, v0.2s }, [sp] // encoding: [0xff,0xab,0x00,0x0c]
// CHECK: st1 { v0.1d, v1.1d }, [x0] // encoding: [0x00,0xac,0x00,0x0c]
//------------------------------------------------------------------------------
// Store multiple 1-element structures from three consecutive registers
//------------------------------------------------------------------------------
st1 {v0.16b, v1.16b, v2.16b}, [x0]
st1 {v15.8h, v16.8h, v17.8h}, [x15]
st1 {v31.4s, v0.4s, v1.4s}, [sp]
st1 {v0.2d, v1.2d, v2.2d}, [x0]
st1 {v0.8b, v1.8b, v2.8b}, [x0]
st1 {v15.4h, v16.4h, v17.4h}, [x15]
st1 {v31.2s, v0.2s, v1.2s}, [sp]
st1 {v0.1d, v1.1d, v2.1d}, [x0]
// CHECK: st1 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x60,0x00,0x4c]
// CHECK: st1 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x65,0x00,0x4c]
// CHECK: st1 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x6b,0x00,0x4c]
// CHECK: st1 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x6c,0x00,0x4c]
// CHECK: st1 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x60,0x00,0x0c]
// CHECK: st1 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x65,0x00,0x0c]
// CHECK: st1 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x6b,0x00,0x0c]
// CHECK: st1 {v0.1d, v1.1d, v2.1d}, [x0] // encoding: [0x00,0x6c,0x00,0x0c]
st1 { v0.16b, v1.16b, v2.16b }, [x0]
st1 { v15.8h, v16.8h, v17.8h }, [x15]
st1 { v31.4s, v0.4s, v1.4s }, [sp]
st1 { v0.2d, v1.2d, v2.2d }, [x0]
st1 { v0.8b, v1.8b, v2.8b }, [x0]
st1 { v15.4h, v16.4h, v17.4h }, [x15]
st1 { v31.2s, v0.2s, v1.2s }, [sp]
st1 { v0.1d, v1.1d, v2.1d }, [x0]
// CHECK: st1 { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0x60,0x00,0x4c]
// CHECK: st1 { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0x65,0x00,0x4c]
// CHECK: st1 { v31.4s, v0.4s, v1.4s }, [sp] // encoding: [0xff,0x6b,0x00,0x4c]
// CHECK: st1 { v0.2d, v1.2d, v2.2d }, [x0] // encoding: [0x00,0x6c,0x00,0x4c]
// CHECK: st1 { v0.8b, v1.8b, v2.8b }, [x0] // encoding: [0x00,0x60,0x00,0x0c]
// CHECK: st1 { v15.4h, v16.4h, v17.4h }, [x15] // encoding: [0xef,0x65,0x00,0x0c]
// CHECK: st1 { v31.2s, v0.2s, v1.2s }, [sp] // encoding: [0xff,0x6b,0x00,0x0c]
// CHECK: st1 { v0.1d, v1.1d, v2.1d }, [x0] // encoding: [0x00,0x6c,0x00,0x0c]
st1 {v0.16b-v2.16b}, [x0]
st1 {v15.8h-v17.8h}, [x15]
st1 {v31.4s-v1.4s}, [sp]
st1 {v0.2d-v2.2d}, [x0]
st1 {v0.8b-v2.8b}, [x0]
st1 {v15.4h-v17.4h}, [x15]
st1 {v31.2s-v1.2s}, [sp]
st1 {v0.1d-v2.1d}, [x0]
// CHECK: st1 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x60,0x00,0x4c]
// CHECK: st1 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x65,0x00,0x4c]
// CHECK: st1 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x6b,0x00,0x4c]
// CHECK: st1 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x6c,0x00,0x4c]
// CHECK: st1 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x60,0x00,0x0c]
// CHECK: st1 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x65,0x00,0x0c]
// CHECK: st1 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x6b,0x00,0x0c]
// CHECK: st1 {v0.1d, v1.1d, v2.1d}, [x0] // encoding: [0x00,0x6c,0x00,0x0c]
st1 { v0.16b-v2.16b }, [x0]
st1 { v15.8h-v17.8h }, [x15]
st1 { v31.4s-v1.4s }, [sp]
st1 { v0.2d-v2.2d }, [x0]
st1 { v0.8b-v2.8b }, [x0]
st1 { v15.4h-v17.4h }, [x15]
st1 { v31.2s-v1.2s }, [sp]
st1 { v0.1d-v2.1d }, [x0]
// CHECK: st1 { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0x60,0x00,0x4c]
// CHECK: st1 { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0x65,0x00,0x4c]
// CHECK: st1 { v31.4s, v0.4s, v1.4s }, [sp] // encoding: [0xff,0x6b,0x00,0x4c]
// CHECK: st1 { v0.2d, v1.2d, v2.2d }, [x0] // encoding: [0x00,0x6c,0x00,0x4c]
// CHECK: st1 { v0.8b, v1.8b, v2.8b }, [x0] // encoding: [0x00,0x60,0x00,0x0c]
// CHECK: st1 { v15.4h, v16.4h, v17.4h }, [x15] // encoding: [0xef,0x65,0x00,0x0c]
// CHECK: st1 { v31.2s, v0.2s, v1.2s }, [sp] // encoding: [0xff,0x6b,0x00,0x0c]
// CHECK: st1 { v0.1d, v1.1d, v2.1d }, [x0] // encoding: [0x00,0x6c,0x00,0x0c]
//------------------------------------------------------------------------------
// Store multiple 1-element structures from four consecutive registers
//------------------------------------------------------------------------------
st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0]
st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15]
st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp]
st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0]
st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0]
st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15]
st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp]
st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0]
// CHECK: st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x20,0x00,0x4c]
// CHECK: st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x25,0x00,0x4c]
// CHECK: st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x2b,0x00,0x4c]
// CHECK: st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x2c,0x00,0x4c]
// CHECK: st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x20,0x00,0x0c]
// CHECK: st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x25,0x00,0x0c]
// CHECK: st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x2b,0x00,0x0c]
// CHECK: st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] // encoding: [0x00,0x2c,0x00,0x0c]
st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]
st1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]
st1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]
st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]
st1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]
st1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]
st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0]
// CHECK: st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0x20,0x00,0x4c]
// CHECK: st1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0x25,0x00,0x4c]
// CHECK: st1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] // encoding: [0xff,0x2b,0x00,0x4c]
// CHECK: st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] // encoding: [0x00,0x2c,0x00,0x4c]
// CHECK: st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x20,0x00,0x0c]
// CHECK: st1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] // encoding: [0xef,0x25,0x00,0x0c]
// CHECK: st1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] // encoding: [0xff,0x2b,0x00,0x0c]
// CHECK: st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0] // encoding: [0x00,0x2c,0x00,0x0c]
st1 {v0.16b-v3.16b}, [x0]
st1 {v15.8h-v18.8h}, [x15]
st1 {v31.4s-v2.4s}, [sp]
st1 {v0.2d-v3.2d}, [x0]
st1 {v0.8b-v3.8b}, [x0]
st1 {v15.4h-v18.4h}, [x15]
st1 {v31.2s-v2.2s}, [sp]
st1 {v0.1d-v3.1d}, [x0]
// CHECK: st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x20,0x00,0x4c]
// CHECK: st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x25,0x00,0x4c]
// CHECK: st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x2b,0x00,0x4c]
// CHECK: st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x2c,0x00,0x4c]
// CHECK: st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x20,0x00,0x0c]
// CHECK: st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x25,0x00,0x0c]
// CHECK: st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x2b,0x00,0x0c]
// CHECK: st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] // encoding: [0x00,0x2c,0x00,0x0c]
st1 { v0.16b-v3.16b }, [x0]
st1 { v15.8h-v18.8h }, [x15]
st1 { v31.4s-v2.4s }, [sp]
st1 { v0.2d-v3.2d }, [x0]
st1 { v0.8b-v3.8b }, [x0]
st1 { v15.4h-v18.4h }, [x15]
st1 { v31.2s-v2.2s }, [sp]
st1 { v0.1d-v3.1d }, [x0]
// CHECK: st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0x20,0x00,0x4c]
// CHECK: st1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0x25,0x00,0x4c]
// CHECK: st1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] // encoding: [0xff,0x2b,0x00,0x4c]
// CHECK: st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] // encoding: [0x00,0x2c,0x00,0x4c]
// CHECK: st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x20,0x00,0x0c]
// CHECK: st1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] // encoding: [0xef,0x25,0x00,0x0c]
// CHECK: st1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] // encoding: [0xff,0x2b,0x00,0x0c]
// CHECK: st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0] // encoding: [0x00,0x2c,0x00,0x0c]
//------------------------------------------------------------------------------
// Store multiple 2-element structures from two consecutive registers
//------------------------------------------------------------------------------
st2 {v0.16b, v1.16b}, [x0]
st2 {v15.8h, v16.8h}, [x15]
st2 {v31.4s, v0.4s}, [sp]
st2 {v0.2d, v1.2d}, [x0]
st2 {v0.8b, v1.8b}, [x0]
st2 {v15.4h, v16.4h}, [x15]
st2 {v31.2s, v0.2s}, [sp]
// CHECK: st2 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0x80,0x00,0x4c]
// CHECK: st2 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0x85,0x00,0x4c]
// CHECK: st2 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0x8b,0x00,0x4c]
// CHECK: st2 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0x8c,0x00,0x4c]
// CHECK: st2 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0x80,0x00,0x0c]
// CHECK: st2 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0x85,0x00,0x0c]
// CHECK: st2 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0x8b,0x00,0x0c]
st2 { v0.16b, v1.16b }, [x0]
st2 { v15.8h, v16.8h }, [x15]
st2 { v31.4s, v0.4s }, [sp]
st2 { v0.2d, v1.2d }, [x0]
st2 { v0.8b, v1.8b }, [x0]
st2 { v15.4h, v16.4h }, [x15]
st2 { v31.2s, v0.2s }, [sp]
// CHECK: st2 { v0.16b, v1.16b }, [x0] // encoding: [0x00,0x80,0x00,0x4c]
// CHECK: st2 { v15.8h, v16.8h }, [x15] // encoding: [0xef,0x85,0x00,0x4c]
// CHECK: st2 { v31.4s, v0.4s }, [sp] // encoding: [0xff,0x8b,0x00,0x4c]
// CHECK: st2 { v0.2d, v1.2d }, [x0] // encoding: [0x00,0x8c,0x00,0x4c]
// CHECK: st2 { v0.8b, v1.8b }, [x0] // encoding: [0x00,0x80,0x00,0x0c]
// CHECK: st2 { v15.4h, v16.4h }, [x15] // encoding: [0xef,0x85,0x00,0x0c]
// CHECK: st2 { v31.2s, v0.2s }, [sp] // encoding: [0xff,0x8b,0x00,0x0c]
st2 {v0.16b-v1.16b}, [x0]
st2 {v15.8h-v16.8h}, [x15]
st2 {v31.4s-v0.4s}, [sp]
st2 {v0.2d-v1.2d}, [x0]
st2 {v0.8b-v1.8b}, [x0]
st2 {v15.4h-v16.4h}, [x15]
st2 {v31.2s-v0.2s}, [sp]
// CHECK: st2 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0x80,0x00,0x4c]
// CHECK: st2 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0x85,0x00,0x4c]
// CHECK: st2 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0x8b,0x00,0x4c]
// CHECK: st2 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0x8c,0x00,0x4c]
// CHECK: st2 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0x80,0x00,0x0c]
// CHECK: st2 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0x85,0x00,0x0c]
// CHECK: st2 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0x8b,0x00,0x0c]
st2 { v0.16b-v1.16b }, [x0]
st2 { v15.8h-v16.8h }, [x15]
st2 { v31.4s-v0.4s }, [sp]
st2 { v0.2d-v1.2d }, [x0]
st2 { v0.8b-v1.8b }, [x0]
st2 { v15.4h-v16.4h }, [x15]
st2 { v31.2s-v0.2s }, [sp]
// CHECK: st2 { v0.16b, v1.16b }, [x0] // encoding: [0x00,0x80,0x00,0x4c]
// CHECK: st2 { v15.8h, v16.8h }, [x15] // encoding: [0xef,0x85,0x00,0x4c]
// CHECK: st2 { v31.4s, v0.4s }, [sp] // encoding: [0xff,0x8b,0x00,0x4c]
// CHECK: st2 { v0.2d, v1.2d }, [x0] // encoding: [0x00,0x8c,0x00,0x4c]
// CHECK: st2 { v0.8b, v1.8b }, [x0] // encoding: [0x00,0x80,0x00,0x0c]
// CHECK: st2 { v15.4h, v16.4h }, [x15] // encoding: [0xef,0x85,0x00,0x0c]
// CHECK: st2 { v31.2s, v0.2s }, [sp] // encoding: [0xff,0x8b,0x00,0x0c]
//------------------------------------------------------------------------------
// Store multiple 3-element structures from three consecutive registers
//------------------------------------------------------------------------------
st3 {v0.16b, v1.16b, v2.16b}, [x0]
st3 {v15.8h, v16.8h, v17.8h}, [x15]
st3 {v31.4s, v0.4s, v1.4s}, [sp]
st3 {v0.2d, v1.2d, v2.2d}, [x0]
st3 {v0.8b, v1.8b, v2.8b}, [x0]
st3 {v15.4h, v16.4h, v17.4h}, [x15]
st3 {v31.2s, v0.2s, v1.2s}, [sp]
// CHECK: st3 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x40,0x00,0x4c]
// CHECK: st3 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x45,0x00,0x4c]
// CHECK: st3 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x4b,0x00,0x4c]
// CHECK: st3 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x4c,0x00,0x4c]
// CHECK: st3 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x40,0x00,0x0c]
// CHECK: st3 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x45,0x00,0x0c]
// CHECK: st3 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x4b,0x00,0x0c]
st3 { v0.16b, v1.16b, v2.16b }, [x0]
st3 { v15.8h, v16.8h, v17.8h }, [x15]
st3 { v31.4s, v0.4s, v1.4s }, [sp]
st3 { v0.2d, v1.2d, v2.2d }, [x0]
st3 { v0.8b, v1.8b, v2.8b }, [x0]
st3 { v15.4h, v16.4h, v17.4h }, [x15]
st3 { v31.2s, v0.2s, v1.2s }, [sp]
// CHECK: st3 { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0x40,0x00,0x4c]
// CHECK: st3 { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0x45,0x00,0x4c]
// CHECK: st3 { v31.4s, v0.4s, v1.4s }, [sp] // encoding: [0xff,0x4b,0x00,0x4c]
// CHECK: st3 { v0.2d, v1.2d, v2.2d }, [x0] // encoding: [0x00,0x4c,0x00,0x4c]
// CHECK: st3 { v0.8b, v1.8b, v2.8b }, [x0] // encoding: [0x00,0x40,0x00,0x0c]
// CHECK: st3 { v15.4h, v16.4h, v17.4h }, [x15] // encoding: [0xef,0x45,0x00,0x0c]
// CHECK: st3 { v31.2s, v0.2s, v1.2s }, [sp] // encoding: [0xff,0x4b,0x00,0x0c]
st3 {v0.16b-v2.16b}, [x0]
st3 {v15.8h-v17.8h}, [x15]
st3 {v31.4s-v1.4s}, [sp]
st3 {v0.2d-v2.2d}, [x0]
st3 {v0.8b-v2.8b}, [x0]
st3 {v15.4h-v17.4h}, [x15]
st3 {v31.2s-v1.2s}, [sp]
// CHECK: st3 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x40,0x00,0x4c]
// CHECK: st3 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x45,0x00,0x4c]
// CHECK: st3 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x4b,0x00,0x4c]
// CHECK: st3 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x4c,0x00,0x4c]
// CHECK: st3 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x40,0x00,0x0c]
// CHECK: st3 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x45,0x00,0x0c]
// CHECK: st3 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x4b,0x00,0x0c]
st3 { v0.16b-v2.16b }, [x0]
st3 { v15.8h-v17.8h }, [x15]
st3 { v31.4s-v1.4s }, [sp]
st3 { v0.2d-v2.2d }, [x0]
st3 { v0.8b-v2.8b }, [x0]
st3 { v15.4h-v17.4h }, [x15]
st3 { v31.2s-v1.2s }, [sp]
// CHECK: st3 { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0x40,0x00,0x4c]
// CHECK: st3 { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0x45,0x00,0x4c]
// CHECK: st3 { v31.4s, v0.4s, v1.4s }, [sp] // encoding: [0xff,0x4b,0x00,0x4c]
// CHECK: st3 { v0.2d, v1.2d, v2.2d }, [x0] // encoding: [0x00,0x4c,0x00,0x4c]
// CHECK: st3 { v0.8b, v1.8b, v2.8b }, [x0] // encoding: [0x00,0x40,0x00,0x0c]
// CHECK: st3 { v15.4h, v16.4h, v17.4h }, [x15] // encoding: [0xef,0x45,0x00,0x0c]
// CHECK: st3 { v31.2s, v0.2s, v1.2s }, [sp] // encoding: [0xff,0x4b,0x00,0x0c]
//------------------------------------------------------------------------------
// Store multiple 4-element structures from four consecutive registers
//------------------------------------------------------------------------------
st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0]
st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15]
st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp]
st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0]
st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0]
st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15]
st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp]
// CHECK: st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x00,0x00,0x4c]
// CHECK: st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x05,0x00,0x4c]
// CHECK: st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x0b,0x00,0x4c]
// CHECK: st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x0c,0x00,0x4c]
// CHECK: st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x00,0x00,0x0c]
// CHECK: st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x05,0x00,0x0c]
// CHECK: st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x0b,0x00,0x0c]
st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]
st4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]
st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]
st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]
st4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]
st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]
// CHECK: st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0x00,0x00,0x4c]
// CHECK: st4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0x05,0x00,0x4c]
// CHECK: st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] // encoding: [0xff,0x0b,0x00,0x4c]
// CHECK: st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] // encoding: [0x00,0x0c,0x00,0x4c]
// CHECK: st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x00,0x00,0x0c]
// CHECK: st4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] // encoding: [0xef,0x05,0x00,0x0c]
// CHECK: st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] // encoding: [0xff,0x0b,0x00,0x0c]
st4 {v0.16b-v3.16b}, [x0]
st4 {v15.8h-v18.8h}, [x15]
st4 {v31.4s-v2.4s}, [sp]
st4 {v0.2d-v3.2d}, [x0]
st4 {v0.8b-v3.8b}, [x0]
st4 {v15.4h-v18.4h}, [x15]
st4 {v31.2s-v2.2s}, [sp]
// CHECK: st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x00,0x00,0x4c]
// CHECK: st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x05,0x00,0x4c]
// CHECK: st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x0b,0x00,0x4c]
// CHECK: st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x0c,0x00,0x4c]
// CHECK: st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x00,0x00,0x0c]
// CHECK: st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x05,0x00,0x0c]
// CHECK: st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x0b,0x00,0x0c]
st4 { v0.16b-v3.16b }, [x0]
st4 { v15.8h-v18.8h }, [x15]
st4 { v31.4s-v2.4s }, [sp]
st4 { v0.2d-v3.2d }, [x0]
st4 { v0.8b-v3.8b }, [x0]
st4 { v15.4h-v18.4h }, [x15]
st4 { v31.2s-v2.2s }, [sp]
// CHECK: st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0x00,0x00,0x4c]
// CHECK: st4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0x05,0x00,0x4c]
// CHECK: st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] // encoding: [0xff,0x0b,0x00,0x4c]
// CHECK: st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] // encoding: [0x00,0x0c,0x00,0x4c]
// CHECK: st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x00,0x00,0x0c]
// CHECK: st4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] // encoding: [0xef,0x05,0x00,0x0c]
// CHECK: st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] // encoding: [0xff,0x0b,0x00,0x0c]
//------------------------------------------------------------------------------
// Load multiple 1-element structures to one register
//------------------------------------------------------------------------------
ld1 {v0.16b}, [x0]
ld1 {v15.8h}, [x15]
ld1 {v31.4s}, [sp]
ld1 {v0.2d}, [x0]
ld1 {v0.8b}, [x0]
ld1 {v15.4h}, [x15]
ld1 {v31.2s}, [sp]
ld1 {v0.1d}, [x0]
// CHECK: ld1 {v0.16b}, [x0] // encoding: [0x00,0x70,0x40,0x4c]
// CHECK: ld1 {v15.8h}, [x15] // encoding: [0xef,0x75,0x40,0x4c]
// CHECK: ld1 {v31.4s}, [sp] // encoding: [0xff,0x7b,0x40,0x4c]
// CHECK: ld1 {v0.2d}, [x0] // encoding: [0x00,0x7c,0x40,0x4c]
// CHECK: ld1 {v0.8b}, [x0] // encoding: [0x00,0x70,0x40,0x0c]
// CHECK: ld1 {v15.4h}, [x15] // encoding: [0xef,0x75,0x40,0x0c]
// CHECK: ld1 {v31.2s}, [sp] // encoding: [0xff,0x7b,0x40,0x0c]
// CHECK: ld1 {v0.1d}, [x0] // encoding: [0x00,0x7c,0x40,0x0c]
ld1 { v0.16b }, [x0]
ld1 { v15.8h }, [x15]
ld1 { v31.4s }, [sp]
ld1 { v0.2d }, [x0]
ld1 { v0.8b }, [x0]
ld1 { v15.4h }, [x15]
ld1 { v31.2s }, [sp]
ld1 { v0.1d }, [x0]
// CHECK: ld1 { v0.16b }, [x0] // encoding: [0x00,0x70,0x40,0x4c]
// CHECK: ld1 { v15.8h }, [x15] // encoding: [0xef,0x75,0x40,0x4c]
// CHECK: ld1 { v31.4s }, [sp] // encoding: [0xff,0x7b,0x40,0x4c]
// CHECK: ld1 { v0.2d }, [x0] // encoding: [0x00,0x7c,0x40,0x4c]
// CHECK: ld1 { v0.8b }, [x0] // encoding: [0x00,0x70,0x40,0x0c]
// CHECK: ld1 { v15.4h }, [x15] // encoding: [0xef,0x75,0x40,0x0c]
// CHECK: ld1 { v31.2s }, [sp] // encoding: [0xff,0x7b,0x40,0x0c]
// CHECK: ld1 { v0.1d }, [x0] // encoding: [0x00,0x7c,0x40,0x0c]
//------------------------------------------------------------------------------
// Load multiple 1-element structures to two consecutive registers
//------------------------------------------------------------------------------
ld1 {v0.16b, v1.16b}, [x0]
ld1 {v15.8h, v16.8h}, [x15]
ld1 {v31.4s, v0.4s}, [sp]
ld1 {v0.2d, v1.2d}, [x0]
ld1 {v0.8b, v1.8b}, [x0]
ld1 {v15.4h, v16.4h}, [x15]
ld1 {v31.2s, v0.2s}, [sp]
ld1 {v0.1d, v1.1d}, [x0]
// CHECK: ld1 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0xa0,0x40,0x4c]
// CHECK: ld1 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0xa5,0x40,0x4c]
// CHECK: ld1 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0xab,0x40,0x4c]
// CHECK: ld1 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0xac,0x40,0x4c]
// CHECK: ld1 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0xa0,0x40,0x0c]
// CHECK: ld1 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0xa5,0x40,0x0c]
// CHECK: ld1 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0xab,0x40,0x0c]
// CHECK: ld1 {v0.1d, v1.1d}, [x0] // encoding: [0x00,0xac,0x40,0x0c]
ld1 { v0.16b, v1.16b }, [x0]
ld1 { v15.8h, v16.8h }, [x15]
ld1 { v31.4s, v0.4s }, [sp]
ld1 { v0.2d, v1.2d }, [x0]
ld1 { v0.8b, v1.8b }, [x0]
ld1 { v15.4h, v16.4h }, [x15]
ld1 { v31.2s, v0.2s }, [sp]
ld1 { v0.1d, v1.1d }, [x0]
// CHECK: ld1 { v0.16b, v1.16b }, [x0] // encoding: [0x00,0xa0,0x40,0x4c]
// CHECK: ld1 { v15.8h, v16.8h }, [x15] // encoding: [0xef,0xa5,0x40,0x4c]
// CHECK: ld1 { v31.4s, v0.4s }, [sp] // encoding: [0xff,0xab,0x40,0x4c]
// CHECK: ld1 { v0.2d, v1.2d }, [x0] // encoding: [0x00,0xac,0x40,0x4c]
// CHECK: ld1 { v0.8b, v1.8b }, [x0] // encoding: [0x00,0xa0,0x40,0x0c]
// CHECK: ld1 { v15.4h, v16.4h }, [x15] // encoding: [0xef,0xa5,0x40,0x0c]
// CHECK: ld1 { v31.2s, v0.2s }, [sp] // encoding: [0xff,0xab,0x40,0x0c]
// CHECK: ld1 { v0.1d, v1.1d }, [x0] // encoding: [0x00,0xac,0x40,0x0c]
ld1 {v0.16b-v1.16b}, [x0]
ld1 {v15.8h-v16.8h}, [x15]
ld1 {v31.4s-v0.4s}, [sp]
ld1 {v0.2d-v1.2d}, [x0]
ld1 {v0.8b-v1.8b}, [x0]
ld1 {v15.4h-v16.4h}, [x15]
ld1 {v31.2s-v0.2s}, [sp]
ld1 {v0.1d-v1.1d}, [x0]
// CHECK: ld1 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0xa0,0x40,0x4c]
// CHECK: ld1 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0xa5,0x40,0x4c]
// CHECK: ld1 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0xab,0x40,0x4c]
// CHECK: ld1 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0xac,0x40,0x4c]
// CHECK: ld1 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0xa0,0x40,0x0c]
// CHECK: ld1 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0xa5,0x40,0x0c]
// CHECK: ld1 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0xab,0x40,0x0c]
// CHECK: ld1 {v0.1d, v1.1d}, [x0] // encoding: [0x00,0xac,0x40,0x0c]
ld1 { v0.16b-v1.16b }, [x0]
ld1 { v15.8h-v16.8h }, [x15]
ld1 { v31.4s-v0.4s }, [sp]
ld1 { v0.2d-v1.2d }, [x0]
ld1 { v0.8b-v1.8b }, [x0]
ld1 { v15.4h-v16.4h }, [x15]
ld1 { v31.2s-v0.2s }, [sp]
ld1 { v0.1d-v1.1d }, [x0]
// CHECK: ld1 { v0.16b, v1.16b }, [x0] // encoding: [0x00,0xa0,0x40,0x4c]
// CHECK: ld1 { v15.8h, v16.8h }, [x15] // encoding: [0xef,0xa5,0x40,0x4c]
// CHECK: ld1 { v31.4s, v0.4s }, [sp] // encoding: [0xff,0xab,0x40,0x4c]
// CHECK: ld1 { v0.2d, v1.2d }, [x0] // encoding: [0x00,0xac,0x40,0x4c]
// CHECK: ld1 { v0.8b, v1.8b }, [x0] // encoding: [0x00,0xa0,0x40,0x0c]
// CHECK: ld1 { v15.4h, v16.4h }, [x15] // encoding: [0xef,0xa5,0x40,0x0c]
// CHECK: ld1 { v31.2s, v0.2s }, [sp] // encoding: [0xff,0xab,0x40,0x0c]
// CHECK: ld1 { v0.1d, v1.1d }, [x0] // encoding: [0x00,0xac,0x40,0x0c]
//------------------------------------------------------------------------------
// Load multiple 1-element structures to three consecutive registers
//------------------------------------------------------------------------------
ld1 {v0.16b, v1.16b, v2.16b}, [x0]
ld1 {v15.8h, v16.8h, v17.8h}, [x15]
ld1 {v31.4s, v0.4s, v1.4s}, [sp]
ld1 {v0.2d, v1.2d, v2.2d}, [x0]
ld1 {v0.8b, v1.8b, v2.8b}, [x0]
ld1 {v15.4h, v16.4h, v17.4h}, [x15]
ld1 {v31.2s, v0.2s, v1.2s}, [sp]
ld1 {v0.1d, v1.1d, v2.1d}, [x0]
// CHECK: ld1 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x60,0x40,0x4c]
// CHECK: ld1 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x65,0x40,0x4c]
// CHECK: ld1 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x6b,0x40,0x4c]
// CHECK: ld1 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x6c,0x40,0x4c]
// CHECK: ld1 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x60,0x40,0x0c]
// CHECK: ld1 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x65,0x40,0x0c]
// CHECK: ld1 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x6b,0x40,0x0c]
// CHECK: ld1 {v0.1d, v1.1d, v2.1d}, [x0] // encoding: [0x00,0x6c,0x40,0x0c]
ld1 { v0.16b, v1.16b, v2.16b }, [x0]
ld1 { v15.8h, v16.8h, v17.8h }, [x15]
ld1 { v31.4s, v0.4s, v1.4s }, [sp]
ld1 { v0.2d, v1.2d, v2.2d }, [x0]
ld1 { v0.8b, v1.8b, v2.8b }, [x0]
ld1 { v15.4h, v16.4h, v17.4h }, [x15]
ld1 { v31.2s, v0.2s, v1.2s }, [sp]
ld1 { v0.1d, v1.1d, v2.1d }, [x0]
// CHECK: ld1 { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0x60,0x40,0x4c]
// CHECK: ld1 { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0x65,0x40,0x4c]
// CHECK: ld1 { v31.4s, v0.4s, v1.4s }, [sp] // encoding: [0xff,0x6b,0x40,0x4c]
// CHECK: ld1 { v0.2d, v1.2d, v2.2d }, [x0] // encoding: [0x00,0x6c,0x40,0x4c]
// CHECK: ld1 { v0.8b, v1.8b, v2.8b }, [x0] // encoding: [0x00,0x60,0x40,0x0c]
// CHECK: ld1 { v15.4h, v16.4h, v17.4h }, [x15] // encoding: [0xef,0x65,0x40,0x0c]
// CHECK: ld1 { v31.2s, v0.2s, v1.2s }, [sp] // encoding: [0xff,0x6b,0x40,0x0c]
// CHECK: ld1 { v0.1d, v1.1d, v2.1d }, [x0] // encoding: [0x00,0x6c,0x40,0x0c]
ld1 {v0.16b-v2.16b}, [x0]
ld1 {v15.8h-v17.8h}, [x15]
ld1 {v31.4s-v1.4s}, [sp]
ld1 {v0.2d-v2.2d}, [x0]
ld1 {v0.8b-v2.8b}, [x0]
ld1 {v15.4h-v17.4h}, [x15]
ld1 {v31.2s-v1.2s}, [sp]
ld1 {v0.1d-v2.1d}, [x0]
// CHECK: ld1 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x60,0x40,0x4c]
// CHECK: ld1 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x65,0x40,0x4c]
// CHECK: ld1 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x6b,0x40,0x4c]
// CHECK: ld1 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x6c,0x40,0x4c]
// CHECK: ld1 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x60,0x40,0x0c]
// CHECK: ld1 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x65,0x40,0x0c]
// CHECK: ld1 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x6b,0x40,0x0c]
// CHECK: ld1 {v0.1d, v1.1d, v2.1d}, [x0] // encoding: [0x00,0x6c,0x40,0x0c]
ld1 { v0.16b-v2.16b }, [x0]
ld1 { v15.8h-v17.8h }, [x15]
ld1 { v31.4s-v1.4s }, [sp]
ld1 { v0.2d-v2.2d }, [x0]
ld1 { v0.8b-v2.8b }, [x0]
ld1 { v15.4h-v17.4h }, [x15]
ld1 { v31.2s-v1.2s }, [sp]
ld1 { v0.1d-v2.1d }, [x0]
// CHECK: ld1 { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0x60,0x40,0x4c]
// CHECK: ld1 { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0x65,0x40,0x4c]
// CHECK: ld1 { v31.4s, v0.4s, v1.4s }, [sp] // encoding: [0xff,0x6b,0x40,0x4c]
// CHECK: ld1 { v0.2d, v1.2d, v2.2d }, [x0] // encoding: [0x00,0x6c,0x40,0x4c]
// CHECK: ld1 { v0.8b, v1.8b, v2.8b }, [x0] // encoding: [0x00,0x60,0x40,0x0c]
// CHECK: ld1 { v15.4h, v16.4h, v17.4h }, [x15] // encoding: [0xef,0x65,0x40,0x0c]
// CHECK: ld1 { v31.2s, v0.2s, v1.2s }, [sp] // encoding: [0xff,0x6b,0x40,0x0c]
// CHECK: ld1 { v0.1d, v1.1d, v2.1d }, [x0] // encoding: [0x00,0x6c,0x40,0x0c]
//------------------------------------------------------------------------------
// Load multiple 1-element structures to four consecutive registers
//------------------------------------------------------------------------------
ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0]
ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15]
ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp]
ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0]
ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0]
ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15]
ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp]
ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0]
// CHECK: ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x20,0x40,0x4c]
// CHECK: ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x25,0x40,0x4c]
// CHECK: ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x2b,0x40,0x4c]
// CHECK: ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x2c,0x40,0x4c]
// CHECK: ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x20,0x40,0x0c]
// CHECK: ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x25,0x40,0x0c]
// CHECK: ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x2b,0x40,0x0c]
// CHECK: ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] // encoding: [0x00,0x2c,0x40,0x0c]
ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]
ld1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]
ld1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]
ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]
ld1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]
ld1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]
ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0]
// CHECK: ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0x20,0x40,0x4c]
// CHECK: ld1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0x25,0x40,0x4c]
// CHECK: ld1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] // encoding: [0xff,0x2b,0x40,0x4c]
// CHECK: ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] // encoding: [0x00,0x2c,0x40,0x4c]
// CHECK: ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x20,0x40,0x0c]
// CHECK: ld1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] // encoding: [0xef,0x25,0x40,0x0c]
// CHECK: ld1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] // encoding: [0xff,0x2b,0x40,0x0c]
// CHECK: ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0] // encoding: [0x00,0x2c,0x40,0x0c]
ld1 {v0.16b-v3.16b}, [x0]
ld1 {v15.8h-v18.8h}, [x15]
ld1 {v31.4s-v2.4s}, [sp]
ld1 {v0.2d-v3.2d}, [x0]
ld1 {v0.8b-v3.8b}, [x0]
ld1 {v15.4h-v18.4h}, [x15]
ld1 {v31.2s-v2.2s}, [sp]
ld1 {v0.1d-v3.1d}, [x0]
// CHECK: ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x20,0x40,0x4c]
// CHECK: ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x25,0x40,0x4c]
// CHECK: ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x2b,0x40,0x4c]
// CHECK: ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x2c,0x40,0x4c]
// CHECK: ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x20,0x40,0x0c]
// CHECK: ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x25,0x40,0x0c]
// CHECK: ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x2b,0x40,0x0c]
// CHECK: ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] // encoding: [0x00,0x2c,0x40,0x0c]
ld1 { v0.16b-v3.16b }, [x0]
ld1 { v15.8h-v18.8h }, [x15]
ld1 { v31.4s-v2.4s }, [sp]
ld1 { v0.2d-v3.2d }, [x0]
ld1 { v0.8b-v3.8b }, [x0]
ld1 { v15.4h-v18.4h }, [x15]
ld1 { v31.2s-v2.2s }, [sp]
ld1 { v0.1d-v3.1d }, [x0]
// CHECK: ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0x20,0x40,0x4c]
// CHECK: ld1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0x25,0x40,0x4c]
// CHECK: ld1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] // encoding: [0xff,0x2b,0x40,0x4c]
// CHECK: ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] // encoding: [0x00,0x2c,0x40,0x4c]
// CHECK: ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x20,0x40,0x0c]
// CHECK: ld1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] // encoding: [0xef,0x25,0x40,0x0c]
// CHECK: ld1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] // encoding: [0xff,0x2b,0x40,0x0c]
// CHECK: ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0] // encoding: [0x00,0x2c,0x40,0x0c]
//------------------------------------------------------------------------------
// Load multiple 4-element structures to two consecutive registers
//------------------------------------------------------------------------------
ld2 {v0.16b, v1.16b}, [x0]
ld2 {v15.8h, v16.8h}, [x15]
ld2 {v31.4s, v0.4s}, [sp]
ld2 {v0.2d, v1.2d}, [x0]
ld2 {v0.8b, v1.8b}, [x0]
ld2 {v15.4h, v16.4h}, [x15]
ld2 {v31.2s, v0.2s}, [sp]
// CHECK: ld2 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0x80,0x40,0x4c]
// CHECK: ld2 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0x85,0x40,0x4c]
// CHECK: ld2 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0x8b,0x40,0x4c]
// CHECK: ld2 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0x8c,0x40,0x4c]
// CHECK: ld2 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0x80,0x40,0x0c]
// CHECK: ld2 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0x85,0x40,0x0c]
// CHECK: ld2 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0x8b,0x40,0x0c]
ld2 { v0.16b, v1.16b }, [x0]
ld2 { v15.8h, v16.8h }, [x15]
ld2 { v31.4s, v0.4s }, [sp]
ld2 { v0.2d, v1.2d }, [x0]
ld2 { v0.8b, v1.8b }, [x0]
ld2 { v15.4h, v16.4h }, [x15]
ld2 { v31.2s, v0.2s }, [sp]
// CHECK: ld2 { v0.16b, v1.16b }, [x0] // encoding: [0x00,0x80,0x40,0x4c]
// CHECK: ld2 { v15.8h, v16.8h }, [x15] // encoding: [0xef,0x85,0x40,0x4c]
// CHECK: ld2 { v31.4s, v0.4s }, [sp] // encoding: [0xff,0x8b,0x40,0x4c]
// CHECK: ld2 { v0.2d, v1.2d }, [x0] // encoding: [0x00,0x8c,0x40,0x4c]
// CHECK: ld2 { v0.8b, v1.8b }, [x0] // encoding: [0x00,0x80,0x40,0x0c]
// CHECK: ld2 { v15.4h, v16.4h }, [x15] // encoding: [0xef,0x85,0x40,0x0c]
// CHECK: ld2 { v31.2s, v0.2s }, [sp] // encoding: [0xff,0x8b,0x40,0x0c]
ld2 {v0.16b-v1.16b}, [x0]
ld2 {v15.8h-v16.8h}, [x15]
ld2 {v31.4s-v0.4s}, [sp]
ld2 {v0.2d-v1.2d}, [x0]
ld2 {v0.8b-v1.8b}, [x0]
ld2 {v15.4h-v16.4h}, [x15]
ld2 {v31.2s-v0.2s}, [sp]
// CHECK: ld2 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0x80,0x40,0x4c]
// CHECK: ld2 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0x85,0x40,0x4c]
// CHECK: ld2 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0x8b,0x40,0x4c]
// CHECK: ld2 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0x8c,0x40,0x4c]
// CHECK: ld2 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0x80,0x40,0x0c]
// CHECK: ld2 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0x85,0x40,0x0c]
// CHECK: ld2 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0x8b,0x40,0x0c]
ld2 { v0.16b-v1.16b }, [x0]
ld2 { v15.8h-v16.8h }, [x15]
ld2 { v31.4s-v0.4s }, [sp]
ld2 { v0.2d-v1.2d }, [x0]
ld2 { v0.8b-v1.8b }, [x0]
ld2 { v15.4h-v16.4h }, [x15]
ld2 { v31.2s-v0.2s }, [sp]
// CHECK: ld2 { v0.16b, v1.16b }, [x0] // encoding: [0x00,0x80,0x40,0x4c]
// CHECK: ld2 { v15.8h, v16.8h }, [x15] // encoding: [0xef,0x85,0x40,0x4c]
// CHECK: ld2 { v31.4s, v0.4s }, [sp] // encoding: [0xff,0x8b,0x40,0x4c]
// CHECK: ld2 { v0.2d, v1.2d }, [x0] // encoding: [0x00,0x8c,0x40,0x4c]
// CHECK: ld2 { v0.8b, v1.8b }, [x0] // encoding: [0x00,0x80,0x40,0x0c]
// CHECK: ld2 { v15.4h, v16.4h }, [x15] // encoding: [0xef,0x85,0x40,0x0c]
// CHECK: ld2 { v31.2s, v0.2s }, [sp] // encoding: [0xff,0x8b,0x40,0x0c]
//------------------------------------------------------------------------------
// Load multiple 3-element structures to three consecutive registers
//------------------------------------------------------------------------------
ld3 {v0.16b, v1.16b, v2.16b}, [x0]
ld3 {v15.8h, v16.8h, v17.8h}, [x15]
ld3 {v31.4s, v0.4s, v1.4s}, [sp]
ld3 {v0.2d, v1.2d, v2.2d}, [x0]
ld3 {v0.8b, v1.8b, v2.8b}, [x0]
ld3 {v15.4h, v16.4h, v17.4h}, [x15]
ld3 {v31.2s, v0.2s, v1.2s}, [sp]
// CHECK: ld3 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x40,0x40,0x4c]
// CHECK: ld3 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x45,0x40,0x4c]
// CHECK: ld3 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x4b,0x40,0x4c]
// CHECK: ld3 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x4c,0x40,0x4c]
// CHECK: ld3 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x40,0x40,0x0c]
// CHECK: ld3 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x45,0x40,0x0c]
// CHECK: ld3 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x4b,0x40,0x0c]
ld3 { v0.16b, v1.16b, v2.16b }, [x0]
ld3 { v15.8h, v16.8h, v17.8h }, [x15]
ld3 { v31.4s, v0.4s, v1.4s }, [sp]
ld3 { v0.2d, v1.2d, v2.2d }, [x0]
ld3 { v0.8b, v1.8b, v2.8b }, [x0]
ld3 { v15.4h, v16.4h, v17.4h }, [x15]
ld3 { v31.2s, v0.2s, v1.2s }, [sp]
// CHECK: ld3 { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0x40,0x40,0x4c]
// CHECK: ld3 { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0x45,0x40,0x4c]
// CHECK: ld3 { v31.4s, v0.4s, v1.4s }, [sp] // encoding: [0xff,0x4b,0x40,0x4c]
// CHECK: ld3 { v0.2d, v1.2d, v2.2d }, [x0] // encoding: [0x00,0x4c,0x40,0x4c]
// CHECK: ld3 { v0.8b, v1.8b, v2.8b }, [x0] // encoding: [0x00,0x40,0x40,0x0c]
// CHECK: ld3 { v15.4h, v16.4h, v17.4h }, [x15] // encoding: [0xef,0x45,0x40,0x0c]
// CHECK: ld3 { v31.2s, v0.2s, v1.2s }, [sp] // encoding: [0xff,0x4b,0x40,0x0c]
ld3 {v0.16b-v2.16b}, [x0]
ld3 {v15.8h-v17.8h}, [x15]
ld3 {v31.4s-v1.4s}, [sp]
ld3 {v0.2d-v2.2d}, [x0]
ld3 {v0.8b-v2.8b}, [x0]
ld3 {v15.4h-v17.4h}, [x15]
ld3 {v31.2s-v1.2s}, [sp]
// CHECK: ld3 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x40,0x40,0x4c]
// CHECK: ld3 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x45,0x40,0x4c]
// CHECK: ld3 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x4b,0x40,0x4c]
// CHECK: ld3 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x4c,0x40,0x4c]
// CHECK: ld3 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x40,0x40,0x0c]
// CHECK: ld3 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x45,0x40,0x0c]
// CHECK: ld3 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x4b,0x40,0x0c]
ld3 { v0.16b-v2.16b }, [x0]
ld3 { v15.8h-v17.8h }, [x15]
ld3 { v31.4s-v1.4s }, [sp]
ld3 { v0.2d-v2.2d }, [x0]
ld3 { v0.8b-v2.8b }, [x0]
ld3 { v15.4h-v17.4h }, [x15]
ld3 { v31.2s-v1.2s }, [sp]
// CHECK: ld3 { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0x40,0x40,0x4c]
// CHECK: ld3 { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0x45,0x40,0x4c]
// CHECK: ld3 { v31.4s, v0.4s, v1.4s }, [sp] // encoding: [0xff,0x4b,0x40,0x4c]
// CHECK: ld3 { v0.2d, v1.2d, v2.2d }, [x0] // encoding: [0x00,0x4c,0x40,0x4c]
// CHECK: ld3 { v0.8b, v1.8b, v2.8b }, [x0] // encoding: [0x00,0x40,0x40,0x0c]
// CHECK: ld3 { v15.4h, v16.4h, v17.4h }, [x15] // encoding: [0xef,0x45,0x40,0x0c]
// CHECK: ld3 { v31.2s, v0.2s, v1.2s }, [sp] // encoding: [0xff,0x4b,0x40,0x0c]
//------------------------------------------------------------------------------
// Load multiple 4-element structures to four consecutive registers
//------------------------------------------------------------------------------
ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0]
ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15]
ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp]
ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0]
ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0]
ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15]
ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp]
// CHECK: ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x00,0x40,0x4c]
// CHECK: ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x05,0x40,0x4c]
// CHECK: ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x0b,0x40,0x4c]
// CHECK: ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x0c,0x40,0x4c]
// CHECK: ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x00,0x40,0x0c]
// CHECK: ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x05,0x40,0x0c]
// CHECK: ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x0b,0x40,0x0c]
ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]
ld4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]
ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]
ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]
ld4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]
ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]
// CHECK: ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0x00,0x40,0x4c]
// CHECK: ld4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0x05,0x40,0x4c]
// CHECK: ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] // encoding: [0xff,0x0b,0x40,0x4c]
// CHECK: ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] // encoding: [0x00,0x0c,0x40,0x4c]
// CHECK: ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x00,0x40,0x0c]
// CHECK: ld4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] // encoding: [0xef,0x05,0x40,0x0c]
// CHECK: ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] // encoding: [0xff,0x0b,0x40,0x0c]
ld4 {v0.16b-v3.16b}, [x0]
ld4 {v15.8h-v18.8h}, [x15]
ld4 {v31.4s-v2.4s}, [sp]
ld4 {v0.2d-v3.2d}, [x0]
ld4 {v0.8b-v3.8b}, [x0]
ld4 {v15.4h-v18.4h}, [x15]
ld4 {v31.2s-v2.2s}, [sp]
// CHECK: ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x00,0x40,0x4c]
// CHECK: ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x05,0x40,0x4c]
// CHECK: ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x0b,0x40,0x4c]
// CHECK: ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x0c,0x40,0x4c]
// CHECK: ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x00,0x40,0x0c]
// CHECK: ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x05,0x40,0x0c]
// CHECK: ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x0b,0x40,0x0c]
ld4 { v0.16b-v3.16b }, [x0]
ld4 { v15.8h-v18.8h }, [x15]
ld4 { v31.4s-v2.4s }, [sp]
ld4 { v0.2d-v3.2d }, [x0]
ld4 { v0.8b-v3.8b }, [x0]
ld4 { v15.4h-v18.4h }, [x15]
ld4 { v31.2s-v2.2s }, [sp]
// CHECK: ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0x00,0x40,0x4c]
// CHECK: ld4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0x05,0x40,0x4c]
// CHECK: ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] // encoding: [0xff,0x0b,0x40,0x4c]
// CHECK: ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] // encoding: [0x00,0x0c,0x40,0x4c]
// CHECK: ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x00,0x40,0x0c]
// CHECK: ld4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] // encoding: [0xef,0x05,0x40,0x0c]
// CHECK: ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] // encoding: [0xff,0x0b,0x40,0x0c]

512
test/MC/AArch64/neon-simd-ldst-one-elem.s
View File

@ -5,321 +5,321 @@
//------------------------------------------------------------------------------
// Load single 1-element structure to all lanes of 1 register
//------------------------------------------------------------------------------
ld1r {v0.16b}, [x0]
ld1r {v15.8h}, [x15]
ld1r {v31.4s}, [sp]
ld1r {v0.2d}, [x0]
ld1r {v0.8b}, [x0]
ld1r {v15.4h}, [x15]
ld1r {v31.2s}, [sp]
ld1r {v0.1d}, [x0]
// CHECK: ld1r {v0.16b}, [x0] // encoding: [0x00,0xc0,0x40,0x4d]
// CHECK: ld1r {v15.8h}, [x15] // encoding: [0xef,0xc5,0x40,0x4d]
// CHECK: ld1r {v31.4s}, [sp] // encoding: [0xff,0xcb,0x40,0x4d]
// CHECK: ld1r {v0.2d}, [x0] // encoding: [0x00,0xcc,0x40,0x4d]
// CHECK: ld1r {v0.8b}, [x0] // encoding: [0x00,0xc0,0x40,0x0d]
// CHECK: ld1r {v15.4h}, [x15] // encoding: [0xef,0xc5,0x40,0x0d]
// CHECK: ld1r {v31.2s}, [sp] // encoding: [0xff,0xcb,0x40,0x0d]
// CHECK: ld1r {v0.1d}, [x0] // encoding: [0x00,0xcc,0x40,0x0d]
ld1r { v0.16b }, [x0]
ld1r { v15.8h }, [x15]
ld1r { v31.4s }, [sp]
ld1r { v0.2d }, [x0]
ld1r { v0.8b }, [x0]
ld1r { v15.4h }, [x15]
ld1r { v31.2s }, [sp]
ld1r { v0.1d }, [x0]
// CHECK: ld1r { v0.16b }, [x0] // encoding: [0x00,0xc0,0x40,0x4d]
// CHECK: ld1r { v15.8h }, [x15] // encoding: [0xef,0xc5,0x40,0x4d]
// CHECK: ld1r { v31.4s }, [sp] // encoding: [0xff,0xcb,0x40,0x4d]
// CHECK: ld1r { v0.2d }, [x0] // encoding: [0x00,0xcc,0x40,0x4d]
// CHECK: ld1r { v0.8b }, [x0] // encoding: [0x00,0xc0,0x40,0x0d]
// CHECK: ld1r { v15.4h }, [x15] // encoding: [0xef,0xc5,0x40,0x0d]
// CHECK: ld1r { v31.2s }, [sp] // encoding: [0xff,0xcb,0x40,0x0d]
// CHECK: ld1r { v0.1d }, [x0] // encoding: [0x00,0xcc,0x40,0x0d]
//------------------------------------------------------------------------------
// Load single N-element structure to all lanes of N consecutive
// registers (N = 2,3,4)
//------------------------------------------------------------------------------
ld2r {v0.16b, v1.16b}, [x0]
ld2r {v15.8h, v16.8h}, [x15]
ld2r {v31.4s, v0.4s}, [sp]
ld2r {v0.2d, v1.2d}, [x0]
ld2r {v0.8b, v1.8b}, [x0]
ld2r {v15.4h, v16.4h}, [x15]
ld2r {v31.2s, v0.2s}, [sp]
ld2r {v31.1d, v0.1d}, [sp]
// CHECK: ld2r {v0.16b, v1.16b}, [x0] // encoding: [0x00,0xc0,0x60,0x4d]
// CHECK: ld2r {v15.8h, v16.8h}, [x15] // encoding: [0xef,0xc5,0x60,0x4d]
// CHECK: ld2r {v31.4s, v0.4s}, [sp] // encoding: [0xff,0xcb,0x60,0x4d]
// CHECK: ld2r {v0.2d, v1.2d}, [x0] // encoding: [0x00,0xcc,0x60,0x4d]
// CHECK: ld2r {v0.8b, v1.8b}, [x0] // encoding: [0x00,0xc0,0x60,0x0d]
// CHECK: ld2r {v15.4h, v16.4h}, [x15] // encoding: [0xef,0xc5,0x60,0x0d]
// CHECK: ld2r {v31.2s, v0.2s}, [sp] // encoding: [0xff,0xcb,0x60,0x0d]
// CHECK: ld2r {v31.1d, v0.1d}, [sp] // encoding: [0xff,0xcf,0x60,0x0d]
ld2r { v0.16b, v1.16b }, [x0]
ld2r { v15.8h, v16.8h }, [x15]
ld2r { v31.4s, v0.4s }, [sp]
ld2r { v0.2d, v1.2d }, [x0]
ld2r { v0.8b, v1.8b }, [x0]
ld2r { v15.4h, v16.4h }, [x15]
ld2r { v31.2s, v0.2s }, [sp]
ld2r { v31.1d, v0.1d }, [sp]
// CHECK: ld2r { v0.16b, v1.16b }, [x0] // encoding: [0x00,0xc0,0x60,0x4d]
// CHECK: ld2r { v15.8h, v16.8h }, [x15] // encoding: [0xef,0xc5,0x60,0x4d]
// CHECK: ld2r { v31.4s, v0.4s }, [sp] // encoding: [0xff,0xcb,0x60,0x4d]
// CHECK: ld2r { v0.2d, v1.2d }, [x0] // encoding: [0x00,0xcc,0x60,0x4d]
// CHECK: ld2r { v0.8b, v1.8b }, [x0] // encoding: [0x00,0xc0,0x60,0x0d]
// CHECK: ld2r { v15.4h, v16.4h }, [x15] // encoding: [0xef,0xc5,0x60,0x0d]
// CHECK: ld2r { v31.2s, v0.2s }, [sp] // encoding: [0xff,0xcb,0x60,0x0d]
// CHECK: ld2r { v31.1d, v0.1d }, [sp] // encoding: [0xff,0xcf,0x60,0x0d]
ld3r {v0.16b, v1.16b, v2.16b}, [x0]
ld3r {v15.8h, v16.8h, v17.8h}, [x15]
ld3r {v31.4s, v0.4s, v1.4s}, [sp]
ld3r {v0.2d, v1.2d, v2.2d}, [x0]
ld3r {v0.8b, v1.8b, v2.8b}, [x0]
ld3r {v15.4h, v16.4h, v17.4h}, [x15]
ld3r {v31.2s, v0.2s, v1.2s}, [sp]
ld3r {v31.1d, v0.1d, v1.1d}, [sp]
// CHECK: ld3r {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0xe0,0x40,0x4d]
// CHECK: ld3r {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0xe5,0x40,0x4d]
// CHECK: ld3r {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0xeb,0x40,0x4d]
// CHECK: ld3r {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0xec,0x40,0x4d]
// CHECK: ld3r {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0xe0,0x40,0x0d]
// CHECK: ld3r {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0xe5,0x40,0x0d]
// CHECK: ld3r {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0xeb,0x40,0x0d]
// CHECK: ld3r {v31.1d, v0.1d, v1.1d}, [sp] // encoding: [0xff,0xef,0x40,0x0d]
ld3r { v0.16b, v1.16b, v2.16b }, [x0]
ld3r { v15.8h, v16.8h, v17.8h }, [x15]
ld3r { v31.4s, v0.4s, v1.4s }, [sp]
ld3r { v0.2d, v1.2d, v2.2d }, [x0]
ld3r { v0.8b, v1.8b, v2.8b }, [x0]
ld3r { v15.4h, v16.4h, v17.4h }, [x15]
ld3r { v31.2s, v0.2s, v1.2s }, [sp]
ld3r { v31.1d, v0.1d, v1.1d }, [sp]
// CHECK: ld3r { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0xe0,0x40,0x4d]
// CHECK: ld3r { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0xe5,0x40,0x4d]
// CHECK: ld3r { v31.4s, v0.4s, v1.4s }, [sp] // encoding: [0xff,0xeb,0x40,0x4d]
// CHECK: ld3r { v0.2d, v1.2d, v2.2d }, [x0] // encoding: [0x00,0xec,0x40,0x4d]
// CHECK: ld3r { v0.8b, v1.8b, v2.8b }, [x0] // encoding: [0x00,0xe0,0x40,0x0d]
// CHECK: ld3r { v15.4h, v16.4h, v17.4h }, [x15] // encoding: [0xef,0xe5,0x40,0x0d]
// CHECK: ld3r { v31.2s, v0.2s, v1.2s }, [sp] // encoding: [0xff,0xeb,0x40,0x0d]
// CHECK: ld3r { v31.1d, v0.1d, v1.1d }, [sp] // encoding: [0xff,0xef,0x40,0x0d]
ld4r {v0.16b, v1.16b, v2.16b, v3.16b}, [x0]
ld4r {v15.8h, v16.8h, v17.8h, v18.8h}, [x15]
ld4r {v31.4s, v0.4s, v1.4s, v2.4s}, [sp]
ld4r {v0.2d, v1.2d, v2.2d, v3.2d}, [x0]
ld4r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0]
ld4r {v15.4h, v16.4h, v17.4h, v18.4h}, [x15]
ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp]
ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp]
// CHECK: ld4r {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0xe0,0x60,0x4d]
// CHECK: ld4r {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0xe5,0x60,0x4d]
// CHECK: ld4r {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0xeb,0x60,0x4d]
// CHECK: ld4r {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0xec,0x60,0x4d]
// CHECK: ld4r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0xe0,0x60,0x0d]
// CHECK: ld4r {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0xe5,0x60,0x0d]
// CHECK: ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0xeb,0x60,0x0d]
// CHECK: ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp] // encoding: [0xff,0xef,0x60,0x0d]
ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]
ld4r { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]
ld4r { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]
ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]
ld4r { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]
ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]
ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp]
// CHECK: ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0xe0,0x60,0x4d]
// CHECK: ld4r { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0xe5,0x60,0x4d]
// CHECK: ld4r { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] // encoding: [0xff,0xeb,0x60,0x4d]
// CHECK: ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] // encoding: [0x00,0xec,0x60,0x4d]
// CHECK: ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0xe0,0x60,0x0d]
// CHECK: ld4r { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] // encoding: [0xef,0xe5,0x60,0x0d]
// CHECK: ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] // encoding: [0xff,0xeb,0x60,0x0d]
// CHECK: ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp] // encoding: [0xff,0xef,0x60,0x0d]
//------------------------------------------------------------------------------
// Load single 1-element structure to one lane of 1 register.
//------------------------------------------------------------------------------
ld1 {v0.b}[9], [x0]
ld1 {v15.h}[7], [x15]
ld1 {v31.s}[3], [sp]
ld1 {v0.d}[1], [x0]
// CHECK: ld1 {v0.b}[9], [x0] // encoding: [0x00,0x04,0x40,0x4d]
// CHECK: ld1 {v15.h}[7], [x15] // encoding: [0xef,0x59,0x40,0x4d]
// CHECK: ld1 {v31.s}[3], [sp] // encoding: [0xff,0x93,0x40,0x4d]
// CHECK: ld1 {v0.d}[1], [x0] // encoding: [0x00,0x84,0x40,0x4d]
ld1 { v0.b }[9], [x0]
ld1 { v15.h }[7], [x15]
ld1 { v31.s }[3], [sp]
ld1 { v0.d }[1], [x0]
// CHECK: ld1 { v0.b }[9], [x0] // encoding: [0x00,0x04,0x40,0x4d]
// CHECK: ld1 { v15.h }[7], [x15] // encoding: [0xef,0x59,0x40,0x4d]
// CHECK: ld1 { v31.s }[3], [sp] // encoding: [0xff,0x93,0x40,0x4d]
// CHECK: ld1 { v0.d }[1], [x0] // encoding: [0x00,0x84,0x40,0x4d]
//------------------------------------------------------------------------------
// Load single N-element structure to one lane of N consecutive registers
// (N = 2,3,4)
//------------------------------------------------------------------------------
ld2 {v0.b, v1.b}[9], [x0]
ld2 {v15.h, v16.h}[7], [x15]
ld2 {v31.s, v0.s}[3], [sp]
ld2 {v0.d, v1.d}[1], [x0]
// CHECK: ld2 {v0.b, v1.b}[9], [x0] // encoding: [0x00,0x04,0x60,0x4d]
// CHECK: ld2 {v15.h, v16.h}[7], [x15] // encoding: [0xef,0x59,0x60,0x4d]
// CHECK: ld2 {v31.s, v0.s}[3], [sp] // encoding: [0xff,0x93,0x60,0x4d]
// CHECK: ld2 {v0.d, v1.d}[1], [x0] // encoding: [0x00,0x84,0x60,0x4d]
ld2 { v0.b, v1.b }[9], [x0]
ld2 { v15.h, v16.h }[7], [x15]
ld2 { v31.s, v0.s }[3], [sp]
ld2 { v0.d, v1.d }[1], [x0]
// CHECK: ld2 { v0.b, v1.b }[9], [x0] // encoding: [0x00,0x04,0x60,0x4d]
// CHECK: ld2 { v15.h, v16.h }[7], [x15] // encoding: [0xef,0x59,0x60,0x4d]
// CHECK: ld2 { v31.s, v0.s }[3], [sp] // encoding: [0xff,0x93,0x60,0x4d]
// CHECK: ld2 { v0.d, v1.d }[1], [x0] // encoding: [0x00,0x84,0x60,0x4d]
ld3 {v0.b, v1.b, v2.b}[9], [x0]
ld3 {v15.h, v16.h, v17.h}[7], [x15]
ld3 {v31.s, v0.s, v1.s}[3], [sp]
ld3 {v0.d, v1.d, v2.d}[1], [x0]
// CHECK: ld3 {v0.b, v1.b, v2.b}[9], [x0] // encoding: [0x00,0x24,0x40,0x4d]
// CHECK: ld3 {v15.h, v16.h, v17.h}[7], [x15] // encoding: [0xef,0x79,0x40,0x4d]
// CHECK: ld3 {v31.s, v0.s, v1.s}[3], [sp] // encoding: [0xff,0xb3,0x40,0x4d]
// CHECK: ld3 {v0.d, v1.d, v2.d}[1], [x0] // encoding: [0x00,0xa4,0x40,0x4d]
ld3 { v0.b, v1.b, v2.b }[9], [x0]
ld3 { v15.h, v16.h, v17.h }[7], [x15]
ld3 { v31.s, v0.s, v1.s }[3], [sp]
ld3 { v0.d, v1.d, v2.d }[1], [x0]
// CHECK: ld3 { v0.b, v1.b, v2.b }[9], [x0] // encoding: [0x00,0x24,0x40,0x4d]
// CHECK: ld3 { v15.h, v16.h, v17.h }[7], [x15] // encoding: [0xef,0x79,0x40,0x4d]
// CHECK: ld3 { v31.s, v0.s, v1.s }[3], [sp] // encoding: [0xff,0xb3,0x40,0x4d]
// CHECK: ld3 { v0.d, v1.d, v2.d }[1], [x0] // encoding: [0x00,0xa4,0x40,0x4d]
ld4 {v0.b, v1.b, v2.b, v3.b}[9], [x0]
ld4 {v15.h, v16.h, v17.h, v18.h}[7], [x15]
ld4 {v31.s, v0.s, v1.s, v2.s}[3], [sp]
ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0]
// CHECK: ld4 {v0.b, v1.b, v2.b, v3.b}[9], [x0] // encoding: [0x00,0x24,0x60,0x4d]
// CHECK: ld4 {v15.h, v16.h, v17.h, v18.h}[7], [x15] // encoding: [0xef,0x79,0x60,0x4d]
// CHECK: ld4 {v31.s, v0.s, v1.s, v2.s}[3], [sp] // encoding: [0xff,0xb3,0x60,0x4d]
// CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0] // encoding: [0x00,0xa4,0x60,0x4d]
ld4 { v0.b, v1.b, v2.b, v3.b }[9], [x0]
ld4 { v15.h, v16.h, v17.h, v18.h }[7], [x15]
ld4 { v31.s, v0.s, v1.s, v2.s }[3], [sp]
ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0]
// CHECK: ld4 { v0.b, v1.b, v2.b, v3.b }[9], [x0] // encoding: [0x00,0x24,0x60,0x4d]
// CHECK: ld4 { v15.h, v16.h, v17.h, v18.h }[7], [x15] // encoding: [0xef,0x79,0x60,0x4d]
// CHECK: ld4 { v31.s, v0.s, v1.s, v2.s }[3], [sp] // encoding: [0xff,0xb3,0x60,0x4d]
// CHECK: ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0] // encoding: [0x00,0xa4,0x60,0x4d]
//------------------------------------------------------------------------------
// Store single 1-element structure from one lane of 1 register.
//------------------------------------------------------------------------------
st1 {v0.b}[9], [x0]
st1 {v15.h}[7], [x15]
st1 {v31.s}[3], [sp]
st1 {v0.d}[1], [x0]
// CHECK: st1 {v0.b}[9], [x0] // encoding: [0x00,0x04,0x00,0x4d]
// CHECK: st1 {v15.h}[7], [x15] // encoding: [0xef,0x59,0x00,0x4d]
// CHECK: st1 {v31.s}[3], [sp] // encoding: [0xff,0x93,0x00,0x4d]
// CHECK: st1 {v0.d}[1], [x0] // encoding: [0x00,0x84,0x00,0x4d]
st1 { v0.b }[9], [x0]
st1 { v15.h }[7], [x15]
st1 { v31.s }[3], [sp]
st1 { v0.d }[1], [x0]
// CHECK: st1 { v0.b }[9], [x0] // encoding: [0x00,0x04,0x00,0x4d]
// CHECK: st1 { v15.h }[7], [x15] // encoding: [0xef,0x59,0x00,0x4d]
// CHECK: st1 { v31.s }[3], [sp] // encoding: [0xff,0x93,0x00,0x4d]
// CHECK: st1 { v0.d }[1], [x0] // encoding: [0x00,0x84,0x00,0x4d]
//------------------------------------------------------------------------------
// Store single N-element structure from one lane of N consecutive registers
// (N = 2,3,4)
//------------------------------------------------------------------------------
st2 {v0.b, v1.b}[9], [x0]
st2 {v15.h, v16.h}[7], [x15]
st2 {v31.s, v0.s}[3], [sp]
st2 {v0.d, v1.d}[1], [x0]
// CHECK: st2 {v0.b, v1.b}[9], [x0] // encoding: [0x00,0x04,0x20,0x4d]
// CHECK: st2 {v15.h, v16.h}[7], [x15] // encoding: [0xef,0x59,0x20,0x4d]
// CHECK: st2 {v31.s, v0.s}[3], [sp] // encoding: [0xff,0x93,0x20,0x4d]
// CHECK: st2 {v0.d, v1.d}[1], [x0] // encoding: [0x00,0x84,0x20,0x4d]
st2 { v0.b, v1.b }[9], [x0]
st2 { v15.h, v16.h }[7], [x15]
st2 { v31.s, v0.s }[3], [sp]
st2 { v0.d, v1.d }[1], [x0]
// CHECK: st2 { v0.b, v1.b }[9], [x0] // encoding: [0x00,0x04,0x20,0x4d]
// CHECK: st2 { v15.h, v16.h }[7], [x15] // encoding: [0xef,0x59,0x20,0x4d]
// CHECK: st2 { v31.s, v0.s }[3], [sp] // encoding: [0xff,0x93,0x20,0x4d]
// CHECK: st2 { v0.d, v1.d }[1], [x0] // encoding: [0x00,0x84,0x20,0x4d]
st3 {v0.b, v1.b, v2.b}[9], [x0]
st3 {v15.h, v16.h, v17.h}[7], [x15]
st3 {v31.s, v0.s, v1.s}[3], [sp]
st3 {v0.d, v1.d, v2.d}[1], [x0]
// CHECK: st3 {v0.b, v1.b, v2.b}[9], [x0] // encoding: [0x00,0x24,0x00,0x4d]
// CHECK: st3 {v15.h, v16.h, v17.h}[7], [x15] // encoding: [0xef,0x79,0x00,0x4d]
// CHECK: st3 {v31.s, v0.s, v1.s}[3], [sp] // encoding: [0xff,0xb3,0x00,0x4d]
// CHECK: st3 {v0.d, v1.d, v2.d}[1], [x0] // encoding: [0x00,0xa4,0x00,0x4d]
st3 { v0.b, v1.b, v2.b }[9], [x0]
st3 { v15.h, v16.h, v17.h }[7], [x15]
st3 { v31.s, v0.s, v1.s }[3], [sp]
st3 { v0.d, v1.d, v2.d }[1], [x0]
// CHECK: st3 { v0.b, v1.b, v2.b }[9], [x0] // encoding: [0x00,0x24,0x00,0x4d]
// CHECK: st3 { v15.h, v16.h, v17.h }[7], [x15] // encoding: [0xef,0x79,0x00,0x4d]
// CHECK: st3 { v31.s, v0.s, v1.s }[3], [sp] // encoding: [0xff,0xb3,0x00,0x4d]
// CHECK: st3 { v0.d, v1.d, v2.d }[1], [x0] // encoding: [0x00,0xa4,0x00,0x4d]
st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0]
st4 {v15.h, v16.h, v17.h, v18.h}[7], [x15]
st4 {v31.s, v0.s, v1.s, v2.s}[3], [sp]
st4 {v0.d, v1.d, v2.d, v3.d}[1], [x0]
// CHECK: st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0] // encoding: [0x00,0x24,0x20,0x4d]
// CHECK: st4 {v15.h, v16.h, v17.h, v18.h}[7], [x15] // encoding: [0xef,0x79,0x20,0x4d]
// CHECK: st4 {v31.s, v0.s, v1.s, v2.s}[3], [sp] // encoding: [0xff,0xb3,0x20,0x4d]
// CHECK: st4 {v0.d, v1.d, v2.d, v3.d}[1], [x0] // encoding: [0x00,0xa4,0x20,0x4d]
st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0]
st4 { v15.h, v16.h, v17.h, v18.h }[7], [x15]
st4 { v31.s, v0.s, v1.s, v2.s }[3], [sp]
st4 { v0.d, v1.d, v2.d, v3.d }[1], [x0]
// CHECK: st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0] // encoding: [0x00,0x24,0x20,0x4d]
// CHECK: st4 { v15.h, v16.h, v17.h, v18.h }[7], [x15] // encoding: [0xef,0x79,0x20,0x4d]
// CHECK: st4 { v31.s, v0.s, v1.s, v2.s }[3], [sp] // encoding: [0xff,0xb3,0x20,0x4d]
// CHECK: st4 { v0.d, v1.d, v2.d, v3.d }[1], [x0] // encoding: [0x00,0xa4,0x20,0x4d]
//------------------------------------------------------------------------------
// Post-index oad single 1-element structure to all lanes of 1 register
//------------------------------------------------------------------------------
ld1r {v0.16b}, [x0], #1
ld1r {v15.8h}, [x15], #2
ld1r {v31.4s}, [sp], #4
ld1r {v0.2d}, [x0], #8
ld1r {v0.8b}, [x0], x0
ld1r {v15.4h}, [x15], x1
ld1r {v31.2s}, [sp], x2
ld1r {v0.1d}, [x0], x3
// CHECK: ld1r {v0.16b}, [x0], #1 // encoding: [0x00,0xc0,0xdf,0x4d]
// CHECK: ld1r {v15.8h}, [x15], #2 // encoding: [0xef,0xc5,0xdf,0x4d]
// CHECK: ld1r {v31.4s}, [sp], #4 // encoding: [0xff,0xcb,0xdf,0x4d]
// CHECK: ld1r {v0.2d}, [x0], #8 // encoding: [0x00,0xcc,0xdf,0x4d]
// CHECK: ld1r {v0.8b}, [x0], x0 // encoding: [0x00,0xc0,0xc0,0x0d]
// CHECK: ld1r {v15.4h}, [x15], x1 // encoding: [0xef,0xc5,0xc1,0x0d]
// CHECK: ld1r {v31.2s}, [sp], x2 // encoding: [0xff,0xcb,0xc2,0x0d]
// CHECK: ld1r {v0.1d}, [x0], x3 // encoding: [0x00,0xcc,0xc3,0x0d]
ld1r { v0.16b }, [x0], #1
ld1r { v15.8h }, [x15], #2
ld1r { v31.4s }, [sp], #4
ld1r { v0.2d }, [x0], #8
ld1r { v0.8b }, [x0], x0
ld1r { v15.4h }, [x15], x1
ld1r { v31.2s }, [sp], x2
ld1r { v0.1d }, [x0], x3
// CHECK: ld1r { v0.16b }, [x0], #1 // encoding: [0x00,0xc0,0xdf,0x4d]
// CHECK: ld1r { v15.8h }, [x15], #2 // encoding: [0xef,0xc5,0xdf,0x4d]
// CHECK: ld1r { v31.4s }, [sp], #4 // encoding: [0xff,0xcb,0xdf,0x4d]
// CHECK: ld1r { v0.2d }, [x0], #8 // encoding: [0x00,0xcc,0xdf,0x4d]
// CHECK: ld1r { v0.8b }, [x0], x0 // encoding: [0x00,0xc0,0xc0,0x0d]
// CHECK: ld1r { v15.4h }, [x15], x1 // encoding: [0xef,0xc5,0xc1,0x0d]
// CHECK: ld1r { v31.2s }, [sp], x2 // encoding: [0xff,0xcb,0xc2,0x0d]
// CHECK: ld1r { v0.1d }, [x0], x3 // encoding: [0x00,0xcc,0xc3,0x0d]
//------------------------------------------------------------------------------
// Post-index load single N-element structure to all lanes of N consecutive
// registers (N = 2,3,4)
//------------------------------------------------------------------------------
ld2r {v0.16b, v1.16b}, [x0], #2
ld2r {v15.8h, v16.8h}, [x15], #4
ld2r {v31.4s, v0.4s}, [sp], #8
ld2r {v0.2d, v1.2d}, [x0], #16
ld2r {v0.8b, v1.8b}, [x0], x6
ld2r {v15.4h, v16.4h}, [x15], x7
ld2r {v31.2s, v0.2s}, [sp], x9
ld2r {v31.1d, v0.1d}, [x0], x5
// CHECK: ld2r {v0.16b, v1.16b}, [x0], #2 // encoding: [0x00,0xc0,0xff,0x4d]
// CHECK: ld2r {v15.8h, v16.8h}, [x15], #4 // encoding: [0xef,0xc5,0xff,0x4d]
// CHECK: ld2r {v31.4s, v0.4s}, [sp], #8 // encoding: [0xff,0xcb,0xff,0x4d]
// CHECK: ld2r {v0.2d, v1.2d}, [x0], #16 // encoding: [0x00,0xcc,0xff,0x4d]
// CHECK: ld2r {v0.8b, v1.8b}, [x0], x6 // encoding: [0x00,0xc0,0xe6,0x0d]
// CHECK: ld2r {v15.4h, v16.4h}, [x15], x7 // encoding: [0xef,0xc5,0xe7,0x0d]
// CHECK: ld2r {v31.2s, v0.2s}, [sp], x9 // encoding: [0xff,0xcb,0xe9,0x0d]
// CHECK: ld2r {v31.1d, v0.1d}, [x0], x5 // encoding: [0x1f,0xcc,0xe5,0x0d]
ld2r { v0.16b, v1.16b }, [x0], #2
ld2r { v15.8h, v16.8h }, [x15], #4
ld2r { v31.4s, v0.4s }, [sp], #8
ld2r { v0.2d, v1.2d }, [x0], #16
ld2r { v0.8b, v1.8b }, [x0], x6
ld2r { v15.4h, v16.4h }, [x15], x7
ld2r { v31.2s, v0.2s }, [sp], x9
ld2r { v31.1d, v0.1d }, [x0], x5
// CHECK: ld2r { v0.16b, v1.16b }, [x0], #2 // encoding: [0x00,0xc0,0xff,0x4d]
// CHECK: ld2r { v15.8h, v16.8h }, [x15], #4 // encoding: [0xef,0xc5,0xff,0x4d]
// CHECK: ld2r { v31.4s, v0.4s }, [sp], #8 // encoding: [0xff,0xcb,0xff,0x4d]
// CHECK: ld2r { v0.2d, v1.2d }, [x0], #16 // encoding: [0x00,0xcc,0xff,0x4d]
// CHECK: ld2r { v0.8b, v1.8b }, [x0], x6 // encoding: [0x00,0xc0,0xe6,0x0d]
// CHECK: ld2r { v15.4h, v16.4h }, [x15], x7 // encoding: [0xef,0xc5,0xe7,0x0d]
// CHECK: ld2r { v31.2s, v0.2s }, [sp], x9 // encoding: [0xff,0xcb,0xe9,0x0d]
// CHECK: ld2r { v31.1d, v0.1d }, [x0], x5 // encoding: [0x1f,0xcc,0xe5,0x0d]
ld3r {v0.16b, v1.16b, v2.16b}, [x0], x9
ld3r {v15.8h, v16.8h, v17.8h}, [x15], x6
ld3r {v31.4s, v0.4s, v1.4s}, [sp], x7
ld3r {v0.2d, v1.2d, v2.2d}, [x0], x5
ld3r {v0.8b, v1.8b, v2.8b}, [x0], #3
ld3r {v15.4h, v16.4h, v17.4h}, [x15], #6
ld3r {v31.2s, v0.2s, v1.2s}, [sp], #12
ld3r {v31.1d, v0.1d, v1.1d}, [sp], #24
// CHECK: ld3r {v0.16b, v1.16b, v2.16b}, [x0], x9 // encoding: [0x00,0xe0,0xc9,0x4d]
// CHECK: ld3r {v15.8h, v16.8h, v17.8h}, [x15], x6 // encoding: [0xef,0xe5,0xc6,0x4d]
// CHECK: ld3r {v31.4s, v0.4s, v1.4s}, [sp], x7 // encoding: [0xff,0xeb,0xc7,0x4d]
// CHECK: ld3r {v0.2d, v1.2d, v2.2d}, [x0], x5 // encoding: [0x00,0xec,0xc5,0x4d]
// CHECK: ld3r {v0.8b, v1.8b, v2.8b}, [x0], #3 // encoding: [0x00,0xe0,0xdf,0x0d]
// CHECK: ld3r {v15.4h, v16.4h, v17.4h}, [x15], #6 // encoding: [0xef,0xe5,0xdf,0x0d]
// CHECK: ld3r {v31.2s, v0.2s, v1.2s}, [sp], #12 // encoding: [0xff,0xeb,0xdf,0x0d]
// CHECK: ld3r {v31.1d, v0.1d, v1.1d}, [sp], #24 // encoding: [0xff,0xef,0xdf,0x0d]
ld3r { v0.16b, v1.16b, v2.16b }, [x0], x9
ld3r { v15.8h, v16.8h, v17.8h }, [x15], x6
ld3r { v31.4s, v0.4s, v1.4s }, [sp], x7
ld3r { v0.2d, v1.2d, v2.2d }, [x0], x5
ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3
ld3r { v15.4h, v16.4h, v17.4h }, [x15], #6
ld3r { v31.2s, v0.2s, v1.2s }, [sp], #12
ld3r { v31.1d, v0.1d, v1.1d }, [sp], #24
// CHECK: ld3r { v0.16b, v1.16b, v2.16b }, [x0], x9 // encoding: [0x00,0xe0,0xc9,0x4d]
// CHECK: ld3r { v15.8h, v16.8h, v17.8h }, [x15], x6 // encoding: [0xef,0xe5,0xc6,0x4d]
// CHECK: ld3r { v31.4s, v0.4s, v1.4s }, [sp], x7 // encoding: [0xff,0xeb,0xc7,0x4d]
// CHECK: ld3r { v0.2d, v1.2d, v2.2d }, [x0], x5 // encoding: [0x00,0xec,0xc5,0x4d]
// CHECK: ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3 // encoding: [0x00,0xe0,0xdf,0x0d]
// CHECK: ld3r { v15.4h, v16.4h, v17.4h }, [x15], #6 // encoding: [0xef,0xe5,0xdf,0x0d]
// CHECK: ld3r { v31.2s, v0.2s, v1.2s }, [sp], #12 // encoding: [0xff,0xeb,0xdf,0x0d]
// CHECK: ld3r { v31.1d, v0.1d, v1.1d }, [sp], #24 // encoding: [0xff,0xef,0xdf,0x0d]
ld4r {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], #4
ld4r {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], #8
ld4r {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #16
ld4r {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #32
ld4r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x5
ld4r {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x9
ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], x30
ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp], x7
// CHECK: ld4r {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], #4 // encoding: [0x00,0xe0,0xff,0x4d]
// CHECK: ld4r {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], #8 // encoding: [0xef,0xe5,0xff,0x4d]
// CHECK: ld4r {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #16 // encoding: [0xff,0xeb,0xff,0x4d]
// CHECK: ld4r {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #32 // encoding: [0x00,0xec,0xff,0x4d]
// CHECK: ld4r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x5 // encoding: [0x00,0xe0,0xe5,0x0d]
// CHECK: ld4r {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x9 // encoding: [0xef,0xe5,0xe9,0x0d]
// CHECK: ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], x30 // encoding: [0xff,0xeb,0xfe,0x0d]
// CHECK: ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp], x7 // encoding: [0xff,0xef,0xe7,0x0d]
ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], #4
ld4r { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], #8
ld4r { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #16
ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #32
ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x5
ld4r { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x9
ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], x30
ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp], x7
// CHECK: ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], #4 // encoding: [0x00,0xe0,0xff,0x4d]
// CHECK: ld4r { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], #8 // encoding: [0xef,0xe5,0xff,0x4d]
// CHECK: ld4r { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #16 // encoding: [0xff,0xeb,0xff,0x4d]
// CHECK: ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #32 // encoding: [0x00,0xec,0xff,0x4d]
// CHECK: ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x5 // encoding: [0x00,0xe0,0xe5,0x0d]
// CHECK: ld4r { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x9 // encoding: [0xef,0xe5,0xe9,0x0d]
// CHECK: ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], x30 // encoding: [0xff,0xeb,0xfe,0x0d]
// CHECK: ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp], x7 // encoding: [0xff,0xef,0xe7,0x0d]
//------------------------------------------------------------------------------
// Post-index load single 1-element structure to one lane of 1 register.
//------------------------------------------------------------------------------
ld1 {v0.b}[9], [x0], #1
ld1 {v15.h}[7], [x15], x9
ld1 {v31.s}[3], [sp], x6
ld1 {v0.d}[1], [x0], #8
// CHECK: ld1 {v0.b}[9], [x0], #1 // encoding: [0x00,0x04,0xdf,0x4d]
// CHECK: ld1 {v15.h}[7], [x15], x9 // encoding: [0xef,0x59,0xc9,0x4d]
// CHECK: ld1 {v31.s}[3], [sp], x6 // encoding: [0xff,0x93,0xc6,0x4d]
// CHECK: ld1 {v0.d}[1], [x0], #8 // encoding: [0x00,0x84,0xdf,0x4d]
ld1 { v0.b }[9], [x0], #1
ld1 { v15.h }[7], [x15], x9
ld1 { v31.s }[3], [sp], x6
ld1 { v0.d }[1], [x0], #8
// CHECK: ld1 { v0.b }[9], [x0], #1 // encoding: [0x00,0x04,0xdf,0x4d]
// CHECK: ld1 { v15.h }[7], [x15], x9 // encoding: [0xef,0x59,0xc9,0x4d]
// CHECK: ld1 { v31.s }[3], [sp], x6 // encoding: [0xff,0x93,0xc6,0x4d]
// CHECK: ld1 { v0.d }[1], [x0], #8 // encoding: [0x00,0x84,0xdf,0x4d]
//------------------------------------------------------------------------------
// Post-index load single N-element structure to one lane of N consecutive
// registers (N = 2,3,4)
//------------------------------------------------------------------------------
ld2 {v0.b, v1.b}[9], [x0], x3
ld2 {v15.h, v16.h}[7], [x15], #4
ld2 {v31.s, v0.s}[3], [sp], #8
ld2 {v0.d, v1.d}[1], [x0], x0
// CHECK: ld2 {v0.b, v1.b}[9], [x0], x3 // encoding: [0x00,0x04,0xe3,0x4d]
// CHECK: ld2 {v15.h, v16.h}[7], [x15], #4 // encoding: [0xef,0x59,0xff,0x4d]
// CHECK: ld2 {v31.s, v0.s}[3], [sp], #8 // encoding: [0xff,0x93,0xff,0x4d]
// CHECK: ld2 {v0.d, v1.d}[1], [x0], x0 // encoding: [0x00,0x84,0xe0,0x4d]
ld2 { v0.b, v1.b }[9], [x0], x3
ld2 { v15.h, v16.h }[7], [x15], #4
ld2 { v31.s, v0.s }[3], [sp], #8
ld2 { v0.d, v1.d }[1], [x0], x0
// CHECK: ld2 { v0.b, v1.b }[9], [x0], x3 // encoding: [0x00,0x04,0xe3,0x4d]
// CHECK: ld2 { v15.h, v16.h }[7], [x15], #4 // encoding: [0xef,0x59,0xff,0x4d]
// CHECK: ld2 { v31.s, v0.s }[3], [sp], #8 // encoding: [0xff,0x93,0xff,0x4d]
// CHECK: ld2 { v0.d, v1.d }[1], [x0], x0 // encoding: [0x00,0x84,0xe0,0x4d]
ld3 {v0.b, v1.b, v2.b}[9], [x0], #3
ld3 {v15.h, v16.h, v17.h}[7], [x15], #6
ld3 {v31.s, v0.s, v1.s}[3], [sp], x3
ld3 {v0.d, v1.d, v2.d}[1], [x0], x6
// CHECK: ld3 {v0.b, v1.b, v2.b}[9], [x0], #3 // encoding: [0x00,0x24,0xdf,0x4d]
// CHECK: ld3 {v15.h, v16.h, v17.h}[7], [x15], #6 // encoding: [0xef,0x79,0xdf,0x4d]
// CHECK: ld3 {v31.s, v0.s, v1.s}[3], [sp], x3 // encoding: [0xff,0xb3,0xc3,0x4d]
// CHECK: ld3 {v0.d, v1.d, v2.d}[1], [x0], x6 // encoding: [0x00,0xa4,0xc6,0x4d]
ld3 { v0.b, v1.b, v2.b }[9], [x0], #3
ld3 { v15.h, v16.h, v17.h }[7], [x15], #6
ld3 { v31.s, v0.s, v1.s }[3], [sp], x3
ld3 { v0.d, v1.d, v2.d }[1], [x0], x6
// CHECK: ld3 { v0.b, v1.b, v2.b }[9], [x0], #3 // encoding: [0x00,0x24,0xdf,0x4d]
// CHECK: ld3 { v15.h, v16.h, v17.h }[7], [x15], #6 // encoding: [0xef,0x79,0xdf,0x4d]
// CHECK: ld3 { v31.s, v0.s, v1.s }[3], [sp], x3 // encoding: [0xff,0xb3,0xc3,0x4d]
// CHECK: ld3 { v0.d, v1.d, v2.d }[1], [x0], x6 // encoding: [0x00,0xa4,0xc6,0x4d]
ld4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5
ld4 {v15.h, v16.h, v17.h, v18.h}[7], [x15], x7
ld4 {v31.s, v0.s, v1.s, v2.s}[3], [sp], #16
ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32
// CHECK: ld4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5 // encoding: [0x00,0x24,0xe5,0x4d]
// CHECK: ld4 {v15.h, v16.h, v17.h, v18.h}[7], [x15], x7 // encoding: [0xef,0x79,0xe7,0x4d]
// CHECK: ld4 {v31.s, v0.s, v1.s, v2.s}[3], [sp], #16 // encoding: [0xff,0xb3,0xff,0x4d]
// CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32 // encoding: [0x00,0xa4,0xff,0x4d]
ld4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5
ld4 { v15.h, v16.h, v17.h, v18.h }[7], [x15], x7
ld4 { v31.s, v0.s, v1.s, v2.s }[3], [sp], #16
ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32
// CHECK: ld4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5 // encoding: [0x00,0x24,0xe5,0x4d]
// CHECK: ld4 { v15.h, v16.h, v17.h, v18.h }[7], [x15], x7 // encoding: [0xef,0x79,0xe7,0x4d]
// CHECK: ld4 { v31.s, v0.s, v1.s, v2.s }[3], [sp], #16 // encoding: [0xff,0xb3,0xff,0x4d]
// CHECK: ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32 // encoding: [0x00,0xa4,0xff,0x4d]
//------------------------------------------------------------------------------
// Post-index store single 1-element structure from one lane of 1 register.
//------------------------------------------------------------------------------
st1 {v0.b}[9], [x0], #1
st1 {v15.h}[7], [x15], x9
st1 {v31.s}[3], [sp], x6
st1 {v0.d}[1], [x0], #8
// CHECK: st1 {v0.b}[9], [x0], #1 // encoding: [0x00,0x04,0x9f,0x4d]
// CHECK: st1 {v15.h}[7], [x15], x9 // encoding: [0xef,0x59,0x89,0x4d]
// CHECK: st1 {v31.s}[3], [sp], x6 // encoding: [0xff,0x93,0x86,0x4d]
// CHECK: st1 {v0.d}[1], [x0], #8 // encoding: [0x00,0x84,0x9f,0x4d]
st1 { v0.b }[9], [x0], #1
st1 { v15.h }[7], [x15], x9
st1 { v31.s }[3], [sp], x6
st1 { v0.d }[1], [x0], #8
// CHECK: st1 { v0.b }[9], [x0], #1 // encoding: [0x00,0x04,0x9f,0x4d]
// CHECK: st1 { v15.h }[7], [x15], x9 // encoding: [0xef,0x59,0x89,0x4d]
// CHECK: st1 { v31.s }[3], [sp], x6 // encoding: [0xff,0x93,0x86,0x4d]
// CHECK: st1 { v0.d }[1], [x0], #8 // encoding: [0x00,0x84,0x9f,0x4d]
//------------------------------------------------------------------------------
// Post-index store single N-element structure from one lane of N consecutive
// registers (N = 2,3,4)
//------------------------------------------------------------------------------
st2 {v0.b, v1.b}[9], [x0], x3
st2 {v15.h, v16.h}[7], [x15], #4
st2 {v31.s, v0.s}[3], [sp], #8
st2 {v0.d, v1.d}[1], [x0], x0
// CHECK: st2 {v0.b, v1.b}[9], [x0], x3 // encoding: [0x00,0x04,0xa3,0x4d]
// CHECK: st2 {v15.h, v16.h}[7], [x15], #4 // encoding: [0xef,0x59,0xbf,0x4d]
// CHECK: st2 {v31.s, v0.s}[3], [sp], #8 // encoding: [0xff,0x93,0xbf,0x4d]
// CHECK: st2 {v0.d, v1.d}[1], [x0], x0 // encoding: [0x00,0x84,0xa0,0x4d]
st2 { v0.b, v1.b }[9], [x0], x3
st2 { v15.h, v16.h }[7], [x15], #4
st2 { v31.s, v0.s }[3], [sp], #8
st2 { v0.d, v1.d }[1], [x0], x0
// CHECK: st2 { v0.b, v1.b }[9], [x0], x3 // encoding: [0x00,0x04,0xa3,0x4d]
// CHECK: st2 { v15.h, v16.h }[7], [x15], #4 // encoding: [0xef,0x59,0xbf,0x4d]
// CHECK: st2 { v31.s, v0.s }[3], [sp], #8 // encoding: [0xff,0x93,0xbf,0x4d]
// CHECK: st2 { v0.d, v1.d }[1], [x0], x0 // encoding: [0x00,0x84,0xa0,0x4d]
st3 {v0.b, v1.b, v2.b}[9], [x0], #3
st3 {v15.h, v16.h, v17.h}[7], [x15], #6
st3 {v31.s, v0.s, v1.s}[3], [sp], x3
st3 {v0.d, v1.d, v2.d}[1], [x0], x6
// CHECK: st3 {v0.b, v1.b, v2.b}[9], [x0], #3 // encoding: [0x00,0x24,0x9f,0x4d]
// CHECK: st3 {v15.h, v16.h, v17.h}[7], [x15], #6 // encoding: [0xef,0x79,0x9f,0x4d]
// CHECK: st3 {v31.s, v0.s, v1.s}[3], [sp], x3 // encoding: [0xff,0xb3,0x83,0x4d]
// CHECK: st3 {v0.d, v1.d, v2.d}[1], [x0], x6 // encoding: [0x00,0xa4,0x86,0x4d]
st3 { v0.b, v1.b, v2.b }[9], [x0], #3
st3 { v15.h, v16.h, v17.h }[7], [x15], #6
st3 { v31.s, v0.s, v1.s }[3], [sp], x3
st3 { v0.d, v1.d, v2.d }[1], [x0], x6
// CHECK: st3 { v0.b, v1.b, v2.b }[9], [x0], #3 // encoding: [0x00,0x24,0x9f,0x4d]
// CHECK: st3 { v15.h, v16.h, v17.h }[7], [x15], #6 // encoding: [0xef,0x79,0x9f,0x4d]
// CHECK: st3 { v31.s, v0.s, v1.s }[3], [sp], x3 // encoding: [0xff,0xb3,0x83,0x4d]
// CHECK: st3 { v0.d, v1.d, v2.d }[1], [x0], x6 // encoding: [0x00,0xa4,0x86,0x4d]
st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5
st4 {v15.h, v16.h, v17.h, v18.h}[7], [x15], x7
st4 {v31.s, v0.s, v1.s, v2.s}[3], [sp], #16
st4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32
// CHECK: st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5 // encoding: [0x00,0x24,0xa5,0x4d]
// CHECK: st4 {v15.h, v16.h, v17.h, v18.h}[7], [x15], x7 // encoding: [0xef,0x79,0xa7,0x4d]
// CHECK: st4 {v31.s, v0.s, v1.s, v2.s}[3], [sp], #16 // encoding: [0xff,0xb3,0xbf,0x4d]
// CHECK: st4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32 // encoding: [0x00,0xa4,0xbf,0x4d]
st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5
st4 { v15.h, v16.h, v17.h, v18.h }[7], [x15], x7
st4 { v31.s, v0.s, v1.s, v2.s }[3], [sp], #16
st4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32
// CHECK: st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5 // encoding: [0x00,0x24,0xa5,0x4d]
// CHECK: st4 { v15.h, v16.h, v17.h, v18.h }[7], [x15], x7 // encoding: [0xef,0x79,0xa7,0x4d]
// CHECK: st4 { v31.s, v0.s, v1.s, v2.s }[3], [sp], #16 // encoding: [0xff,0xb3,0xbf,0x4d]
// CHECK: st4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32 // encoding: [0x00,0xa4,0xbf,0x4d]

424
test/MC/AArch64/neon-simd-post-ldst-multi-elem.s
View File

@ -5,385 +5,385 @@
//------------------------------------------------------------------------------
// Load multiple 1-element structures from one register (post-index)
//------------------------------------------------------------------------------
ld1 {v0.16b}, [x0], x1
ld1 {v15.8h}, [x15], x2
ld1 {v31.4s}, [sp], #16
ld1 {v0.2d}, [x0], #16
ld1 {v0.8b}, [x0], x2
ld1 {v15.4h}, [x15], x3
ld1 {v31.2s}, [sp], #8
ld1 {v0.1d}, [x0], #8
// CHECK: ld1 {v0.16b}, [x0], x1
ld1 { v0.16b }, [x0], x1
ld1 { v15.8h }, [x15], x2
ld1 { v31.4s }, [sp], #16
ld1 { v0.2d }, [x0], #16
ld1 { v0.8b }, [x0], x2
ld1 { v15.4h }, [x15], x3
ld1 { v31.2s }, [sp], #8
ld1 { v0.1d }, [x0], #8
// CHECK: ld1 { v0.16b }, [x0], x1
// CHECK: // encoding: [0x00,0x70,0xc1,0x4c]
// CHECK: ld1 {v15.8h}, [x15], x2
// CHECK: ld1 { v15.8h }, [x15], x2
// CHECK: // encoding: [0xef,0x75,0xc2,0x4c]
// CHECK: ld1 {v31.4s}, [sp], #16
// CHECK: ld1 { v31.4s }, [sp], #16
// CHECK: // encoding: [0xff,0x7b,0xdf,0x4c]
// CHECK: ld1 {v0.2d}, [x0], #16
// CHECK: ld1 { v0.2d }, [x0], #16
// CHECK: // encoding: [0x00,0x7c,0xdf,0x4c]
// CHECK: ld1 {v0.8b}, [x0], x2
// CHECK: ld1 { v0.8b }, [x0], x2
// CHECK: // encoding: [0x00,0x70,0xc2,0x0c]
// CHECK: ld1 {v15.4h}, [x15], x3
// CHECK: ld1 { v15.4h }, [x15], x3
// CHECK: // encoding: [0xef,0x75,0xc3,0x0c]
// CHECK: ld1 {v31.2s}, [sp], #8
// CHECK: ld1 { v31.2s }, [sp], #8
// CHECK: // encoding: [0xff,0x7b,0xdf,0x0c]
// CHECK: ld1 {v0.1d}, [x0], #8
// CHECK: ld1 { v0.1d }, [x0], #8
// CHECK: // encoding: [0x00,0x7c,0xdf,0x0c]
//------------------------------------------------------------------------------
// Load multiple 1-element structures from two consecutive registers
// (post-index)
//------------------------------------------------------------------------------
ld1 {v0.16b, v1.16b}, [x0], x1
ld1 {v15.8h, v16.8h}, [x15], x2
ld1 {v31.4s, v0.4s}, [sp], #32
ld1 {v0.2d, v1.2d}, [x0], #32
ld1 {v0.8b, v1.8b}, [x0], x2
ld1 {v15.4h, v16.4h}, [x15], x3
ld1 {v31.2s, v0.2s}, [sp], #16
ld1 {v0.1d, v1.1d}, [x0], #16
// CHECK: ld1 {v0.16b, v1.16b}, [x0], x1
ld1 { v0.16b, v1.16b }, [x0], x1
ld1 { v15.8h, v16.8h }, [x15], x2
ld1 { v31.4s, v0.4s }, [sp], #32
ld1 { v0.2d, v1.2d }, [x0], #32
ld1 { v0.8b, v1.8b }, [x0], x2
ld1 { v15.4h, v16.4h }, [x15], x3
ld1 { v31.2s, v0.2s }, [sp], #16
ld1 { v0.1d, v1.1d }, [x0], #16
// CHECK: ld1 { v0.16b, v1.16b }, [x0], x1
// CHECK: // encoding: [0x00,0xa0,0xc1,0x4c]
// CHECK: ld1 {v15.8h, v16.8h}, [x15], x2
// CHECK: ld1 { v15.8h, v16.8h }, [x15], x2
// CHECK: // encoding: [0xef,0xa5,0xc2,0x4c]
// CHECK: ld1 {v31.4s, v0.4s}, [sp], #32
// CHECK: ld1 { v31.4s, v0.4s }, [sp], #32
// CHECK: // encoding: [0xff,0xab,0xdf,0x4c]
// CHECK: ld1 {v0.2d, v1.2d}, [x0], #32
// CHECK: ld1 { v0.2d, v1.2d }, [x0], #32
// CHECK: // encoding: [0x00,0xac,0xdf,0x4c]
// CHECK: ld1 {v0.8b, v1.8b}, [x0], x2
// CHECK: ld1 { v0.8b, v1.8b }, [x0], x2
// CHECK: // encoding: [0x00,0xa0,0xc2,0x0c]
// CHECK: ld1 {v15.4h, v16.4h}, [x15], x3
// CHECK: ld1 { v15.4h, v16.4h }, [x15], x3
// CHECK: // encoding: [0xef,0xa5,0xc3,0x0c]
// CHECK: ld1 {v31.2s, v0.2s}, [sp], #16
// CHECK: ld1 { v31.2s, v0.2s }, [sp], #16
// CHECK: // encoding: [0xff,0xab,0xdf,0x0c]
// CHECK: ld1 {v0.1d, v1.1d}, [x0], #16
// CHECK: ld1 { v0.1d, v1.1d }, [x0], #16
// CHECK: // encoding: [0x00,0xac,0xdf,0x0c]
//------------------------------------------------------------------------------
// Load multiple 1-element structures from three consecutive registers
// (post-index)
//------------------------------------------------------------------------------
ld1 {v0.16b, v1.16b, v2.16b}, [x0], x1
ld1 {v15.8h, v16.8h, v17.8h}, [x15], x2
ld1 {v31.4s, v0.4s, v1.4s}, [sp], #48
ld1 {v0.2d, v1.2d, v2.2d}, [x0], #48
ld1 {v0.8b, v1.8b, v2.8b}, [x0], x2
ld1 {v15.4h, v16.4h, v17.4h}, [x15], x3
ld1 {v31.2s, v0.2s, v1.2s}, [sp], #24
ld1 {v0.1d, v1.1d, v2.1d}, [x0], #24
// CHECK: ld1 {v0.16b, v1.16b, v2.16b}, [x0], x1
ld1 { v0.16b, v1.16b, v2.16b }, [x0], x1
ld1 { v15.8h, v16.8h, v17.8h }, [x15], x2
ld1 { v31.4s, v0.4s, v1.4s }, [sp], #48
ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48
ld1 { v0.8b, v1.8b, v2.8b }, [x0], x2
ld1 { v15.4h, v16.4h, v17.4h }, [x15], x3
ld1 { v31.2s, v0.2s, v1.2s }, [sp], #24
ld1 { v0.1d, v1.1d, v2.1d }, [x0], #24
// CHECK: ld1 { v0.16b, v1.16b, v2.16b }, [x0], x1
// CHECK: // encoding: [0x00,0x60,0xc1,0x4c]
// CHECK: ld1 {v15.8h, v16.8h, v17.8h}, [x15], x2
// CHECK: ld1 { v15.8h, v16.8h, v17.8h }, [x15], x2
// CHECK: // encoding: [0xef,0x65,0xc2,0x4c]
// CHECK: ld1 {v31.4s, v0.4s, v1.4s}, [sp], #48
// CHECK: ld1 { v31.4s, v0.4s, v1.4s }, [sp], #48
// CHECK: // encoding: [0xff,0x6b,0xdf,0x4c]
// CHECK: ld1 {v0.2d, v1.2d, v2.2d}, [x0], #48
// CHECK: ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48
// CHECK: // encoding: [0x00,0x6c,0xdf,0x4c]
// CHECK: ld1 {v0.8b, v1.8b, v2.8b}, [x0], x2
// CHECK: ld1 { v0.8b, v1.8b, v2.8b }, [x0], x2
// CHECK: // encoding: [0x00,0x60,0xc2,0x0c]
// CHECK: ld1 {v15.4h, v16.4h, v17.4h}, [x15], x3
// CHECK: ld1 { v15.4h, v16.4h, v17.4h }, [x15], x3
// CHECK: // encoding: [0xef,0x65,0xc3,0x0c]
// CHECK: ld1 {v31.2s, v0.2s, v1.2s}, [sp], #24
// CHECK: ld1 { v31.2s, v0.2s, v1.2s }, [sp], #24
// CHECK: // encoding: [0xff,0x6b,0xdf,0x0c]
// CHECK: ld1 {v0.1d, v1.1d, v2.1d}, [x0], #24
// CHECK: ld1 { v0.1d, v1.1d, v2.1d }, [x0], #24
// CHECK: // encoding: [0x00,0x6c,0xdf,0x0c]
//------------------------------------------------------------------------------
// Load multiple 1-element structures from four consecutive registers
// (post-index)
//------------------------------------------------------------------------------
ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1
ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2
ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64
ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64
ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3
ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4
ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32
ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0], #32
// CHECK: ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1
ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1
ld1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2
ld1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64
ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64
ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
ld1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4
ld1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32
ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0], #32
// CHECK: ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1
// CHECK: // encoding: [0x00,0x20,0xc1,0x4c]
// CHECK: ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2
// CHECK: ld1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2
// CHECK: // encoding: [0xef,0x25,0xc2,0x4c]
// CHECK: ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64
// CHECK: ld1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64
// CHECK: // encoding: [0xff,0x2b,0xdf,0x4c]
// CHECK: ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64
// CHECK: ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64
// CHECK: // encoding: [0x00,0x2c,0xdf,0x4c]
// CHECK: ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3
// CHECK: ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
// CHECK: // encoding: [0x00,0x20,0xc3,0x0c]
// CHECK: ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4
// CHECK: ld1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4
// CHECK: // encoding: [0xef,0x25,0xc4,0x0c]
// CHECK: ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32
// CHECK: ld1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32
// CHECK: // encoding: [0xff,0x2b,0xdf,0x0c]
// CHECK: ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0], #32
// CHECK: ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0], #32
// CHECK: // encoding: [0x00,0x2c,0xdf,0x0c]
//------------------------------------------------------------------------------
// Load multiple 2-element structures from two consecutive registers
// (post-index)
//------------------------------------------------------------------------------
ld2 {v0.16b, v1.16b}, [x0], x1
ld2 {v15.8h, v16.8h}, [x15], x2
ld2 {v31.4s, v0.4s}, [sp], #32
ld2 {v0.2d, v1.2d}, [x0], #32
ld2 {v0.8b, v1.8b}, [x0], x2
ld2 {v15.4h, v16.4h}, [x15], x3
ld2 {v31.2s, v0.2s}, [sp], #16
// CHECK: ld2 {v0.16b, v1.16b}, [x0], x1
ld2 { v0.16b, v1.16b }, [x0], x1
ld2 { v15.8h, v16.8h }, [x15], x2
ld2 { v31.4s, v0.4s }, [sp], #32
ld2 { v0.2d, v1.2d }, [x0], #32
ld2 { v0.8b, v1.8b }, [x0], x2
ld2 { v15.4h, v16.4h }, [x15], x3
ld2 { v31.2s, v0.2s }, [sp], #16
// CHECK: ld2 { v0.16b, v1.16b }, [x0], x1
// CHECK: // encoding: [0x00,0x80,0xc1,0x4c]
// CHECK: ld2 {v15.8h, v16.8h}, [x15], x2
// CHECK: ld2 { v15.8h, v16.8h }, [x15], x2
// CHECK: // encoding: [0xef,0x85,0xc2,0x4c]
// CHECK: ld2 {v31.4s, v0.4s}, [sp], #32
// CHECK: ld2 { v31.4s, v0.4s }, [sp], #32
// CHECK: // encoding: [0xff,0x8b,0xdf,0x4c]
// CHECK: ld2 {v0.2d, v1.2d}, [x0], #32
// CHECK: ld2 { v0.2d, v1.2d }, [x0], #32
// CHECK: // encoding: [0x00,0x8c,0xdf,0x4c]
// CHECK: ld2 {v0.8b, v1.8b}, [x0], x2
// CHECK: ld2 { v0.8b, v1.8b }, [x0], x2
// CHECK: // encoding: [0x00,0x80,0xc2,0x0c]
// CHECK: ld2 {v15.4h, v16.4h}, [x15], x3
// CHECK: ld2 { v15.4h, v16.4h }, [x15], x3
// CHECK: // encoding: [0xef,0x85,0xc3,0x0c]
// CHECK: ld2 {v31.2s, v0.2s}, [sp], #16
// CHECK: ld2 { v31.2s, v0.2s }, [sp], #16
// CHECK: // encoding: [0xff,0x8b,0xdf,0x0c]
//------------------------------------------------------------------------------
// Load multiple 3-element structures from three consecutive registers
// (post-index)
//------------------------------------------------------------------------------
ld3 {v0.16b, v1.16b, v2.16b}, [x0], x1
ld3 {v15.8h, v16.8h, v17.8h}, [x15], x2
ld3 {v31.4s, v0.4s, v1.4s}, [sp], #48
ld3 {v0.2d, v1.2d, v2.2d}, [x0], #48
ld3 {v0.8b, v1.8b, v2.8b}, [x0], x2
ld3 {v15.4h, v16.4h, v17.4h}, [x15], x3
ld3 {v31.2s, v0.2s, v1.2s}, [sp], #24
// CHECK: ld3 {v0.16b, v1.16b, v2.16b}, [x0], x1
ld3 { v0.16b, v1.16b, v2.16b }, [x0], x1
ld3 { v15.8h, v16.8h, v17.8h }, [x15], x2
ld3 { v31.4s, v0.4s, v1.4s }, [sp], #48
ld3 { v0.2d, v1.2d, v2.2d }, [x0], #48
ld3 { v0.8b, v1.8b, v2.8b }, [x0], x2
ld3 { v15.4h, v16.4h, v17.4h }, [x15], x3
ld3 { v31.2s, v0.2s, v1.2s }, [sp], #24
// CHECK: ld3 { v0.16b, v1.16b, v2.16b }, [x0], x1
// CHECK: // encoding: [0x00,0x40,0xc1,0x4c]
// CHECK: ld3 {v15.8h, v16.8h, v17.8h}, [x15], x2
// CHECK: ld3 { v15.8h, v16.8h, v17.8h }, [x15], x2
// CHECK: // encoding: [0xef,0x45,0xc2,0x4c]
// CHECK: ld3 {v31.4s, v0.4s, v1.4s}, [sp], #48
// CHECK: ld3 { v31.4s, v0.4s, v1.4s }, [sp], #48
// CHECK: // encoding: [0xff,0x4b,0xdf,0x4c]
// CHECK: ld3 {v0.2d, v1.2d, v2.2d}, [x0], #48
// CHECK: ld3 { v0.2d, v1.2d, v2.2d }, [x0], #48
// CHECK: // encoding: [0x00,0x4c,0xdf,0x4c]
// CHECK: ld3 {v0.8b, v1.8b, v2.8b}, [x0], x2
// CHECK: ld3 { v0.8b, v1.8b, v2.8b }, [x0], x2
// CHECK: // encoding: [0x00,0x40,0xc2,0x0c]
// CHECK: ld3 {v15.4h, v16.4h, v17.4h}, [x15], x3
// CHECK: ld3 { v15.4h, v16.4h, v17.4h }, [x15], x3
// CHECK: // encoding: [0xef,0x45,0xc3,0x0c]
// CHECK: ld3 {v31.2s, v0.2s, v1.2s}, [sp], #24
// CHECK: ld3 { v31.2s, v0.2s, v1.2s }, [sp], #24
// CHECK: // encoding: [0xff,0x4b,0xdf,0x0c]
//------------------------------------------------------------------------------
// Load multiple 4-element structures from four consecutive registers
// (post-index)
//------------------------------------------------------------------------------
ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1
ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2
ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64
ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64
ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3
ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4
ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32
// CHECK: ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1
ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1
ld4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2
ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64
ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64
ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
ld4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4
ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32
// CHECK: ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1
// CHECK: // encoding: [0x00,0x00,0xc1,0x4c]
// CHECK: ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2
// CHECK: ld4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2
// CHECK: // encoding: [0xef,0x05,0xc2,0x4c]
// CHECK: ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64
// CHECK: ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64
// CHECK: // encoding: [0xff,0x0b,0xdf,0x4c]
// CHECK: ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64
// CHECK: ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64
// CHECK: // encoding: [0x00,0x0c,0xdf,0x4c]
// CHECK: ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3
// CHECK: ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
// CHECK: // encoding: [0x00,0x00,0xc3,0x0c]
// CHECK: ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4
// CHECK: ld4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4
// CHECK: // encoding: [0xef,0x05,0xc4,0x0c]
// CHECK: ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32
// CHECK: ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32
// CHECK: // encoding: [0xff,0x0b,0xdf,0x0c]
//------------------------------------------------------------------------------
// Store multiple 1-element structures from one register (post-index)
//------------------------------------------------------------------------------
st1 {v0.16b}, [x0], x1
st1 {v15.8h}, [x15], x2
st1 {v31.4s}, [sp], #16
st1 {v0.2d}, [x0], #16
st1 {v0.8b}, [x0], x2
st1 {v15.4h}, [x15], x3
st1 {v31.2s}, [sp], #8
st1 {v0.1d}, [x0], #8
// CHECK: st1 {v0.16b}, [x0], x1
st1 { v0.16b }, [x0], x1
st1 { v15.8h }, [x15], x2
st1 { v31.4s }, [sp], #16
st1 { v0.2d }, [x0], #16
st1 { v0.8b }, [x0], x2
st1 { v15.4h }, [x15], x3
st1 { v31.2s }, [sp], #8
st1 { v0.1d }, [x0], #8
// CHECK: st1 { v0.16b }, [x0], x1
// CHECK: // encoding: [0x00,0x70,0x81,0x4c]
// CHECK: st1 {v15.8h}, [x15], x2
// CHECK: st1 { v15.8h }, [x15], x2
// CHECK: // encoding: [0xef,0x75,0x82,0x4c]
// CHECK: st1 {v31.4s}, [sp], #16
// CHECK: st1 { v31.4s }, [sp], #16
// CHECK: // encoding: [0xff,0x7b,0x9f,0x4c]
// CHECK: st1 {v0.2d}, [x0], #16
// CHECK: st1 { v0.2d }, [x0], #16
// CHECK: // encoding: [0x00,0x7c,0x9f,0x4c]
// CHECK: st1 {v0.8b}, [x0], x2
// CHECK: st1 { v0.8b }, [x0], x2
// CHECK: // encoding: [0x00,0x70,0x82,0x0c]
// CHECK: st1 {v15.4h}, [x15], x3
// CHECK: st1 { v15.4h }, [x15], x3
// CHECK: // encoding: [0xef,0x75,0x83,0x0c]
// CHECK: st1 {v31.2s}, [sp], #8
// CHECK: st1 { v31.2s }, [sp], #8
// CHECK: // encoding: [0xff,0x7b,0x9f,0x0c]
// CHECK: st1 {v0.1d}, [x0], #8
// CHECK: st1 { v0.1d }, [x0], #8
// CHECK: // encoding: [0x00,0x7c,0x9f,0x0c]
//------------------------------------------------------------------------------
// Store multiple 1-element structures from two consecutive registers
// (post-index)
//------------------------------------------------------------------------------
st1 {v0.16b, v1.16b}, [x0], x1
st1 {v15.8h, v16.8h}, [x15], x2
st1 {v31.4s, v0.4s}, [sp], #32
st1 {v0.2d, v1.2d}, [x0], #32
st1 {v0.8b, v1.8b}, [x0], x2
st1 {v15.4h, v16.4h}, [x15], x3
st1 {v31.2s, v0.2s}, [sp], #16
st1 {v0.1d, v1.1d}, [x0], #16
// CHECK: st1 {v0.16b, v1.16b}, [x0], x1
st1 { v0.16b, v1.16b }, [x0], x1
st1 { v15.8h, v16.8h }, [x15], x2
st1 { v31.4s, v0.4s }, [sp], #32
st1 { v0.2d, v1.2d }, [x0], #32
st1 { v0.8b, v1.8b }, [x0], x2
st1 { v15.4h, v16.4h }, [x15], x3
st1 { v31.2s, v0.2s }, [sp], #16
st1 { v0.1d, v1.1d }, [x0], #16
// CHECK: st1 { v0.16b, v1.16b }, [x0], x1
// CHECK: // encoding: [0x00,0xa0,0x81,0x4c]
// CHECK: st1 {v15.8h, v16.8h}, [x15], x2
// CHECK: st1 { v15.8h, v16.8h }, [x15], x2
// CHECK: // encoding: [0xef,0xa5,0x82,0x4c]
// CHECK: st1 {v31.4s, v0.4s}, [sp], #32
// CHECK: st1 { v31.4s, v0.4s }, [sp], #32
// CHECK: // encoding: [0xff,0xab,0x9f,0x4c]
// CHECK: st1 {v0.2d, v1.2d}, [x0], #32
// CHECK: st1 { v0.2d, v1.2d }, [x0], #32
// CHECK: // encoding: [0x00,0xac,0x9f,0x4c]
// CHECK: st1 {v0.8b, v1.8b}, [x0], x2
// CHECK: st1 { v0.8b, v1.8b }, [x0], x2
// CHECK: // encoding: [0x00,0xa0,0x82,0x0c]
// CHECK: st1 {v15.4h, v16.4h}, [x15], x3
// CHECK: st1 { v15.4h, v16.4h }, [x15], x3
// CHECK: // encoding: [0xef,0xa5,0x83,0x0c]
// CHECK: st1 {v31.2s, v0.2s}, [sp], #16
// CHECK: st1 { v31.2s, v0.2s }, [sp], #16
// CHECK: // encoding: [0xff,0xab,0x9f,0x0c]
// CHECK: st1 {v0.1d, v1.1d}, [x0], #16
// CHECK: st1 { v0.1d, v1.1d }, [x0], #16
// CHECK: // encoding: [0x00,0xac,0x9f,0x0c]
//------------------------------------------------------------------------------
// Store multiple 1-element structures from three consecutive registers
// (post-index)
//------------------------------------------------------------------------------
st1 {v0.16b, v1.16b, v2.16b}, [x0], x1
st1 {v15.8h, v16.8h, v17.8h}, [x15], x2
st1 {v31.4s, v0.4s, v1.4s}, [sp], #48
st1 {v0.2d, v1.2d, v2.2d}, [x0], #48
st1 {v0.8b, v1.8b, v2.8b}, [x0], x2
st1 {v15.4h, v16.4h, v17.4h}, [x15], x3
st1 {v31.2s, v0.2s, v1.2s}, [sp], #24
st1 {v0.1d, v1.1d, v2.1d}, [x0], #24
// CHECK: st1 {v0.16b, v1.16b, v2.16b}, [x0], x1
st1 { v0.16b, v1.16b, v2.16b }, [x0], x1
st1 { v15.8h, v16.8h, v17.8h }, [x15], x2
st1 { v31.4s, v0.4s, v1.4s }, [sp], #48
st1 { v0.2d, v1.2d, v2.2d }, [x0], #48
st1 { v0.8b, v1.8b, v2.8b }, [x0], x2
st1 { v15.4h, v16.4h, v17.4h }, [x15], x3
st1 { v31.2s, v0.2s, v1.2s }, [sp], #24
st1 { v0.1d, v1.1d, v2.1d }, [x0], #24
// CHECK: st1 { v0.16b, v1.16b, v2.16b }, [x0], x1
// CHECK: // encoding: [0x00,0x60,0x81,0x4c]
// CHECK: st1 {v15.8h, v16.8h, v17.8h}, [x15], x2
// CHECK: st1 { v15.8h, v16.8h, v17.8h }, [x15], x2
// CHECK: // encoding: [0xef,0x65,0x82,0x4c]
// CHECK: st1 {v31.4s, v0.4s, v1.4s}, [sp], #48
// CHECK: st1 { v31.4s, v0.4s, v1.4s }, [sp], #48
// CHECK: // encoding: [0xff,0x6b,0x9f,0x4c]
// CHECK: st1 {v0.2d, v1.2d, v2.2d}, [x0], #48
// CHECK: st1 { v0.2d, v1.2d, v2.2d }, [x0], #48
// CHECK: // encoding: [0x00,0x6c,0x9f,0x4c]
// CHECK: st1 {v0.8b, v1.8b, v2.8b}, [x0], x2
// CHECK: st1 { v0.8b, v1.8b, v2.8b }, [x0], x2
// CHECK: // encoding: [0x00,0x60,0x82,0x0c]
// CHECK: st1 {v15.4h, v16.4h, v17.4h}, [x15], x3
// CHECK: st1 { v15.4h, v16.4h, v17.4h }, [x15], x3
// CHECK: // encoding: [0xef,0x65,0x83,0x0c]
// CHECK: st1 {v31.2s, v0.2s, v1.2s}, [sp], #24
// CHECK: st1 { v31.2s, v0.2s, v1.2s }, [sp], #24
// CHECK: // encoding: [0xff,0x6b,0x9f,0x0c]
// CHECK: st1 {v0.1d, v1.1d, v2.1d}, [x0], #24
// CHECK: st1 { v0.1d, v1.1d, v2.1d }, [x0], #24
// CHECK: // encoding: [0x00,0x6c,0x9f,0x0c]
//------------------------------------------------------------------------------
// Store multiple 1-element structures from four consecutive registers
// (post-index)
//------------------------------------------------------------------------------
st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1
st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2
st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64
st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64
st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3
st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4
st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32
st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0], #32
// CHECK: st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1
st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1
st1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2
st1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64
st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64
st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
st1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4
st1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32
st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0], #32
// CHECK: st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1
// CHECK: // encoding: [0x00,0x20,0x81,0x4c]
// CHECK: st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2
// CHECK: st1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2
// CHECK: // encoding: [0xef,0x25,0x82,0x4c]
// CHECK: st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64
// CHECK: st1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64
// CHECK: // encoding: [0xff,0x2b,0x9f,0x4c]
// CHECK: st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64
// CHECK: st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64
// CHECK: // encoding: [0x00,0x2c,0x9f,0x4c]
// CHECK: st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3
// CHECK: st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
// CHECK: // encoding: [0x00,0x20,0x83,0x0c]
// CHECK: st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4
// CHECK: st1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4
// CHECK: // encoding: [0xef,0x25,0x84,0x0c]
// CHECK: st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32
// CHECK: st1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32
// CHECK: // encoding: [0xff,0x2b,0x9f,0x0c]
// CHECK: st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0], #32
// CHECK: st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0], #32
// CHECK: // encoding: [0x00,0x2c,0x9f,0x0c]
//------------------------------------------------------------------------------
// Store multiple 2-element structures from two consecutive registers
// (post-index)
//------------------------------------------------------------------------------
st2 {v0.16b, v1.16b}, [x0], x1
st2 {v15.8h, v16.8h}, [x15], x2
st2 {v31.4s, v0.4s}, [sp], #32
st2 {v0.2d, v1.2d}, [x0], #32
st2 {v0.8b, v1.8b}, [x0], x2
st2 {v15.4h, v16.4h}, [x15], x3
st2 {v31.2s, v0.2s}, [sp], #16
// CHECK: st2 {v0.16b, v1.16b}, [x0], x1
st2 { v0.16b, v1.16b }, [x0], x1
st2 { v15.8h, v16.8h }, [x15], x2
st2 { v31.4s, v0.4s }, [sp], #32
st2 { v0.2d, v1.2d }, [x0], #32
st2 { v0.8b, v1.8b }, [x0], x2
st2 { v15.4h, v16.4h }, [x15], x3
st2 { v31.2s, v0.2s }, [sp], #16
// CHECK: st2 { v0.16b, v1.16b }, [x0], x1
// CHECK: // encoding: [0x00,0x80,0x81,0x4c]
// CHECK: st2 {v15.8h, v16.8h}, [x15], x2
// CHECK: st2 { v15.8h, v16.8h }, [x15], x2
// CHECK: // encoding: [0xef,0x85,0x82,0x4c]
// CHECK: st2 {v31.4s, v0.4s}, [sp], #32
// CHECK: st2 { v31.4s, v0.4s }, [sp], #32
// CHECK: // encoding: [0xff,0x8b,0x9f,0x4c]
// CHECK: st2 {v0.2d, v1.2d}, [x0], #32
// CHECK: st2 { v0.2d, v1.2d }, [x0], #32
// CHECK: // encoding: [0x00,0x8c,0x9f,0x4c]
// CHECK: st2 {v0.8b, v1.8b}, [x0], x2
// CHECK: st2 { v0.8b, v1.8b }, [x0], x2
// CHECK: // encoding: [0x00,0x80,0x82,0x0c]
// CHECK: st2 {v15.4h, v16.4h}, [x15], x3
// CHECK: st2 { v15.4h, v16.4h }, [x15], x3
// CHECK: // encoding: [0xef,0x85,0x83,0x0c]
// CHECK: st2 {v31.2s, v0.2s}, [sp], #16
// CHECK: st2 { v31.2s, v0.2s }, [sp], #16
// CHECK: // encoding: [0xff,0x8b,0x9f,0x0c]
//------------------------------------------------------------------------------
// Store multiple 3-element structures from three consecutive registers
// (post-index)
//------------------------------------------------------------------------------
st3 {v0.16b, v1.16b, v2.16b}, [x0], x1
st3 {v15.8h, v16.8h, v17.8h}, [x15], x2
st3 {v31.4s, v0.4s, v1.4s}, [sp], #48
st3 {v0.2d, v1.2d, v2.2d}, [x0], #48
st3 {v0.8b, v1.8b, v2.8b}, [x0], x2
st3 {v15.4h, v16.4h, v17.4h}, [x15], x3
st3 {v31.2s, v0.2s, v1.2s}, [sp], #24
// CHECK: st3 {v0.16b, v1.16b, v2.16b}, [x0], x1
st3 { v0.16b, v1.16b, v2.16b }, [x0], x1
st3 { v15.8h, v16.8h, v17.8h }, [x15], x2
st3 { v31.4s, v0.4s, v1.4s }, [sp], #48
st3 { v0.2d, v1.2d, v2.2d }, [x0], #48
st3 { v0.8b, v1.8b, v2.8b }, [x0], x2
st3 { v15.4h, v16.4h, v17.4h }, [x15], x3
st3 { v31.2s, v0.2s, v1.2s }, [sp], #24
// CHECK: st3 { v0.16b, v1.16b, v2.16b }, [x0], x1
// CHECK: // encoding: [0x00,0x40,0x81,0x4c]
// CHECK: st3 {v15.8h, v16.8h, v17.8h}, [x15], x2
// CHECK: st3 { v15.8h, v16.8h, v17.8h }, [x15], x2
// CHECK: // encoding: [0xef,0x45,0x82,0x4c]
// CHECK: st3 {v31.4s, v0.4s, v1.4s}, [sp], #48
// CHECK: st3 { v31.4s, v0.4s, v1.4s }, [sp], #48
// CHECK: // encoding: [0xff,0x4b,0x9f,0x4c]
// CHECK: st3 {v0.2d, v1.2d, v2.2d}, [x0], #48
// CHECK: st3 { v0.2d, v1.2d, v2.2d }, [x0], #48
// CHECK: // encoding: [0x00,0x4c,0x9f,0x4c]
// CHECK: st3 {v0.8b, v1.8b, v2.8b}, [x0], x2
// CHECK: st3 { v0.8b, v1.8b, v2.8b }, [x0], x2
// CHECK: // encoding: [0x00,0x40,0x82,0x0c]
// CHECK: st3 {v15.4h, v16.4h, v17.4h}, [x15], x3
// CHECK: st3 { v15.4h, v16.4h, v17.4h }, [x15], x3
// CHECK: // encoding: [0xef,0x45,0x83,0x0c]
// CHECK: st3 {v31.2s, v0.2s, v1.2s}, [sp], #24
// CHECK: st3 { v31.2s, v0.2s, v1.2s }, [sp], #24
// CHECK: // encoding: [0xff,0x4b,0x9f,0x0c]
//------------------------------------------------------------------------------
// Store multiple 4-element structures from four consecutive registers
// (post-index)
//------------------------------------------------------------------------------
st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1
st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2
st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64
st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64
st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3
st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4
st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32
// CHECK: st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1
st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1
st4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2
st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64
st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64
st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
st4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4
st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32
// CHECK: st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1
// CHECK: // encoding: [0x00,0x00,0x81,0x4c]
// CHECK: st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2
// CHECK: st4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2
// CHECK: // encoding: [0xef,0x05,0x82,0x4c]
// CHECK: st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64
// CHECK: st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64
// CHECK: // encoding: [0xff,0x0b,0x9f,0x4c]
// CHECK: st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64
// CHECK: st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64
// CHECK: // encoding: [0x00,0x0c,0x9f,0x4c]
// CHECK: st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3
// CHECK: st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
// CHECK: // encoding: [0x00,0x00,0x83,0x0c]
// CHECK: st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4
// CHECK: st4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4
// CHECK: // encoding: [0xef,0x05,0x84,0x0c]
// CHECK: st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32
// CHECK: st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32
// CHECK: // encoding: [0xff,0x0b,0x9f,0x0c]

80
test/MC/AArch64/neon-tbl.s
View File

@ -6,51 +6,51 @@
// Instructions across vector registers
//------------------------------------------------------------------------------
tbl v0.8b, {v1.16b}, v2.8b
tbl v0.8b, {v1.16b, v2.16b}, v2.8b
tbl v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b
tbl v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b
tbl v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b
tbl v0.8b, { v1.16b }, v2.8b
tbl v0.8b, { v1.16b, v2.16b }, v2.8b
tbl v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b
tbl v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b
tbl v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b
// CHECK: tbl v0.8b, {v1.16b}, v2.8b // encoding: [0x20,0x00,0x02,0x0e]
// CHECK: tbl v0.8b, {v1.16b, v2.16b}, v2.8b // encoding: [0x20,0x20,0x02,0x0e]
// CHECK: tbl v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b // encoding: [0x20,0x40,0x02,0x0e]
// CHECK: tbl v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b // encoding: [0x20,0x60,0x02,0x0e]
// CHECK: tbl v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b // encoding: [0xe0,0x63,0x02,0x0e]
// CHECK: tbl v0.8b, { v1.16b }, v2.8b // encoding: [0x20,0x00,0x02,0x0e]
// CHECK: tbl v0.8b, { v1.16b, v2.16b }, v2.8b // encoding: [0x20,0x20,0x02,0x0e]
// CHECK: tbl v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b // encoding: [0x20,0x40,0x02,0x0e]
// CHECK: tbl v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b // encoding: [0x20,0x60,0x02,0x0e]
// CHECK: tbl v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b // encoding: [0xe0,0x63,0x02,0x0e]
tbl v0.16b, {v1.16b}, v2.16b
tbl v0.16b, {v1.16b, v2.16b}, v2.16b
tbl v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b
tbl v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b
tbl v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b
tbl v0.16b, { v1.16b }, v2.16b
tbl v0.16b, { v1.16b, v2.16b }, v2.16b
tbl v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b
tbl v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b
tbl v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b
// CHECK: tbl v0.16b, {v1.16b}, v2.16b // encoding: [0x20,0x00,0x02,0x4e]
// CHECK: tbl v0.16b, {v1.16b, v2.16b}, v2.16b // encoding: [0x20,0x20,0x02,0x4e]
// CHECK: tbl v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b // encoding: [0x20,0x40,0x02,0x4e]
// CHECK: tbl v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b // encoding: [0x20,0x60,0x02,0x4e]
// CHECK: tbl v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b // encoding: [0xc0,0x63,0x02,0x4e]
// CHECK: tbl v0.16b, { v1.16b }, v2.16b // encoding: [0x20,0x00,0x02,0x4e]
// CHECK: tbl v0.16b, { v1.16b, v2.16b }, v2.16b // encoding: [0x20,0x20,0x02,0x4e]
// CHECK: tbl v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b // encoding: [0x20,0x40,0x02,0x4e]
// CHECK: tbl v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b // encoding: [0x20,0x60,0x02,0x4e]
// CHECK: tbl v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b // encoding: [0xc0,0x63,0x02,0x4e]
tbx v0.8b, {v1.16b}, v2.8b
tbx v0.8b, {v1.16b, v2.16b}, v2.8b
tbx v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b
tbx v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b
tbx v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b
tbx v0.8b, { v1.16b }, v2.8b
tbx v0.8b, { v1.16b, v2.16b }, v2.8b
tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b
tbx v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b
tbx v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b
// CHECK: tbx v0.8b, {v1.16b}, v2.8b // encoding: [0x20,0x10,0x02,0x0e]
// CHECK: tbx v0.8b, {v1.16b, v2.16b}, v2.8b // encoding: [0x20,0x30,0x02,0x0e]
// CHECK: tbx v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b // encoding: [0x20,0x50,0x02,0x0e]
// CHECK: tbx v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b // encoding: [0x20,0x70,0x02,0x0e]
// CHECK: tbx v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b // encoding: [0xe0,0x73,0x02,0x0e]
// CHECK: tbx v0.8b, { v1.16b }, v2.8b // encoding: [0x20,0x10,0x02,0x0e]
// CHECK: tbx v0.8b, { v1.16b, v2.16b }, v2.8b // encoding: [0x20,0x30,0x02,0x0e]
// CHECK: tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b // encoding: [0x20,0x50,0x02,0x0e]
// CHECK: tbx v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b // encoding: [0x20,0x70,0x02,0x0e]
// CHECK: tbx v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b // encoding: [0xe0,0x73,0x02,0x0e]
tbx v0.16b, {v1.16b}, v2.16b
tbx v0.16b, {v1.16b, v2.16b}, v2.16b
tbx v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b
tbx v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b
tbx v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b
tbx v0.16b, { v1.16b }, v2.16b
tbx v0.16b, { v1.16b, v2.16b }, v2.16b
tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b
tbx v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b
tbx v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b
// CHECK: tbx v0.16b, {v1.16b}, v2.16b // encoding: [0x20,0x10,0x02,0x4e]
// CHECK: tbx v0.16b, {v1.16b, v2.16b}, v2.16b // encoding: [0x20,0x30,0x02,0x4e]
// CHECK: tbx v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b // encoding: [0x20,0x50,0x02,0x4e]
// CHECK: tbx v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b // encoding: [0x20,0x70,0x02,0x4e]
// CHECK: tbx v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b // encoding: [0xc0,0x73,0x02,0x4e]
// CHECK: tbx v0.16b, { v1.16b }, v2.16b // encoding: [0x20,0x10,0x02,0x4e]
// CHECK: tbx v0.16b, { v1.16b, v2.16b }, v2.16b // encoding: [0x20,0x30,0x02,0x4e]
// CHECK: tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b // encoding: [0x20,0x50,0x02,0x4e]
// CHECK: tbx v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b // encoding: [0x20,0x70,0x02,0x4e]
// CHECK: tbx v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b // encoding: [0xc0,0x73,0x02,0x4e]

154
test/MC/Disassembler/AArch64/neon-instructions.txt
View File

@ -2008,34 +2008,34 @@
#----------------------------------------------------------------------
# Vector load/store multiple N-element structure
#----------------------------------------------------------------------
# CHECK: ld1 {v0.16b}, [x0]
# CHECK: ld1 {v15.8h, v16.8h}, [x15]
# CHECK: ld1 {v31.4s, v0.4s, v1.4s}, [sp]
# CHECK: ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0]
# CHECK: ld1 { v0.16b }, [x0]
# CHECK: ld1 { v15.8h, v16.8h }, [x15]
# CHECK: ld1 { v31.4s, v0.4s, v1.4s }, [sp]
# CHECK: ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
0x00,0x70,0x40,0x4c
0xef,0xa5,0x40,0x4c
0xff,0x6b,0x40,0x4c
0x00,0x2c,0x40,0x4c
# CHECK: ld2 {v0.8b, v1.8b}, [x0]
# CHECK: ld3 {v15.4h, v16.4h, v17.4h}, [x15]
# CHECK: ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp]
# CHECK: ld2 { v0.8b, v1.8b }, [x0]
# CHECK: ld3 { v15.4h, v16.4h, v17.4h }, [x15]
# CHECK: ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]
0x00,0x80,0x40,0x0c
0xef,0x45,0x40,0x0c
0xff,0x0b,0x40,0x0c
# CHECK: st1 {v0.16b}, [x0]
# CHECK: st1 {v15.8h, v16.8h}, [x15]
# CHECK: st1 {v31.4s, v0.4s, v1.4s}, [sp]
# CHECK: st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0]
# CHECK: st1 { v0.16b }, [x0]
# CHECK: st1 { v15.8h, v16.8h }, [x15]
# CHECK: st1 { v31.4s, v0.4s, v1.4s }, [sp]
# CHECK: st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
0x00,0x70,0x00,0x4c
0xef,0xa5,0x00,0x4c
0xff,0x6b,0x00,0x4c
0x00,0x2c,0x00,0x4c
# CHECK: st2 {v0.8b, v1.8b}, [x0]
# CHECK: st3 {v15.4h, v16.4h, v17.4h}, [x15]
# CHECK: st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp]
# CHECK: st2 { v0.8b, v1.8b }, [x0]
# CHECK: st3 { v15.4h, v16.4h, v17.4h }, [x15]
# CHECK: st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]
0x00,0x80,0x00,0x0c
0xef,0x45,0x00,0x0c
0xff,0x0b,0x00,0x0c
@ -2043,35 +2043,35 @@
#----------------------------------------------------------------------
# Vector load/store multiple N-element structure (post-index)
#----------------------------------------------------------------------
# CHECK: ld1 {v15.8h}, [x15], x2
# CHECK: ld1 {v31.4s, v0.4s}, [sp], #32
# CHECK: ld1 {v0.2d, v1.2d, v2.2d}, [x0], #48
# CHECK: ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3
# CHECK: ld1 { v15.8h }, [x15], x2
# CHECK: ld1 { v31.4s, v0.4s }, [sp], #32
# CHECK: ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48
# CHECK: ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
0xef,0x75,0xc2,0x4c
0xff,0xab,0xdf,0x4c
0x00,0x6c,0xdf,0x4c
0x00,0x20,0xc3,0x0c
# CHECK: ld2 {v0.16b, v1.16b}, [x0], x1
# CHECK: ld3 {v15.8h, v16.8h, v17.8h}, [x15], x2
# CHECK: ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64
# CHECK: ld2 { v0.16b, v1.16b }, [x0], x1
# CHECK: ld3 { v15.8h, v16.8h, v17.8h }, [x15], x2
# CHECK: ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64
0x00,0x80,0xc1,0x4c
0xef,0x45,0xc2,0x4c
0xff,0x0b,0xdf,0x4c
# CHECK: st1 {v15.8h}, [x15], x2
# CHECK: st1 {v31.4s, v0.4s}, [sp], #32
# CHECK: st1 {v0.2d, v1.2d, v2.2d}, [x0], #48
# CHECK: st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3
# CHECK: st1 { v15.8h }, [x15], x2
# CHECK: st1 { v31.4s, v0.4s }, [sp], #32
# CHECK: st1 { v0.2d, v1.2d, v2.2d }, [x0], #48
# CHECK: st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3
0xef,0x75,0x82,0x4c
0xff,0xab,0x9f,0x4c
0x00,0x6c,0x9f,0x4c
0x00,0x20,0x83,0x0c
# CHECK: st2 {v0.16b, v1.16b}, [x0], x1
# CHECK: st3 {v15.8h, v16.8h, v17.8h}, [x15], x2
# CHECK: st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64
# CHECK: st2 { v0.16b, v1.16b }, [x0], x1
# CHECK: st3 { v15.8h, v16.8h, v17.8h }, [x15], x2
# CHECK: st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64
0x00,0x80,0x81,0x4c
0xef,0x45,0x82,0x4c
0xff,0x0b,0x9f,0x4c
@ -2080,14 +2080,14 @@
# Vector load single N-element structure to all lane of N
# consecutive registers (N = 1,2,3,4)
#----------------------------------------------------------------------
# CHECK: ld1r {v0.16b}, [x0]
# CHECK: ld1r {v15.8h}, [x15]
# CHECK: ld2r {v31.4s, v0.4s}, [sp]
# CHECK: ld2r {v0.2d, v1.2d}, [x0]
# CHECK: ld3r {v0.8b, v1.8b, v2.8b}, [x0]
# CHECK: ld3r {v15.4h, v16.4h, v17.4h}, [x15]
# CHECK: ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp]
# CHECK: ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp]
# CHECK: ld1r { v0.16b }, [x0]
# CHECK: ld1r { v15.8h }, [x15]
# CHECK: ld2r { v31.4s, v0.4s }, [sp]
# CHECK: ld2r { v0.2d, v1.2d }, [x0]
# CHECK: ld3r { v0.8b, v1.8b, v2.8b }, [x0]
# CHECK: ld3r { v15.4h, v16.4h, v17.4h }, [x15]
# CHECK: ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]
# CHECK: ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp]
0x00,0xc0,0x40,0x4d
0xef,0xc5,0x40,0x4d
0xff,0xcb,0x60,0x4d
@ -2101,14 +2101,14 @@
# Vector load/store single N-element structure to/from one lane of N
# consecutive registers (N = 1,2,3,4)
#----------------------------------------------------------------------
# CHECK: ld1 {v0.b}[9], [x0]
# CHECK: ld2 {v15.h, v16.h}[7], [x15]
# CHECK: ld3 {v31.s, v0.s, v1.s}[3], [sp]
# CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0]
# CHECK: st1 {v0.d}[1], [x0]
# CHECK: st2 {v31.s, v0.s}[3], [sp]
# CHECK: st3 {v15.h, v16.h, v17.h}[7], [x15]
# CHECK: st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0]
# CHECK: ld1 { v0.b }[9], [x0]
# CHECK: ld2 { v15.h, v16.h }[7], [x15]
# CHECK: ld3 { v31.s, v0.s, v1.s }[3], [sp]
# CHECK: ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0]
# CHECK: st1 { v0.d }[1], [x0]
# CHECK: st2 { v31.s, v0.s }[3], [sp]
# CHECK: st3 { v15.h, v16.h, v17.h }[7], [x15]
# CHECK: st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0]
0x00,0x04,0x40,0x4d
0xef,0x59,0x60,0x4d
0xff,0xb3,0x40,0x4d
@ -2122,14 +2122,14 @@
# Post-index of vector load single N-element structure to all lane of N
# consecutive registers (N = 1,2,3,4)
#----------------------------------------------------------------------
# CHECK: ld1r {v0.16b}, [x0], #1
# CHECK: ld1r {v15.8h}, [x15], #2
# CHECK: ld2r {v31.4s, v0.4s}, [sp], #8
# CHECK: ld2r {v0.2d, v1.2d}, [x0], #16
# CHECK: ld3r {v0.8b, v1.8b, v2.8b}, [x0], #3
# CHECK: ld3r {v15.4h, v16.4h, v17.4h}, [x15], #6
# CHECK: ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], x30
# CHECK: ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp], x7
# CHECK: ld1r { v0.16b }, [x0], #1
# CHECK: ld1r { v15.8h }, [x15], #2
# CHECK: ld2r { v31.4s, v0.4s }, [sp], #8
# CHECK: ld2r { v0.2d, v1.2d }, [x0], #16
# CHECK: ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3
# CHECK: ld3r { v15.4h, v16.4h, v17.4h }, [x15], #6
# CHECK: ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], x30
# CHECK: ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp], x7
0x00,0xc0,0xdf,0x4d
0xef,0xc5,0xdf,0x4d
0xff,0xcb,0xff,0x4d
@ -2143,15 +2143,15 @@
# Post-index of vector load/store single N-element structure to/from
# one lane of N consecutive registers (N = 1,2,3,4)
#----------------------------------------------------------------------
# CHECK: ld1 {v0.b}[9], [x0], #1
# CHECK: ld2 {v15.h, v16.h}[7], [x15], #4
# CHECK: ld3 {v31.s, v0.s, v1.s}[3], [sp], x3
# CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32
# CHECK: ld4 {v0.h, v1.h, v2.h, v3.h}[7], [x0], x0
# CHECK: st1 {v0.d}[1], [x0], #8
# CHECK: st2 {v31.s, v0.s}[3], [sp], #8
# CHECK: st3 {v15.h, v16.h, v17.h}[7], [x15], #6
# CHECK: st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5
# CHECK: ld1 { v0.b }[9], [x0], #1
# CHECK: ld2 { v15.h, v16.h }[7], [x15], #4
# CHECK: ld3 { v31.s, v0.s, v1.s }[3], [sp], x3
# CHECK: ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32
# CHECK: ld4 { v0.h, v1.h, v2.h, v3.h }[7], [x0], x0
# CHECK: st1 { v0.d }[1], [x0], #8
# CHECK: st2 { v31.s, v0.s }[3], [sp], #8
# CHECK: st3 { v15.h, v16.h, v17.h }[7], [x15], #6
# CHECK: st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5
0x00,0x04,0xdf,0x4d
0xef,0x59,0xff,0x4d
0xff,0xb3,0xc3,0x4d
@ -2497,37 +2497,37 @@
0xf0,0x23,0x02,0x0e
0x20,0x40,0x02,0x0e
0xf0,0x62,0x02,0x0e
# CHECK: tbl v0.8b, {v1.16b}, v2.8b
# CHECK: tbl v16.8b, {v31.16b, v0.16b}, v2.8b
# CHECK: tbl v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b
# CHECK: tbl v16.8b, {v23.16b, v24.16b, v25.16b, v26.16b}, v2.8b
# CHECK: tbl v0.8b, { v1.16b }, v2.8b
# CHECK: tbl v16.8b, { v31.16b, v0.16b }, v2.8b
# CHECK: tbl v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b
# CHECK: tbl v16.8b, { v23.16b, v24.16b, v25.16b, v26.16b }, v2.8b
0x20,0x00,0x02,0x4e
0xf0,0x23,0x02,0x4e
0x20,0x40,0x02,0x4e
0xe0,0x63,0x02,0x4e
# CHECK: tbl v0.16b, {v1.16b}, v2.16b
# CHECK: tbl v16.16b, {v31.16b, v0.16b}, v2.16b
# CHECK: tbl v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b
# CHECK: tbl v0.16b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.16b
# CHECK: tbl v0.16b, { v1.16b }, v2.16b
# CHECK: tbl v16.16b, { v31.16b, v0.16b }, v2.16b
# CHECK: tbl v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b
# CHECK: tbl v0.16b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.16b
0x20,0x10,0x02,0x0e
0xf0,0x33,0x02,0x0e
0x20,0x50,0x02,0x0e
0xf0,0x72,0x02,0x0e
# CHECK: tbx v0.8b, {v1.16b}, v2.8b
# CHECK: tbx v16.8b, {v31.16b, v0.16b}, v2.8b
# CHECK: tbx v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b
# CHECK: tbx v16.8b, {v23.16b, v24.16b, v25.16b, v26.16b}, v2.8b
# CHECK: tbx v0.8b, { v1.16b }, v2.8b
# CHECK: tbx v16.8b, { v31.16b, v0.16b }, v2.8b
# CHECK: tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b
# CHECK: tbx v16.8b, { v23.16b, v24.16b, v25.16b, v26.16b }, v2.8b
0x20,0x10,0x02,0x4e
0xf0,0x33,0x02,0x4e
0x20,0x50,0x02,0x4e
0xf0,0x73,0x02,0x4e
# CHECK: tbx v0.16b, {v1.16b}, v2.16b
# CHECK: tbx v16.16b, {v31.16b, v0.16b}, v2.16b
# CHECK: tbx v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b
# CHECK: tbx v16.16b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.16b
# CHECK: tbx v0.16b, { v1.16b }, v2.16b
# CHECK: tbx v16.16b, { v31.16b, v0.16b }, v2.16b
# CHECK: tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b
# CHECK: tbx v16.16b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.16b
#----------------------------------------------------------------------
# Scalar Floating-point Convert To Lower Precision Narrow, Rounding To