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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26848 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-03-19 01:13:28 +00:00
parent b2827b0901
commit a064d28843
2 changed files with 12 additions and 12 deletions
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6
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -179,10 +179,10 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
setOperationAction(ISD::LOAD , MVT::v4f32, Legal); setOperationAction(ISD::LOAD , MVT::v4f32, Legal);
setOperationAction(ISD::ADD , MVT::v4i32, Legal); setOperationAction(ISD::ADD , MVT::v4i32, Legal);
setOperationAction(ISD::LOAD , MVT::v4i32, Legal); setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
// FIXME: We don't support any ConstantVec's yet. We should custom expand // FIXME: We don't support any BUILD_VECTOR's yet. We should custom expand
// the ones we do! // the ones we do!
setOperationAction(ISD::ConstantVec, MVT::v4f32, Expand); setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Expand);
setOperationAction(ISD::ConstantVec, MVT::v4i32, Expand); setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Expand);
} }
setSetCCResultContents(ZeroOrOneSetCCResult); setSetCCResultContents(ZeroOrOneSetCCResult);

18
lib/Target/X86/X86ISelLowering.cpp
View File

@ -263,9 +263,9 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
addRegisterClass(MVT::v2i32, X86::VR64RegisterClass); addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
// FIXME: add MMX packed arithmetics // FIXME: add MMX packed arithmetics
setOperationAction(ISD::ConstantVec, MVT::v8i8, Expand); setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
setOperationAction(ISD::ConstantVec, MVT::v4i16, Expand); setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
setOperationAction(ISD::ConstantVec, MVT::v2i32, Expand); setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand);
} }
if (TM.getSubtarget<X86Subtarget>().hasSSE1()) { if (TM.getSubtarget<X86Subtarget>().hasSSE1()) {
@ -275,7 +275,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
setOperationAction(ISD::SUB , MVT::v4f32, Legal); setOperationAction(ISD::SUB , MVT::v4f32, Legal);
setOperationAction(ISD::MUL , MVT::v4f32, Legal); setOperationAction(ISD::MUL , MVT::v4f32, Legal);
setOperationAction(ISD::LOAD , MVT::v4f32, Legal); setOperationAction(ISD::LOAD , MVT::v4f32, Legal);
setOperationAction(ISD::ConstantVec, MVT::v4f32, Expand); setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Expand);
} }
if (TM.getSubtarget<X86Subtarget>().hasSSE2()) { if (TM.getSubtarget<X86Subtarget>().hasSSE2()) {
@ -290,11 +290,11 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
setOperationAction(ISD::SUB , MVT::v2f64, Legal); setOperationAction(ISD::SUB , MVT::v2f64, Legal);
setOperationAction(ISD::MUL , MVT::v2f64, Legal); setOperationAction(ISD::MUL , MVT::v2f64, Legal);
setOperationAction(ISD::LOAD , MVT::v2f64, Legal); setOperationAction(ISD::LOAD , MVT::v2f64, Legal);
setOperationAction(ISD::ConstantVec, MVT::v2f64, Expand); setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Expand);
setOperationAction(ISD::ConstantVec, MVT::v16i8, Expand); setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Expand);
setOperationAction(ISD::ConstantVec, MVT::v8i16, Expand); setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Expand);
setOperationAction(ISD::ConstantVec, MVT::v4i32, Expand); setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Expand);
setOperationAction(ISD::ConstantVec, MVT::v2i64, Expand); setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Expand);
} }
computeRegisterProperties(); computeRegisterProperties();