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Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't

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optimize it to a SINT_TO_FP when the sign bit is known zero. X86 isel should perform the optimization itself.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62504 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-01-19 08:08:22 +00:00
parent c4f85dd708
commit a06ec9efe1
2 changed files with 9 additions and 1 deletions
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9
lib/Target/X86/X86ISelLowering.cpp
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@ -4884,8 +4884,15 @@ SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
}
SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
MVT SrcVT = Op.getOperand(0).getValueType();
SDValue N0 = Op.getOperand(0);
// Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
// optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
// the optimization here.
if (DAG.SignBitIsZero(N0))
return DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), N0);
MVT SrcVT = N0.getValueType();
if (SrcVT == MVT::i64) {
// We only handle SSE2 f64 target here; caller can handle the rest.
if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)

1
test/CodeGen/X86/uint_to_fp.ll
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@ -1,4 +1,5 @@
; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | not grep {sub.*esp}
; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | grep cvtsi2ss
; rdar://6034396
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"