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Use the new predicate support that Evan Cheng added to remove some code
from the DAGToDAG cpp file. This adds pattern support for vector and
scalar fma, which passes test/Regression/CodeGen/PowerPC/fma.ll, and
does the right thing in the presence of -disable-excess-fp-precision.
Allows us to match:
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
%tmp3 = add <4 x float> %tmp2, %tmp1
store <4 x float> %tmp3, <4 x float> *%a
ret void
}
As:
_foo:
li r2, 0
lvx v0, r2, r3
vmaddfp v0, v0, v0, v0
stvx v0, r2, r3
blr
Or, with llc -disable-excess-fp-precision,
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v1, v0, v0, v1
vaddfp v0, v1, v0
stvx v0, r2, r3
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24719 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman
parent
1dae25e23a
commit
a07da92624
@ -885,53 +885,6 @@ SDOperand PPCDAGToDAGISel::Select(SDOperand Op) {
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CurDAG->getTargetFrameIndex(FI, MVT::i32),
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getI32Imm(0));
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}
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case ISD::FADD: {
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MVT::ValueType Ty = N->getValueType(0);
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if (!NoExcessFPPrecision) { // Match FMA ops
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if (N->getOperand(0).getOpcode() == ISD::FMUL &&
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N->getOperand(0).Val->hasOneUse()) {
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++FusedFP; // Statistic
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return CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMADD :PPC::FMADDS,
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Ty, Select(N->getOperand(0).getOperand(0)),
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Select(N->getOperand(0).getOperand(1)),
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Select(N->getOperand(1)));
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} else if (N->getOperand(1).getOpcode() == ISD::FMUL &&
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N->getOperand(1).hasOneUse()) {
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++FusedFP; // Statistic
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return CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMADD :PPC::FMADDS,
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Ty, Select(N->getOperand(1).getOperand(0)),
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Select(N->getOperand(1).getOperand(1)),
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Select(N->getOperand(0)));
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}
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}
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// Other cases are autogenerated.
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break;
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}
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case ISD::FSUB: {
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MVT::ValueType Ty = N->getValueType(0);
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if (!NoExcessFPPrecision) { // Match FMA ops
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if (N->getOperand(0).getOpcode() == ISD::FMUL &&
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N->getOperand(0).Val->hasOneUse()) {
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++FusedFP; // Statistic
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return CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMSUB:PPC::FMSUBS,
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Ty, Select(N->getOperand(0).getOperand(0)),
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Select(N->getOperand(0).getOperand(1)),
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Select(N->getOperand(1)));
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} else if (N->getOperand(1).getOpcode() == ISD::FMUL &&
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N->getOperand(1).Val->hasOneUse()) {
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++FusedFP; // Statistic
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return CurDAG->SelectNodeTo(N, Ty == MVT::f64 ?PPC::FNMSUB:PPC::FNMSUBS,
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Ty, Select(N->getOperand(1).getOperand(0)),
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Select(N->getOperand(1).getOperand(1)),
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Select(N->getOperand(0)));
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}
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}
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// Other cases are autogenerated.
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break;
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}
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case ISD::SDIV: {
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// FIXME: since this depends on the setting of the carry flag from the srawi
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// we should really be making notes about that for the scheduler.
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@ -168,7 +168,7 @@ def crbitm: Operand<i8> {
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//===----------------------------------------------------------------------===//
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// PowerPC Instruction Predicate Definitions.
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def FPContractions : Predicate<"!NoExcessFPPrecision">;
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def FPContractions : Predicate<"NoExcessFPPrecision">;
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//===----------------------------------------------------------------------===//
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// PowerPC Instruction Definitions.
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@ -746,22 +746,26 @@ def FNMADD : AForm_1<63, 31,
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(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
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"fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
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[(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
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F8RC:$FRB)))]>;
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F8RC:$FRB)))]>,
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Requires<[FPContractions]>;
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def FNMADDS : AForm_1<59, 31,
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(ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
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"fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
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[(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
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F4RC:$FRB)))]>;
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F4RC:$FRB)))]>,
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Requires<[FPContractions]>;
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def FNMSUB : AForm_1<63, 30,
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(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
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"fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
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[(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
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F8RC:$FRB)))]>;
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F8RC:$FRB)))]>,
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Requires<[FPContractions]>;
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def FNMSUBS : AForm_1<59, 30,
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(ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
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"fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
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[(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
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F4RC:$FRB)))]>;
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F4RC:$FRB)))]>,
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Requires<[FPContractions]>;
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// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
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// having 4 of these, force the comparison to always be an 8-byte double (code
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// should use an FMRSD if the input comparison value really wants to be a float)
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@ -848,12 +852,14 @@ def RLDICR : MDForm_1<30, 1,
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def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
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"vmaddfp $vD, $vA, $vC, $vB", VecFP,
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[(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
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VRRC:$vB))]>;
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VRRC:$vB))]>,
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Requires<[FPContractions]>;
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def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
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"vnmsubfp $vD, $vA, $vC, $vB", VecFP,
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[(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA,
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VRRC:$vC),
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VRRC:$vB)))]>;
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"vnmsubfp $vD, $vA, $vC, $vB", VecFP,
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[(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA,
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VRRC:$vC),
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VRRC:$vB)))]>,
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Requires<[FPContractions]>;
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// VX-Form instructions. AltiVec arithmetic ops.
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def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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@ -971,6 +977,14 @@ def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
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def : Pat<(fmul VRRC:$vA, VRRC:$vB),
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(VMADDFP VRRC:$vA, (V_SET0), VRRC:$vB)>;
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// Fused negative multiply subtract, alternate pattern
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def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
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(FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
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Requires<[FPContractions]>;
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def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
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(FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
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Requires<[FPContractions]>;
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// Fused multiply add and multiply sub for packed float. These are represented
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// separately from the real instructions above, for operations that must have
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// the additional precision, such as Newton-Rhapson (used by divide, sqrt)
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