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ARM/MC/ELF TPsoft is now a proper pseudo inst.

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Added test to check bl __aeabi_read_tp gets emitted properly for ELF/ASM
as well as ELF/OBJ (including fixup)

Also added support for ELF::R_ARM_TLS_IE32



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121312 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jason W Kim 2010-12-08 23:14:44 +00:00
parent 7685ff84ad
commit a0871e7927
4 changed files with 83 additions and 9 deletions
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18
lib/MC/ELFObjectWriter.cpp
View File

@ -1533,6 +1533,7 @@ unsigned ARMELFObjectWriter::GetRelocType(const MCValue &Target,
MCSymbolRefExpr::VariantKind Modifier = Target.isAbsolute() ?
MCSymbolRefExpr::VK_None : Target.getSymA()->getKind();
unsigned Type = 0;
if (IsPCRel) {
switch (Modifier) {
default: assert(0 && "Unimplemented Modifier");
@ -1540,11 +1541,17 @@ unsigned ARMELFObjectWriter::GetRelocType(const MCValue &Target,
}
switch ((unsigned)Fixup.getKind()) {
default: assert(0 && "Unimplemented");
case ARM::fixup_arm_branch: return ELF::R_ARM_CALL; break;
case ARM::fixup_arm_branch: Type = ELF::R_ARM_CALL; break;
}
} else {
switch ((unsigned)Fixup.getKind()) {
default: llvm_unreachable("invalid fixup kind!");
case FK_Data_4:
switch (Modifier) {
default: llvm_unreachable("Unsupported Modifier");
case MCSymbolRefExpr::VK_ARM_GOTTPOFF:
Type = ELF::R_ARM_TLS_IE32;
} break;
case ARM::fixup_arm_ldst_pcrel_12:
case ARM::fixup_arm_pcrel_10:
case ARM::fixup_arm_adr_pcrel_12:
@ -1553,17 +1560,18 @@ unsigned ARMELFObjectWriter::GetRelocType(const MCValue &Target,
case ARM::fixup_arm_thumb_cp:
assert(0 && "Unimplemented"); break;
case ARM::fixup_arm_branch:
return ELF::R_ARM_CALL; break;
Type = ELF::R_ARM_CALL; break;
case ARM::fixup_arm_movt_hi16:
return ELF::R_ARM_MOVT_ABS; break;
Type = ELF::R_ARM_MOVT_ABS; break;
case ARM::fixup_arm_movw_lo16:
return ELF::R_ARM_MOVW_ABS_NC; break;
Type = ELF::R_ARM_MOVW_ABS_NC; break;
}
}
if (RelocNeedsGOT(Modifier))
NeedsGOT = true;
return -1;
return Type;
}
//===- MBlazeELFObjectWriter -------------------------------------------===//

15
lib/Target/ARM/ARMExpandPseudoInsts.cpp
View File

@ -699,6 +699,21 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
MI.eraseFromParent();
break;
}
case ARM::TPsoft: {
unsigned PredReg = 0;
ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg);
MachineInstrBuilder MIB =
BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(ARM::BL))
.addExternalSymbol("__aeabi_read_tp", 0);
(*MIB).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
TransferImpOps(MI, MIB, MIB);
MI.eraseFromParent();
//assert(0 && "HELP!");
}; break;
case ARM::t2LDRHpci:
case ARM::t2LDRBpci:
case ARM::t2LDRSHpci:

7
lib/Target/ARM/ARMInstrInfo.td
View File

@ -3249,12 +3249,11 @@ def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
//
// __aeabi_read_tp preserves the registers r1-r3.
// FIXME: This needs to be a pseudo of some sort so that we can get the
// encoding right, complete with fixup for the aeabi_read_tp function.
// This is a pseudo inst so that we can get the encoding right,
// complete with fixup for the aeabi_read_tp function.
let isCall = 1,
Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
"bl\t__aeabi_read_tp",
def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
[(set R0, ARMthread_pointer)]>;
}

52
test/CodeGen/ARM/2010-12-08-tpsoft.ll Normal file
View File

@ -0,0 +1,52 @@
; RUN: llc %s -mtriple=armv7-linux-gnueabi -o - | \
; RUN: FileCheck -check-prefix=ELFASM %s
; RUN: llc %s -mtriple=armv7-linux-gnueabi -filetype=obj -o - | \
; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=ELFOBJ %s
;; Make sure that bl __aeabi_read_tp is materiazlied and fixed up correctly
;; in the obj case.
@i = external thread_local global i32
@a = external global i8
@b = external global [10 x i8]
define arm_aapcs_vfpcc i32 @main() nounwind {
entry:
%0 = load i32* @i, align 4
switch i32 %0, label %bb2 [
i32 12, label %bb
i32 13, label %bb1
]
bb: ; preds = %entry
%1 = tail call arm_aapcs_vfpcc i32 @foo(i8* @a) nounwind
ret i32 %1
; ELFASM: bl __aeabi_read_tp
; ELFOBJ: '.text'
; ELFOBJ-NEXT: 'sh_type'
; ELFOBJ-NEXT: 'sh_flags'
; ELFOBJ-NEXT: 'sh_addr'
; ELFOBJ-NEXT: 'sh_offset'
; ELFOBJ-NEXT: 'sh_size'
; ELFOBJ-NEXT: 'sh_link'
; ELFOBJ-NEXT: 'sh_info'
; ELFOBJ-NEXT: 'sh_addralign'
; ELFOBJ-NEXT: 'sh_entsize'
;;; BL __aeabi_read_tp is ---+
;;; V
; ELFOBJ-NEXT: 00482de9 3c009fe5 00109fe7 feffffeb
bb1: ; preds = %entry
%2 = tail call arm_aapcs_vfpcc i32 @bar(i32* bitcast ([10 x i8]* @b to i32*)) nounwind
ret i32 %2
bb2: ; preds = %entry
ret i32 -1
}
declare arm_aapcs_vfpcc i32 @foo(i8*)
declare arm_aapcs_vfpcc i32 @bar(i32*)