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Prevents PerformShuffleCombine from creating a node with an illegal type after legalize types

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has run, e.g., prevent creating an i64 node from a v2i64 when i64 is not a legal type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122206 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Mon P Wang 2010-12-19 23:55:53 +00:00
parent 1b031ddede
commit a0fd0d5b27
2 changed files with 31 additions and 6 deletions
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9
lib/Target/X86/X86ISelLowering.cpp
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@ -10372,13 +10372,18 @@ bool X86TargetLowering::isGAPlusOffset(SDNode *N,
/// if the load addresses are consecutive, non-overlapping, and in the right
/// order.
static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
const TargetLowering &TLI) {
TargetLowering::DAGCombinerInfo &DCI) {
DebugLoc dl = N->getDebugLoc();
EVT VT = N->getValueType(0);
if (VT.getSizeInBits() != 128)
return SDValue();
// Don't create instructions with illegal types after legalize types has run.
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
return SDValue();
SmallVector<SDValue, 16> Elts;
for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
@ -11485,7 +11490,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
case X86ISD::PSHUFLW:
case X86ISD::MOVSS:
case X86ISD::MOVSD:
case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI);
}
return SDValue();

28
test/CodeGen/X86/vec_shuffle-27.ll
View File

@ -1,7 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=sse41 -o %t
; RUN: grep addps %t | count 2
; RUN: grep mulps %t | count 2
; RUN: grep subps %t | count 2
; RUN: llc < %s -march=x86 -mattr=sse41 | FileCheck %s
; ModuleID = 'vec_shuffle-27.bc'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
@ -9,9 +6,32 @@ target triple = "i686-apple-cl.1.0"
define <8 x float> @my2filter4_1d(<4 x float> %a, <8 x float> %T0, <8 x float> %T1) nounwind readnone {
entry:
; CHECK: subps
; CHECK: mulps
; CHECK: addps
; CHECK: subps
; CHECK: mulps
; CHECK: addps
%tmp7 = shufflevector <4 x float> %a, <4 x float> undef, <8 x i32> < i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3 > ; <<8 x float>> [#uses=1]
%sub = fsub <8 x float> %T1, %T0 ; <<8 x float>> [#uses=1]
%mul = fmul <8 x float> %sub, %tmp7 ; <<8 x float>> [#uses=1]
%add = fadd <8 x float> %mul, %T0 ; <<8 x float>> [#uses=1]
ret <8 x float> %add
}
define void @test2(<4 x i64>* %ap, <4 x i64>* %bp) nounwind {
entry:
%a = load <4 x i64> * %ap
%b = load <4 x i64> * %bp
%mulaa = mul <4 x i64> %a, %a
%mulbb = mul <4 x i64> %b, %b
%mulab = mul <4 x i64> %a, %b
%vect1271 = shufflevector <4 x i64> %mulaa, <4 x i64> %mulbb, <4 x i32> <i32 0, i32 4, i32 undef, i32 undef>
%vect1272 = shufflevector <4 x i64> %mulaa, <4 x i64> %mulbb, <4 x i32> <i32 1, i32 5, i32 undef, i32 undef>
%vect1487 = shufflevector <4 x i64> %vect1271, <4 x i64> %mulab, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
%vect1488 = shufflevector <4 x i64> %vect1272, <4 x i64> %mulab, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
store <4 x i64> %vect1487, <4 x i64>* %ap
store <4 x i64> %vect1488, <4 x i64>* %bp
ret void;
}