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[AArch64] Optimize some simple TBZ/TBNZ cases.
Summary: Add some AArch64 dag combines to optimize some simple TBZ/TBNZ cases: (tbz (and x, m), b) -> (tbz x, b) (tbz (shl x, c), b) -> (tbz x, b-c) (tbz (shr x, c), b) -> (tbz x, b+c) (tbz (xor x, -1), b) -> (tbnz x, b) Reviewers: jmolloy, mcrosier, t.p.northover Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D15702 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256765 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Geoff Berry
parent
d84e2865f6
commit
a1c12525dc
@ -9491,6 +9491,103 @@ static SDValue performBRCONDCombine(SDNode *N,
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return SDValue();
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}
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// Optimize some simple tbz/tbnz cases. Returns the new operand and bit to test
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// as well as whether the test should be inverted. This code is required to
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// catch these cases (as opposed to standard dag combines) because
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// AArch64ISD::TBZ is matched during legalization.
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static SDValue getTestBitOperand(SDValue Op, unsigned &Bit, bool &Invert,
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SelectionDAG &DAG) {
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if (!Op->hasOneUse())
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return Op;
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// We don't handle undef/constant-fold cases below, as they should have
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// already been taken care of (e.g. and of 0, test of undefined shifted bits,
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// etc.)
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// (tbz (trunc x), b) -> (tbz x, b)
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// This case is just here to enable more of the below cases to be caught.
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if (Op->getOpcode() == ISD::TRUNCATE &&
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Bit < Op->getValueType(0).getSizeInBits()) {
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return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
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}
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if (Op->getNumOperands() != 2)
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return Op;
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auto *C = dyn_cast<ConstantSDNode>(Op->getOperand(1));
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if (!C)
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return Op;
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switch (Op->getOpcode()) {
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default:
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return Op;
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// (tbz (and x, m), b) -> (tbz x, b)
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case ISD::AND:
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if ((C->getZExtValue() >> Bit) & 1)
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return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
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return Op;
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// (tbz (shl x, c), b) -> (tbz x, b-c)
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case ISD::SHL:
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if (C->getZExtValue() <= Bit &&
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(Bit - C->getZExtValue()) < Op->getValueType(0).getSizeInBits()) {
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Bit = Bit - C->getZExtValue();
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return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
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}
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return Op;
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// (tbz (sra x, c), b) -> (tbz x, b+c) or (tbz x, msb) if b+c is > # bits in x
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case ISD::SRA:
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Bit = Bit + C->getZExtValue();
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if (Bit >= Op->getValueType(0).getSizeInBits())
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Bit = Op->getValueType(0).getSizeInBits() - 1;
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return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
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// (tbz (srl x, c), b) -> (tbz x, b+c)
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case ISD::SRL:
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if ((Bit + C->getZExtValue()) < Op->getValueType(0).getSizeInBits()) {
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Bit = Bit + C->getZExtValue();
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return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
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}
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return Op;
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// (tbz (xor x, -1), b) -> (tbnz x, b)
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case ISD::XOR:
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if ((C->getZExtValue() >> Bit) & 1)
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Invert = !Invert;
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return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
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}
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}
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// Optimize test single bit zero/non-zero and branch.
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static SDValue performTBZCombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI,
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SelectionDAG &DAG) {
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unsigned Bit = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
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bool Invert = false;
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SDValue TestSrc = N->getOperand(1);
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SDValue NewTestSrc = getTestBitOperand(TestSrc, Bit, Invert, DAG);
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if (TestSrc == NewTestSrc)
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return SDValue();
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unsigned NewOpc = N->getOpcode();
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if (Invert) {
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if (NewOpc == AArch64ISD::TBZ)
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NewOpc = AArch64ISD::TBNZ;
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else {
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assert(NewOpc == AArch64ISD::TBNZ);
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NewOpc = AArch64ISD::TBZ;
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}
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}
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SDLoc DL(N);
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return DAG.getNode(NewOpc, DL, MVT::Other, N->getOperand(0), NewTestSrc,
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DAG.getConstant(Bit, DL, MVT::i64), N->getOperand(3));
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}
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// vselect (v1i1 setcc) ->
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// vselect (v1iXX setcc) (XX is the size of the compared operand type)
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// FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
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@ -9642,6 +9739,9 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
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return performSTORECombine(N, DCI, DAG, Subtarget);
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case AArch64ISD::BRCOND:
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return performBRCONDCombine(N, DCI, DAG);
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case AArch64ISD::TBNZ:
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case AArch64ISD::TBZ:
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return performTBZCombine(N, DCI, DAG);
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case AArch64ISD::CSEL:
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return performCONDCombine(N, DCI, DAG, 2, 3);
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case AArch64ISD::DUP:
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@ -256,3 +256,106 @@ if.then:
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if.end:
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ret void
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}
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define void @test14(i1 %cond) {
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; CHECK-LABEL: @test14
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br i1 %cond, label %if.end, label %if.then
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; CHECK-NOT: and
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; CHECK: tbnz w0, #0
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if.then:
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call void @t()
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br label %if.end
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if.end:
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ret void
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}
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define void @test15(i1 %cond) {
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; CHECK-LABEL: @test15
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%cond1 = xor i1 %cond, -1
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br i1 %cond1, label %if.then, label %if.end
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; CHECK-NOT: movn
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; CHECK: tbnz w0, #0
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if.then:
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call void @t()
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br label %if.end
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if.end:
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ret void
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}
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define void @test16(i64 %in) {
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; CHECK-LABEL: @test16
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%shl = shl i64 %in, 3
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%and = and i64 %shl, 32
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%cond = icmp eq i64 %and, 0
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br i1 %cond, label %then, label %end
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; CHECK-NOT: lsl
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; CHECK: tbnz w0, #2
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then:
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call void @t()
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br label %end
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end:
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ret void
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}
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define void @test17(i64 %in) {
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; CHECK-LABEL: @test17
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%shr = ashr i64 %in, 3
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%and = and i64 %shr, 1
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%cond = icmp eq i64 %and, 0
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br i1 %cond, label %then, label %end
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; CHECK-NOT: lsr
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; CHECK: tbnz w0, #3
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then:
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call void @t()
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br label %end
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end:
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ret void
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}
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define void @test18(i32 %in) {
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; CHECK-LABEL: @test18
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%shr = ashr i32 %in, 2
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%cond = icmp sge i32 %shr, 0
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br i1 %cond, label %then, label %end
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; CHECK-NOT: asr
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; CHECK: tbnz w0, #31
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then:
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call void @t()
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br label %end
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end:
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ret void
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}
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define void @test19(i64 %in) {
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; CHECK-LABEL: @test19
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%shl = lshr i64 %in, 3
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%trunc = trunc i64 %shl to i32
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%and = and i32 %trunc, 1
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%cond = icmp eq i32 %and, 0
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br i1 %cond, label %then, label %end
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; CHECK-NOT: ubfx
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; CHECK: tbnz w0, #3
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then:
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call void @t()
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br label %end
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end:
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ret void
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}
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