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s/ISel/PPC32ISel/ to have unique class names for debugging via gdb because the
C++ front-end in gcc does not mangle classes in anonymous namespaces correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16470 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman
parent
eae1bf10ea
commit
a1dca55a3a
@ -71,7 +71,7 @@ static inline TypeClass getClassB(const Type *Ty) {
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}
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namespace {
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struct ISel : public FunctionPass, InstVisitor<ISel> {
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struct PPC32ISel : public FunctionPass, InstVisitor<PPC32ISel> {
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PPC32TargetMachine &TM;
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MachineFunction *F; // The function we are compiling into
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MachineBasicBlock *BB; // The current MBB we are compiling
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@ -96,7 +96,7 @@ namespace {
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unsigned GlobalBaseReg;
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bool GlobalBaseInitialized;
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ISel(TargetMachine &tm) : TM(reinterpret_cast<PPC32TargetMachine&>(tm)),
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PPC32ISel(TargetMachine &tm):TM(reinterpret_cast<PPC32TargetMachine&>(tm)),
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F(0), BB(0) {}
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bool doInitialization(Module &M) {
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@ -361,9 +361,9 @@ namespace {
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/// copyGlobalBaseToRegister - Output the instructions required to put the
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/// base address to use for accessing globals into a register.
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///
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void ISel::copyGlobalBaseToRegister(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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unsigned R);
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void copyGlobalBaseToRegister(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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unsigned R);
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/// copyConstantToRegister - Output the instructions required to put the
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/// specified constant into the specified register.
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@ -436,8 +436,8 @@ static AllocaInst *dyn_castFixedAlloca(Value *V) {
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/// getReg - This method turns an LLVM value into a register number.
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///
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unsigned ISel::getReg(Value *V, MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IPt) {
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unsigned PPC32ISel::getReg(Value *V, MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IPt) {
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if (Constant *C = dyn_cast<Constant>(V)) {
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unsigned Reg = makeAnotherReg(V->getType());
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copyConstantToRegister(MBB, IPt, C, Reg);
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@ -462,7 +462,7 @@ unsigned ISel::getReg(Value *V, MachineBasicBlock *MBB,
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/// is okay to use as an immediate argument to a certain binary operator.
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///
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/// Operator is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for Xor.
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bool ISel::canUseAsImmediateForOpcode(ConstantInt *CI, unsigned Operator) {
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bool PPC32ISel::canUseAsImmediateForOpcode(ConstantInt *CI, unsigned Operator) {
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ConstantSInt *Op1Cs;
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ConstantUInt *Op1Cu;
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@ -503,7 +503,7 @@ bool ISel::canUseAsImmediateForOpcode(ConstantInt *CI, unsigned Operator) {
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/// getFixedSizedAllocaFI - Return the frame index for a fixed sized alloca
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/// that is to be statically allocated with the initial stack frame
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/// adjustment.
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unsigned ISel::getFixedSizedAllocaFI(AllocaInst *AI) {
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unsigned PPC32ISel::getFixedSizedAllocaFI(AllocaInst *AI) {
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// Already computed this?
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std::map<AllocaInst*, unsigned>::iterator I = AllocaMap.lower_bound(AI);
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if (I != AllocaMap.end() && I->first == AI) return I->second;
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@ -524,9 +524,9 @@ unsigned ISel::getFixedSizedAllocaFI(AllocaInst *AI) {
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/// copyGlobalBaseToRegister - Output the instructions required to put the
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/// base address to use for accessing globals into a register.
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///
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void ISel::copyGlobalBaseToRegister(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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unsigned R) {
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void PPC32ISel::copyGlobalBaseToRegister(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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unsigned R) {
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if (!GlobalBaseInitialized) {
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// Insert the set of GlobalBaseReg into the first MBB of the function
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MachineBasicBlock &FirstMBB = F->front();
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@ -545,9 +545,9 @@ void ISel::copyGlobalBaseToRegister(MachineBasicBlock *MBB,
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/// copyConstantToRegister - Output the instructions required to put the
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/// specified constant into the specified register.
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///
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void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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Constant *C, unsigned R) {
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void PPC32ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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Constant *C, unsigned R) {
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if (C->getType()->isIntegral()) {
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unsigned Class = getClassB(C->getType());
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@ -653,7 +653,7 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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/// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
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/// the stack into virtual registers.
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void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
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void PPC32ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
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unsigned ArgOffset = 24;
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unsigned GPR_remaining = 8;
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unsigned FPR_remaining = 13;
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@ -790,7 +790,7 @@ void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
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/// because we have to generate our sources into the source basic blocks, not
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/// the current one.
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///
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void ISel::SelectPHINodes() {
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void PPC32ISel::SelectPHINodes() {
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const TargetInstrInfo &TII = *TM.getInstrInfo();
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const Function &LF = *F->getFunction(); // The LLVM function...
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for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
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@ -955,14 +955,14 @@ static unsigned getPPCOpcodeForSetCCNumber(unsigned Opcode) {
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}
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/// emitUCOM - emits an unordered FP compare.
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void ISel::emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
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unsigned LHS, unsigned RHS) {
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void PPC32ISel::emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
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unsigned LHS, unsigned RHS) {
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BuildMI(*MBB, IP, PPC::FCMPU, 2, PPC::CR0).addReg(LHS).addReg(RHS);
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}
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unsigned ISel::ExtendOrClear(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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Value *Op0, Value *Op1) {
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unsigned PPC32ISel::ExtendOrClear(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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Value *Op0, Value *Op1) {
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const Type *CompTy = Op0->getType();
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unsigned Reg = getReg(Op0, MBB, IP);
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unsigned Class = getClassB(CompTy);
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@ -992,9 +992,9 @@ unsigned ISel::ExtendOrClear(MachineBasicBlock *MBB,
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/// EmitComparison - emits a comparison of the two operands, returning the
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/// extended setcc code to use. The result is in CR0.
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///
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unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
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MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP) {
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unsigned PPC32ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
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MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP) {
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// The arguments are already supposed to be of the same type.
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const Type *CompTy = Op0->getType();
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unsigned Class = getClassB(CompTy);
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@ -1104,7 +1104,7 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
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/// visitSetCondInst - emit code to calculate the condition via
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/// EmitComparison(), and possibly store a 0 or 1 to a register as a result
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///
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void ISel::visitSetCondInst(SetCondInst &I) {
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void PPC32ISel::visitSetCondInst(SetCondInst &I) {
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if (canFoldSetCCIntoBranchOrSelect(&I))
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return;
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@ -1153,7 +1153,7 @@ void ISel::visitSetCondInst(SetCondInst &I) {
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.addMBB(copy0MBB).addReg(TrueValue).addMBB(thisMBB);
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}
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void ISel::visitSelectInst(SelectInst &SI) {
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void PPC32ISel::visitSelectInst(SelectInst &SI) {
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unsigned DestReg = getReg(SI);
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MachineBasicBlock::iterator MII = BB->end();
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emitSelectOperation(BB, MII, SI.getCondition(), SI.getTrueValue(),
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@ -1164,10 +1164,10 @@ void ISel::visitSelectInst(SelectInst &SI) {
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/// expression support.
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/// FIXME: this is most likely broken in one or more ways. Namely, PowerPC has
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/// no select instruction. FSEL only works for comparisons against zero.
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void ISel::emitSelectOperation(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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Value *Cond, Value *TrueVal, Value *FalseVal,
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unsigned DestReg) {
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void PPC32ISel::emitSelectOperation(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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Value *Cond, Value *TrueVal,
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Value *FalseVal, unsigned DestReg) {
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unsigned SelectClass = getClassB(TrueVal->getType());
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unsigned Opcode;
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@ -1231,7 +1231,7 @@ void ISel::emitSelectOperation(MachineBasicBlock *MBB,
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/// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
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/// operand, in the specified target register.
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///
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void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
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void PPC32ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
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bool isUnsigned = VR.Ty->isUnsigned() || VR.Ty == Type::BoolTy;
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Value *Val = VR.Val;
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@ -1291,7 +1291,7 @@ void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
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/// visitReturnInst - implemented with BLR
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///
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void ISel::visitReturnInst(ReturnInst &I) {
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void PPC32ISel::visitReturnInst(ReturnInst &I) {
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// Only do the processing if this is a non-void return
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if (I.getNumOperands() > 0) {
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Value *RetVal = I.getOperand(0);
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@ -1332,7 +1332,7 @@ static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
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/// jump to a block that is the immediate successor of the current block, we can
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/// just make a fall-through (but we don't currently).
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///
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void ISel::visitBranchInst(BranchInst &BI) {
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void PPC32ISel::visitBranchInst(BranchInst &BI) {
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// Update machine-CFG edges
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BB->addSuccessor(MBBMap[BI.getSuccessor(0)]);
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if (BI.isConditional())
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@ -1397,8 +1397,8 @@ void ISel::visitBranchInst(BranchInst &BI) {
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///
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/// FIXME: See Documentation at the following URL for "correct" behavior
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/// <http://developer.apple.com/documentation/DeveloperTools/Conceptual/MachORuntime/2rt_powerpc_abi/chapter_9_section_5.html>
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void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
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const std::vector<ValueRecord> &Args, bool isVarArg) {
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void PPC32ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
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const std::vector<ValueRecord> &Args, bool isVarArg) {
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// Count how many bytes are to be pushed on the stack, including the linkage
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// area, and parameter passing area.
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unsigned NumBytes = 24;
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@ -1602,7 +1602,7 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
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/// visitCallInst - Push args on stack and do a procedure call instruction.
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void ISel::visitCallInst(CallInst &CI) {
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void PPC32ISel::visitCallInst(CallInst &CI) {
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MachineInstr *TheCall;
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Function *F = CI.getCalledFunction();
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if (F) {
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@ -1663,7 +1663,7 @@ static bool isOnlyUsedByUnorderedComparisons(Value *V) {
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/// function, lowering any calls to unknown intrinsic functions into the
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/// equivalent LLVM code.
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///
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void ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
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void PPC32ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
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for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
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for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
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if (CallInst *CI = dyn_cast<CallInst>(I++))
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@ -1712,7 +1712,7 @@ void ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
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}
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}
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void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
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void PPC32ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
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unsigned TmpReg1, TmpReg2, TmpReg3;
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switch (ID) {
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case Intrinsic::vastart:
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@ -1775,7 +1775,7 @@ void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
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/// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
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/// Xor.
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///
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void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
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void PPC32ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
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unsigned DestReg = getReg(B);
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MachineBasicBlock::iterator MI = BB->end();
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Value *Op0 = B.getOperand(0), *Op1 = B.getOperand(1);
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@ -1786,10 +1786,10 @@ void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
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/// emitBinaryFPOperation - This method handles emission of floating point
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/// Add (0), Sub (1), Mul (2), and Div (3) operations.
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void ISel::emitBinaryFPOperation(MachineBasicBlock *BB,
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MachineBasicBlock::iterator IP,
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Value *Op0, Value *Op1,
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unsigned OperatorClass, unsigned DestReg) {
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void PPC32ISel::emitBinaryFPOperation(MachineBasicBlock *BB,
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MachineBasicBlock::iterator IP,
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Value *Op0, Value *Op1,
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unsigned OperatorClass, unsigned DestReg){
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static const unsigned OpcodeTab[][4] = {
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{ PPC::FADDS, PPC::FSUBS, PPC::FMULS, PPC::FDIVS }, // Float
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@ -1818,10 +1818,11 @@ void ISel::emitBinaryFPOperation(MachineBasicBlock *BB,
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/// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
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/// and constant expression support.
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///
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void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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Value *Op0, Value *Op1,
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unsigned OperatorClass, unsigned DestReg) {
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void PPC32ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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Value *Op0, Value *Op1,
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unsigned OperatorClass,
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unsigned DestReg) {
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unsigned Class = getClassB(Op0->getType());
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// Arithmetic and Bitwise operators
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@ -1970,9 +1971,9 @@ static unsigned ExactLog2(unsigned Val) {
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/// doMultiply - Emit appropriate instructions to multiply together the
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/// Values Op0 and Op1, and put the result in DestReg.
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///
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void ISel::doMultiply(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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unsigned DestReg, Value *Op0, Value *Op1) {
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void PPC32ISel::doMultiply(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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unsigned DestReg, Value *Op0, Value *Op1) {
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unsigned Class0 = getClass(Op0->getType());
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unsigned Class1 = getClass(Op1->getType());
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@ -2025,9 +2026,9 @@ void ISel::doMultiply(MachineBasicBlock *MBB,
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/// doMultiplyConst - This method will multiply the value in Op0 by the
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/// value of the ContantInt *CI
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void ISel::doMultiplyConst(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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unsigned DestReg, Value *Op0, ConstantInt *CI) {
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void PPC32ISel::doMultiplyConst(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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unsigned DestReg, Value *Op0, ConstantInt *CI) {
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unsigned Class = getClass(Op0->getType());
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// Mul op0, 0 ==> 0
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@ -2067,7 +2068,7 @@ void ISel::doMultiplyConst(MachineBasicBlock *MBB,
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doMultiply(MBB, IP, DestReg, Op0, CI);
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}
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void ISel::visitMul(BinaryOperator &I) {
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void PPC32ISel::visitMul(BinaryOperator &I) {
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unsigned ResultReg = getReg(I);
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Value *Op0 = I.getOperand(0);
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@ -2077,8 +2078,9 @@ void ISel::visitMul(BinaryOperator &I) {
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emitMultiply(BB, IP, Op0, Op1, ResultReg);
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}
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void ISel::emitMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
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Value *Op0, Value *Op1, unsigned DestReg) {
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void PPC32ISel::emitMultiply(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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Value *Op0, Value *Op1, unsigned DestReg) {
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TypeClass Class = getClass(Op0->getType());
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switch (Class) {
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@ -2106,7 +2108,7 @@ void ISel::emitMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
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/// select the result from a different register. Note that both of these
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/// instructions work differently for signed and unsigned operands.
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///
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void ISel::visitDivRem(BinaryOperator &I) {
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void PPC32ISel::visitDivRem(BinaryOperator &I) {
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unsigned ResultReg = getReg(I);
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Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
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@ -2115,10 +2117,10 @@ void ISel::visitDivRem(BinaryOperator &I) {
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ResultReg);
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}
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void ISel::emitDivRemOperation(MachineBasicBlock *BB,
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MachineBasicBlock::iterator IP,
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Value *Op0, Value *Op1, bool isDiv,
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unsigned ResultReg) {
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void PPC32ISel::emitDivRemOperation(MachineBasicBlock *BB,
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MachineBasicBlock::iterator IP,
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Value *Op0, Value *Op1, bool isDiv,
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unsigned ResultReg) {
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const Type *Ty = Op0->getType();
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unsigned Class = getClass(Ty);
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switch (Class) {
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@ -2230,7 +2232,7 @@ void ISel::emitDivRemOperation(MachineBasicBlock *BB,
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/// shift values equal to 1. Even the general case is sort of special,
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/// because the shift amount has to be in CL, not just any old register.
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///
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void ISel::visitShiftInst(ShiftInst &I) {
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void PPC32ISel::visitShiftInst(ShiftInst &I) {
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MachineBasicBlock::iterator IP = BB->end();
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emitShiftOperation(BB, IP, I.getOperand(0), I.getOperand(1),
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I.getOpcode() == Instruction::Shl, I.getType(),
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@ -2240,10 +2242,11 @@ void ISel::visitShiftInst(ShiftInst &I) {
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/// emitShiftOperation - Common code shared between visitShiftInst and
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/// constant expression support.
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///
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void ISel::emitShiftOperation(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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Value *Op, Value *ShiftAmount, bool isLeftShift,
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const Type *ResultTy, unsigned DestReg) {
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void PPC32ISel::emitShiftOperation(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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Value *Op, Value *ShiftAmount,
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bool isLeftShift, const Type *ResultTy,
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unsigned DestReg) {
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unsigned SrcReg = getReg (Op, MBB, IP);
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bool isSigned = ResultTy->isSigned ();
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unsigned Class = getClass (ResultTy);
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@ -2439,7 +2442,7 @@ static bool LoadNeedsSignExtend(LoadInst &LI) {
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/// mapping of LLVM classes to PPC load instructions, with the exception of
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/// signed byte loads, which need a sign extension following them.
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///
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void ISel::visitLoadInst(LoadInst &I) {
|
||||
void PPC32ISel::visitLoadInst(LoadInst &I) {
|
||||
// Immediate opcodes, for reg+imm addressing
|
||||
static const unsigned ImmOpcodes[] = {
|
||||
PPC::LBZ, PPC::LHZ, PPC::LWZ,
|
||||
@ -2538,7 +2541,7 @@ void ISel::visitLoadInst(LoadInst &I) {
|
||||
|
||||
/// visitStoreInst - Implement LLVM store instructions
|
||||
///
|
||||
void ISel::visitStoreInst(StoreInst &I) {
|
||||
void PPC32ISel::visitStoreInst(StoreInst &I) {
|
||||
// Immediate opcodes, for reg+imm addressing
|
||||
static const unsigned ImmOpcodes[] = {
|
||||
PPC::STB, PPC::STH, PPC::STW,
|
||||
@ -2607,7 +2610,7 @@ void ISel::visitStoreInst(StoreInst &I) {
|
||||
/// visitCastInst - Here we have various kinds of copying with or without sign
|
||||
/// extension going on.
|
||||
///
|
||||
void ISel::visitCastInst(CastInst &CI) {
|
||||
void PPC32ISel::visitCastInst(CastInst &CI) {
|
||||
Value *Op = CI.getOperand(0);
|
||||
|
||||
unsigned SrcClass = getClassB(Op->getType());
|
||||
@ -2654,10 +2657,10 @@ void ISel::visitCastInst(CastInst &CI) {
|
||||
/// emitCastOperation - Common code shared between visitCastInst and constant
|
||||
/// expression cast support.
|
||||
///
|
||||
void ISel::emitCastOperation(MachineBasicBlock *MBB,
|
||||
MachineBasicBlock::iterator IP,
|
||||
Value *Src, const Type *DestTy,
|
||||
unsigned DestReg) {
|
||||
void PPC32ISel::emitCastOperation(MachineBasicBlock *MBB,
|
||||
MachineBasicBlock::iterator IP,
|
||||
Value *Src, const Type *DestTy,
|
||||
unsigned DestReg) {
|
||||
const Type *SrcTy = Src->getType();
|
||||
unsigned SrcClass = getClassB(SrcTy);
|
||||
unsigned DestClass = getClassB(DestTy);
|
||||
@ -3136,7 +3139,7 @@ void ISel::emitCastOperation(MachineBasicBlock *MBB,
|
||||
|
||||
/// visitVANextInst - Implement the va_next instruction...
|
||||
///
|
||||
void ISel::visitVANextInst(VANextInst &I) {
|
||||
void PPC32ISel::visitVANextInst(VANextInst &I) {
|
||||
unsigned VAList = getReg(I.getOperand(0));
|
||||
unsigned DestReg = getReg(I);
|
||||
|
||||
@ -3162,7 +3165,7 @@ void ISel::visitVANextInst(VANextInst &I) {
|
||||
BuildMI(BB, PPC::ADDI, 2, DestReg).addReg(VAList).addSImm(Size);
|
||||
}
|
||||
|
||||
void ISel::visitVAArgInst(VAArgInst &I) {
|
||||
void PPC32ISel::visitVAArgInst(VAArgInst &I) {
|
||||
unsigned VAList = getReg(I.getOperand(0));
|
||||
unsigned DestReg = getReg(I);
|
||||
|
||||
@ -3192,7 +3195,7 @@ void ISel::visitVAArgInst(VAArgInst &I) {
|
||||
|
||||
/// visitGetElementPtrInst - instruction-select GEP instructions
|
||||
///
|
||||
void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
|
||||
void PPC32ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
|
||||
if (canFoldGEPIntoLoadOrStore(&I))
|
||||
return;
|
||||
|
||||
@ -3204,12 +3207,12 @@ void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
|
||||
/// emitGEPOperation - Common code shared between visitGetElementPtrInst and
|
||||
/// constant expression GEP support.
|
||||
///
|
||||
void ISel::emitGEPOperation(MachineBasicBlock *MBB,
|
||||
MachineBasicBlock::iterator IP,
|
||||
Value *Src, User::op_iterator IdxBegin,
|
||||
User::op_iterator IdxEnd, unsigned TargetReg,
|
||||
bool GEPIsFolded, ConstantSInt **RemainderPtr,
|
||||
unsigned *PendingAddReg) {
|
||||
void PPC32ISel::emitGEPOperation(MachineBasicBlock *MBB,
|
||||
MachineBasicBlock::iterator IP,
|
||||
Value *Src, User::op_iterator IdxBegin,
|
||||
User::op_iterator IdxEnd, unsigned TargetReg,
|
||||
bool GEPIsFolded, ConstantSInt **RemainderPtr,
|
||||
unsigned *PendingAddReg) {
|
||||
const TargetData &TD = TM.getTargetData();
|
||||
const Type *Ty = Src->getType();
|
||||
unsigned basePtrReg = getReg(Src, MBB, IP);
|
||||
@ -3375,7 +3378,7 @@ void ISel::emitGEPOperation(MachineBasicBlock *MBB,
|
||||
/// visitAllocaInst - If this is a fixed size alloca, allocate space from the
|
||||
/// frame manager, otherwise do it the hard way.
|
||||
///
|
||||
void ISel::visitAllocaInst(AllocaInst &I) {
|
||||
void PPC32ISel::visitAllocaInst(AllocaInst &I) {
|
||||
// If this is a fixed size alloca in the entry block for the function, we
|
||||
// statically stack allocate the space, so we don't need to do anything here.
|
||||
//
|
||||
@ -3418,7 +3421,7 @@ void ISel::visitAllocaInst(AllocaInst &I) {
|
||||
/// visitMallocInst - Malloc instructions are code generated into direct calls
|
||||
/// to the library malloc.
|
||||
///
|
||||
void ISel::visitMallocInst(MallocInst &I) {
|
||||
void PPC32ISel::visitMallocInst(MallocInst &I) {
|
||||
unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
|
||||
unsigned Arg;
|
||||
|
||||
@ -3443,7 +3446,7 @@ void ISel::visitMallocInst(MallocInst &I) {
|
||||
/// visitFreeInst - Free instructions are code gen'd to call the free libc
|
||||
/// function.
|
||||
///
|
||||
void ISel::visitFreeInst(FreeInst &I) {
|
||||
void PPC32ISel::visitFreeInst(FreeInst &I) {
|
||||
std::vector<ValueRecord> Args;
|
||||
Args.push_back(ValueRecord(I.getOperand(0)));
|
||||
MachineInstr *TheCall =
|
||||
@ -3456,5 +3459,5 @@ void ISel::visitFreeInst(FreeInst &I) {
|
||||
/// code representation is a very simple peep-hole fashion.
|
||||
///
|
||||
FunctionPass *llvm::createPPC32ISelSimple(TargetMachine &TM) {
|
||||
return new ISel(TM);
|
||||
return new PPC32ISel(TM);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user