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Use PairDRegs to implement ConcatVectors. No functionality change.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122017 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2010-12-17 01:21:08 +00:00
parent c7c5e781a3
commit a1f544b62e
1 changed files with 1 additions and 7 deletions
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8
lib/Target/ARM/ARMISelDAGToDAG.cpp
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@ -2141,13 +2141,7 @@ SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
EVT VT = N->getValueType(0);
if (!VT.is128BitVector() || N->getNumOperands() != 2)
llvm_unreachable("unexpected CONCAT_VECTORS");
DebugLoc dl = N->getDebugLoc();
SDValue V0 = N->getOperand(0);
SDValue V1 = N->getOperand(1);
SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
return PairDRegs(VT, N->getOperand(0), N->getOperand(1));
}
SDNode *ARMDAGToDAGISel::Select(SDNode *N) {