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Constant generation instructions are re-materializable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35161 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -137,7 +137,7 @@ def so_imm_neg :
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PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(-(int)N->getValue()) != -1; }],
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so_imm_neg_XFORM>;
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def so_imm_not :
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def so_imm_not :
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PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(~(int)N->getValue()) != -1; }],
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so_imm_not_XFORM>;
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@ -709,6 +709,8 @@ def MOVrr : AI1<(ops GPR:$dst, GPR:$src),
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"mov $dst, $src", []>;
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def MOVrs : AI1<(ops GPR:$dst, so_reg:$src),
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"mov $dst, $src", [(set GPR:$dst, so_reg:$src)]>;
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let isReMaterializable = 1 in
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def MOVri : AI1<(ops GPR:$dst, so_imm:$src),
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"mov $dst, $src", [(set GPR:$dst, so_imm:$src)]>;
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@ -806,10 +808,13 @@ defm ORR : AI1_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>>;
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defm EOR : AI1_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
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defm BIC : AI1_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
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defm MVN : AI1_unary_irs<"mvn", not>;
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def : ARMPat<(i32 so_imm_not:$imm),
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(MVNi so_imm_not:$imm)>;
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def MVNr : AI<(ops GPR:$dst, GPR:$src),
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"mvn $dst, $src", [(set GPR:$dst, (not GPR:$src))]>;
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def MVNs : AI<(ops GPR:$dst, so_reg:$src),
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"mvn $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>;
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let isReMaterializable = 1 in
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def MVNi : AI<(ops GPR:$dst, so_imm:$imm),
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"mvn $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>;
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def : ARMPat<(and GPR:$src, so_imm_not:$imm),
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(BICri GPR:$src, so_imm_not:$imm)>;
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@ -374,6 +374,7 @@ def tLSRrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
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"lsr $dst, $rhs",
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[(set GPR:$dst, (srl GPR:$lhs, GPR:$rhs))]>;
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let isReMaterializable = 1 in
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def tMOVri8 : TI<(ops GPR:$dst, i32imm:$src),
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"mov $dst, $src",
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[(set GPR:$dst, imm0_255:$src)]>;
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