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https://github.com/RPCS3/llvm.git
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Still need to support -mcpu=<> or cross compilation will fail. Doh.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30764 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
abc346ceda
commit
a26eb5e1a7
@ -14,6 +14,7 @@ EXTRA_DIST = README.txt
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BUILT_SOURCES = X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
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X86GenRegisterInfo.inc X86GenInstrNames.inc \
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X86GenInstrInfo.inc X86GenAsmWriter.inc \
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X86GenAsmWriter1.inc X86GenDAGISel.inc
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X86GenAsmWriter1.inc X86GenDAGISel.inc \
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X86GenSubtarget.inc
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include $(LEVEL)/Makefile.common
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@ -16,6 +16,79 @@
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//
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include "../Target.td"
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//===----------------------------------------------------------------------===//
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// X86 Subtarget features.
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//
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def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
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"Support 64-bit instructions">;
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def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
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"Enable MMX instructions">;
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def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
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"Enable SSE instructions">;
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def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
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"Enable SSE2 instructions">;
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def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
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"Enable SSE3 instructions">;
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def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
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"Enable 3DNow! instructions">;
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def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
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"Enable 3DNow! Athlon instructions">;
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//===----------------------------------------------------------------------===//
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// X86 processors supported.
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//===----------------------------------------------------------------------===//
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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def : Proc<"generic", []>;
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def : Proc<"i386", []>;
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def : Proc<"i486", []>;
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def : Proc<"pentium", []>;
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def : Proc<"pentium-mmx", [FeatureMMX]>;
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def : Proc<"i686", []>;
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def : Proc<"pentiumpro", []>;
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def : Proc<"pentium2", [FeatureMMX]>;
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def : Proc<"pentium3", [FeatureMMX, FeatureSSE1]>;
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def : Proc<"pentium-m", [FeatureMMX, FeatureSSE1, FeatureSSE2]>;
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def : Proc<"pentium4", [FeatureMMX, FeatureSSE1, FeatureSSE2]>;
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def : Proc<"x86-64", [FeatureMMX, FeatureSSE1, FeatureSSE2,
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Feature64Bit]>;
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def : Proc<"yonah", [FeatureMMX, FeatureSSE1, FeatureSSE2,
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FeatureSSE3]>;
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def : Proc<"prescott", [FeatureMMX, FeatureSSE1, FeatureSSE2,
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FeatureSSE3]>;
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def : Proc<"nocona", [FeatureMMX, FeatureSSE1, FeatureSSE2,
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FeatureSSE3, Feature64Bit]>;
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def : Proc<"core2", [FeatureMMX, FeatureSSE1, FeatureSSE2,
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FeatureSSE3, Feature64Bit]>;
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def : Proc<"k6", [FeatureMMX]>;
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def : Proc<"k6-2", [FeatureMMX, Feature3DNow]>;
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def : Proc<"k6-3", [FeatureMMX, Feature3DNow]>;
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def : Proc<"athlon", [FeatureMMX, Feature3DNow, Feature3DNowA]>;
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def : Proc<"athlon-tbird", [FeatureMMX, Feature3DNow, Feature3DNowA]>;
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def : Proc<"athlon-4", [FeatureMMX, FeatureSSE1, Feature3DNow,
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Feature3DNowA]>;
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def : Proc<"athlon-xp", [FeatureMMX, FeatureSSE1, Feature3DNow,
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Feature3DNowA]>;
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def : Proc<"athlon-mp", [FeatureMMX, FeatureSSE1, Feature3DNow,
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Feature3DNowA]>;
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def : Proc<"k8", [FeatureMMX, FeatureSSE1, FeatureSSE2,
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Feature3DNow, Feature3DNowA, Feature64Bit]>;
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def : Proc<"opteron", [FeatureMMX, FeatureSSE1, FeatureSSE2,
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Feature3DNow, Feature3DNowA, Feature64Bit]>;
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def : Proc<"athlon64", [FeatureMMX, FeatureSSE1, FeatureSSE2,
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Feature3DNow, Feature3DNowA, Feature64Bit]>;
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def : Proc<"athlon-fx", [FeatureMMX, FeatureSSE1, FeatureSSE2,
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Feature3DNow, Feature3DNowA, Feature64Bit]>;
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def : Proc<"winchip-c6", [FeatureMMX]>;
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def : Proc<"winchip2", [FeatureMMX, Feature3DNow]>;
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def : Proc<"c3", [FeatureMMX, Feature3DNow]>;
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def : Proc<"c3-2", [FeatureMMX, FeatureSSE1]>;
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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@ -12,7 +12,7 @@
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//===----------------------------------------------------------------------===//
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#include "X86Subtarget.h"
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//#include "X86GenSubtarget.inc"
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#include "X86GenSubtarget.inc"
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#include "llvm/Module.h"
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#include "llvm/Support/CommandLine.h"
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#include <iostream>
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@ -72,7 +72,7 @@ static inline bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEB
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return true;
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}
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void X86Subtarget::DetectSubtargetFeatures() {
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void X86Subtarget::AutoDetectSubtargetFeatures() {
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unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
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union {
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unsigned u[3];
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@ -96,6 +96,100 @@ void X86Subtarget::DetectSubtargetFeatures() {
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}
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}
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static const char *GetCurrentX86CPU() {
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unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
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if (GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
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return "generic";
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unsigned Family = (EAX >> 8) & 0xf; // Bits 8 - 11
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unsigned Model = (EAX >> 4) & 0xf; // Bits 4 - 7
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GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
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bool Em64T = EDX & (1 << 29);
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union {
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unsigned u[3];
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char c[12];
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} text;
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GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
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if (memcmp(text.c, "GenuineIntel", 12) == 0) {
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switch (Family) {
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case 3:
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return "i386";
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case 4:
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return "i486";
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case 5:
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switch (Model) {
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case 4: return "pentium-mmx";
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default: return "pentium";
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}
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case 6:
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switch (Model) {
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case 1: return "pentiumpro";
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case 3:
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case 5:
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case 6: return "pentium2";
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case 7:
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case 8:
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case 10:
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case 11: return "pentium3";
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case 9:
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case 13: return "pentium-m";
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case 14: return "yonah";
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case 15: return "core2";
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default: return "i686";
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}
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case 15: {
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switch (Model) {
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case 3:
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case 4:
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return (Em64T) ? "nocona" : "prescott";
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default:
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return (Em64T) ? "x86-64" : "pentium4";
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}
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}
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default:
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return "generic";
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}
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} else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
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// FIXME: this poorly matches the generated SubtargetFeatureKV table. There
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// appears to be no way to generate the wide variety of AMD-specific targets
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// from the information returned from CPUID.
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switch (Family) {
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case 4:
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return "i486";
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case 5:
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switch (Model) {
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case 6:
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case 7: return "k6";
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case 8: return "k6-2";
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case 9:
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case 13: return "k6-3";
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default: return "pentium";
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}
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case 6:
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switch (Model) {
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case 4: return "athlon-tbird";
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case 6:
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case 7:
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case 8: return "athlon-mp";
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case 10: return "athlon-xp";
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default: return "athlon";
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}
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case 15:
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switch (Model) {
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case 5: return "athlon-fx"; // also opteron
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default: return "athlon64";
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}
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default:
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return "generic";
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}
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} else {
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return "generic";
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}
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}
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X86Subtarget::X86Subtarget(const Module &M, const std::string &FS, bool is64Bit)
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: AsmFlavor(AsmWriterFlavor)
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, X86SSELevel(NoMMXSSE)
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@ -107,7 +201,14 @@ X86Subtarget::X86Subtarget(const Module &M, const std::string &FS, bool is64Bit)
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, TargetType(isELF) { // Default to ELF unless otherwise specified.
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// Determine default and user specified characteristics
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DetectSubtargetFeatures();
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if (!FS.empty()) {
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// If feature string is not empty, parse features string.
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std::string CPU = GetCurrentX86CPU();
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ParseSubtargetFeatures(FS, CPU);
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} else
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// Otherwise, use CPUID to auto-detect feature set.
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AutoDetectSubtargetFeatures();
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if (Is64Bit && !HasX86_64) {
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std::cerr << "Warning: Generation of 64-bit code for a 32-bit processor "
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"requested.\n";
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@ -32,12 +32,19 @@ protected:
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NoMMXSSE, MMX, SSE1, SSE2, SSE3
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};
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enum X863DNowEnum {
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NoThreeDNow, ThreeDNow, ThreeDNowA
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};
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/// AsmFlavor - Which x86 asm dialect to use.
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AsmWriterFlavorTy AsmFlavor;
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/// X86SSELevel - MMX, SSE1, SSE2, SSE3, or none supported.
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X86SSEEnum X86SSELevel;
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/// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
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X863DNowEnum X863DNowLevel;
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/// HasX86_64 - True if the processor supports X86-64 instructions.
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bool HasX86_64;
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@ -74,9 +81,13 @@ public:
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/// aligned.
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unsigned getMinRepStrSizeThreshold() const { return MinRepStrSizeThreshold; }
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/// DetectSubtargetFeatures - Auto-detect CPU features using CPUID instruction.
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///
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void DetectSubtargetFeatures();
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/// ParseSubtargetFeatures - Parses features string setting specified
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/// subtarget options. Definition of function is auto generated by tblgen.
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void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
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/// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID
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/// instruction.
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void AutoDetectSubtargetFeatures();
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bool is64Bit() const { return Is64Bit; }
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@ -84,6 +95,8 @@ public:
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bool hasSSE1() const { return X86SSELevel >= SSE1; }
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bool hasSSE2() const { return X86SSELevel >= SSE2; }
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bool hasSSE3() const { return X86SSELevel >= SSE3; }
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bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
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bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
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bool isFlavorAtt() const { return AsmFlavor == att; }
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bool isFlavorIntel() const { return AsmFlavor == intel; }
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