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Followup to r106770: actually generate SXTB and SXTH for sign-extensions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106940 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman 2010-06-26 04:36:50 +00:00
parent ccd9bcca14
commit a2c6f457a4
1 changed files with 2 additions and 5 deletions
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7
lib/Target/ARM/ARMISelLowering.cpp
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@ -459,11 +459,8 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand); setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand); setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
// If the subtarget does not have extract instructions, sign_extend_inreg // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
// needs to be expanded. Extract is available in ARM mode on v6 and up, if (!Subtarget->hasV6Ops()) {
// and on most Thumb2 implementations.
if (!Subtarget->hasV6Ops()
|| (Subtarget->isThumb2() && !Subtarget->hasT2ExtractPack())) {
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
} }