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Prefer LMUL to MACCU as LMUL has no tied operands.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98153 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne 2010-03-10 13:27:10 +00:00
parent a7e78402b8
commit a2cc0613d0
4 changed files with 14 additions and 7 deletions
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6
lib/Target/XCore/XCoreISelDAGToDAG.cpp
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@ -220,6 +220,12 @@ SDNode *XCoreDAGToDAGISel::Select(SDNode *N) {
return CurDAG->getMachineNode(XCore::MACCS_l4r, dl, MVT::i32, MVT::i32,
Ops, 4);
}
case XCoreISD::LMUL: {
SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
N->getOperand(2), N->getOperand(3) };
return CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32, MVT::i32,
Ops, 4);
}
// Other cases are autogenerated.
}
}

7
lib/Target/XCore/XCoreISelLowering.cpp
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@ -54,6 +54,7 @@ getTargetNodeName(unsigned Opcode) const
case XCoreISD::RETSP : return "XCoreISD::RETSP";
case XCoreISD::LADD : return "XCoreISD::LADD";
case XCoreISD::LSUB : return "XCoreISD::LSUB";
case XCoreISD::LMUL : return "XCoreISD::LMUL";
case XCoreISD::MACCU : return "XCoreISD::MACCU";
case XCoreISD::MACCS : return "XCoreISD::MACCS";
case XCoreISD::BR_JT : return "XCoreISD::BR_JT";
@ -573,9 +574,9 @@ LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG)
SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1);
SDValue Zero = DAG.getConstant(0, MVT::i32);
SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero,
LHS, RHS);
SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
DAG.getVTList(MVT::i32, MVT::i32), LHS, RHS,
Zero, Zero);
SDValue Lo(Hi.getNode(), 1);
SDValue Ops[] = { Lo, Hi };
return DAG.getMergeValues(Ops, 2, dl);

3
lib/Target/XCore/XCoreISelLowering.h
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@ -54,6 +54,9 @@ namespace llvm {
// Corresponds to LSUB instruction
LSUB,
// Corresponds to LMUL instruction
LMUL,
// Corresponds to MACCU instruction
MACCU,

5
test/CodeGen/XCore/mul64.ll
View File

@ -8,10 +8,7 @@ entry:
}
; CHECK: umul_lohi:
; CHECK: ldc r2, 0
; CHECK-NEXT: mov r3, r2
; CHECK-NEXT: maccu r2, r3, r1, r0
; CHECK-NEXT: mov r0, r3
; CHECK-NEXT: mov r1, r2
; CHECK-NEXT: lmul r1, r0, r1, r0, r2, r2
; CHECK-NEXT: retsp 0
define i64 @smul_lohi(i32 %a, i32 %b) {