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Add assertions to the trivial scheduler to check that the value types match

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up between defs and uses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23590 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-10-02 07:10:55 +00:00
parent 43f07a4bbc
commit a3638c0f1f
1 changed files with 21 additions and 0 deletions
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21
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
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@ -1102,6 +1102,20 @@ unsigned SimpleSched::EmitDAG(SDOperand Op) {
unsigned VReg = EmitDAG(Op.getOperand(i));
MI->addRegOperand(VReg, MachineOperand::Use);
// Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
assert(II.OpInfo[i+NumResults].RegClass &&
"Don't have operand info for this instruction!");
#ifndef NDEBUG
if (RegMap->getRegClass(VReg) != II.OpInfo[i+NumResults].RegClass) {
std::cerr << "OP: ";
Op.getOperand(i).Val->dump(&DAG); std::cerr << "\nUSE: ";
Op.Val->dump(&DAG); std::cerr << "\n";
}
#endif
assert(RegMap->getRegClass(VReg) == II.OpInfo[i+NumResults].RegClass &&
"Register class of operand and regclass of use don't agree!");
} else if (ConstantSDNode *C =
dyn_cast<ConstantSDNode>(Op.getOperand(i))) {
MI->addZeroExtImm64Operand(C->getValue());
@ -1129,6 +1143,13 @@ unsigned SimpleSched::EmitDAG(SDOperand Op) {
"Chain and flag operands should occur at end of operand list!");
unsigned VReg = EmitDAG(Op.getOperand(i));
MI->addRegOperand(VReg, MachineOperand::Use);
// Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
assert(II.OpInfo[i+NumResults].RegClass &&
"Don't have operand info for this instruction!");
assert(RegMap->getRegClass(VReg) == II.OpInfo[i+NumResults].RegClass &&
"Register class of operand and regclass of use don't agree!");
}
}