From a3837424391e08fe88bf5d65ea265464d11c1528 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Fri, 17 Oct 2014 00:36:20 +0000
Subject: [PATCH] R600/SI: Simplify debug printing

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219999 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/R600/SIFixSGPRCopies.cpp | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/lib/Target/R600/SIFixSGPRCopies.cpp b/lib/Target/R600/SIFixSGPRCopies.cpp
index 349744c5b56..086b44433c2 100644
--- a/lib/Target/R600/SIFixSGPRCopies.cpp
+++ b/lib/Target/R600/SIFixSGPRCopies.cpp
@@ -243,7 +243,7 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
         // we must move it to the VALU, because the SGPR operands will
         // all end up being assigned the same register, which means
         // there is a potential for a conflict if different threads take
-	// different control flow paths.
+        // different control flow paths.
         //
         // For Example:
         //
@@ -305,8 +305,7 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
             !hasVGPROperands(MI, TRI))
           continue;
 
-        DEBUG(dbgs() << "Fixing REG_SEQUENCE:\n");
-        DEBUG(MI.print(dbgs()));
+        DEBUG(dbgs() << "Fixing REG_SEQUENCE: " << MI);
 
         TII->moveToVALU(MI);
         break;
@@ -318,8 +317,7 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
         Src1RC = MRI.getRegClass(MI.getOperand(2).getReg());
         if (TRI->isSGPRClass(DstRC) &&
             (TRI->hasVGPRs(Src0RC) || TRI->hasVGPRs(Src1RC))) {
-          DEBUG(dbgs() << " Fixing INSERT_SUBREG:\n");
-          DEBUG(MI.print(dbgs()));
+          DEBUG(dbgs() << " Fixing INSERT_SUBREG: " << MI);
           TII->moveToVALU(MI);
         }
         break;