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[mips] Split Instruction.Predicates into smaller lists and re-join them with !listconcat
Summary: The overall idea is to chop the Predicates list into subsets that are usually overridden independently. This allows subclasses to partially override the predicates of their superclasses without having to re-add all the existing predicates. This patch starts the process by moving HasStdEnc into a new EncodingPredicates list and almost everything else into AdditionalPredicates. It has revealed a couple likely bugs where 'let Predicates' has removed the HasStdEnc predicate. No functional change (confirmed by diffing tablegen-erated files). Depends on D3549, D3506 Reviewers: vmedic Differential Revision: http://reviews.llvm.org/D3550 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208184 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
parent
d80222a48b
commit
a3953a30b6
@ -95,7 +95,7 @@ def FNEG_MM : MMRel, ABSS_FT<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>,
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ABS_FM_MM<1, 0x2d>;
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def FMOV_D32_MM : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,
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ABS_FM_MM<1, 0x1>, Requires<[HasStdEnc, NotFP64bit]>;
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ABS_FM_MM<1, 0x1>, AdditionalRequires<[NotFP64bit]>;
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def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd,
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II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>;
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@ -15,6 +15,24 @@
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include "llvm/Target/Target.td"
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// The overall idea of the PredicateControl class is to chop the Predicates list
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// into subsets that are usually overridden independently. This allows
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// subclasses to partially override the predicates of their superclasses without
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// having to re-add all the existing predicates.
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class PredicateControl {
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// Predicates for the encoding scheme in use such as HasStdEnc
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list<Predicate> EncodingPredicates = [];
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// Predicates for anything else
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list<Predicate> AdditionalPredicates = [];
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list<Predicate> Predicates = !listconcat(EncodingPredicates,
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AdditionalPredicates);
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}
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// Like Requires<> but for the AdditionalPredicates list
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class AdditionalRequires<list<Predicate> preds> {
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list<Predicate> AdditionalPredicates = preds;
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}
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//===----------------------------------------------------------------------===//
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// Register File, Calling Conv, Instruction Descriptions
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//===----------------------------------------------------------------------===//
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@ -118,7 +118,7 @@ def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
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SRA_FM<0x3f, 0>;
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// Rotate Instructions
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let Predicates = [HasStdEnc, HasMips64r2] in {
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let AdditionalPredicates = [HasMips64r2] in {
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def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
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immZExt6>, SRA_FM<0x3a, 1>;
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def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>,
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@ -252,7 +252,8 @@ def LONG_BRANCH_DADDiu : PseudoSE<(outs GPR64Opnd:$dst),
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(ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
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// Cavium Octeon cmMIPS instructions
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let Predicates = [HasCnMips] in {
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let EncodingPredicates = []<Predicate>, // FIXME: The lack of HasStdEnc is probably a bug
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AdditionalPredicates = [HasCnMips] in {
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class Count1s<string opstr, RegisterOperand RO>:
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InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
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@ -401,8 +402,7 @@ defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>;
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// truncate
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def : MipsPat<(i32 (trunc GPR64:$src)),
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(SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>,
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Requires<[HasStdEnc]>;
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(SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>;
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// 32-to-64-bit extension
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def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
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@ -132,23 +132,23 @@ def MOVZ_I_S : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, II_MOVZ_S>,
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let isCodeGenOnly = 1 in
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def MOVZ_I64_S : CMov_I_F_FT<"movz.s", GPR64Opnd, FGR32Opnd, II_MOVZ_S>,
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CMov_I_F_FM<18, 16>, Requires<[HasStdEnc, HasMips64]>;
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CMov_I_F_FM<18, 16>, AdditionalRequires<[HasMips64]>;
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def MOVN_I_S : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, II_MOVN_S>,
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CMov_I_F_FM<19, 16>;
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let isCodeGenOnly = 1 in
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def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, II_MOVN_S>,
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CMov_I_F_FM<19, 16>, Requires<[HasStdEnc, IsGP64bit]>;
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CMov_I_F_FM<19, 16>, AdditionalRequires<[IsGP64bit]>;
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let Predicates = [HasStdEnc, NotFP64bit] in {
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let AdditionalPredicates = [NotFP64bit] in {
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def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
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II_MOVZ_D>, CMov_I_F_FM<18, 17>;
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def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
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II_MOVN_D>, CMov_I_F_FM<19, 17>;
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}
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let Predicates = [HasStdEnc, IsFP64bit], DecoderNamespace = "Mips64" in {
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let AdditionalPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
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def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, II_MOVZ_D>,
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CMov_I_F_FM<18, 17>;
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def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, II_MOVN_D>,
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@ -166,28 +166,28 @@ def MOVT_I : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT, MipsCMovFP_T>,
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let isCodeGenOnly = 1 in
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def MOVT_I64 : CMov_F_I_FT<"movt", GPR64Opnd, II_MOVT, MipsCMovFP_T>,
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CMov_F_I_FM<1>, Requires<[HasStdEnc, IsGP64bit]>;
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CMov_F_I_FM<1>, AdditionalRequires<[IsGP64bit]>;
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def MOVF_I : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>,
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CMov_F_I_FM<0>;
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let isCodeGenOnly = 1 in
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def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, II_MOVF, MipsCMovFP_F>,
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CMov_F_I_FM<0>, Requires<[HasStdEnc, IsGP64bit]>;
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CMov_F_I_FM<0>, AdditionalRequires<[IsGP64bit]>;
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def MOVT_S : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, MipsCMovFP_T>,
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CMov_F_F_FM<16, 1>;
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def MOVF_S : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, MipsCMovFP_F>,
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CMov_F_F_FM<16, 0>;
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let Predicates = [HasStdEnc, NotFP64bit] in {
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let AdditionalPredicates = [NotFP64bit] in {
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def MOVT_D32 : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D,
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MipsCMovFP_T>, CMov_F_F_FM<17, 1>;
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def MOVF_D32 : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,
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MipsCMovFP_F>, CMov_F_F_FM<17, 0>;
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}
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let Predicates = [HasStdEnc, IsFP64bit], DecoderNamespace = "Mips64" in {
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let AdditionalPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
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def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, II_MOVT_D, MipsCMovFP_T>,
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CMov_F_F_FM<17, 1>;
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def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, II_MOVF_D, MipsCMovFP_F>,
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@ -198,7 +198,7 @@ let Predicates = [HasStdEnc, IsFP64bit], DecoderNamespace = "Mips64" in {
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defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR>;
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defm : MovzPats2<GPR32, GPR32, MOVZ_I_I, XORi>;
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let Predicates = [HasStdEnc, IsGP64bit] in {
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let AdditionalPredicates = [IsGP64bit] in {
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defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats0<GPR64, GPR32, MOVZ_I_I, SLT64, SLTu64, SLTi64,
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SLTiu64>;
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@ -213,7 +213,7 @@ let Predicates = [HasStdEnc, IsGP64bit] in {
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}
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defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>;
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let Predicates = [HasStdEnc, IsGP64bit] in {
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let AdditionalPredicates = [IsGP64bit] in {
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defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>;
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defm : MovnPats<GPR64, GPR32, MOVN_I64_I, XOR64>;
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defm : MovnPats<GPR64, GPR64, MOVN_I64_I64, XOR64>;
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@ -222,19 +222,19 @@ let Predicates = [HasStdEnc, IsGP64bit] in {
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defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats1<GPR32, FGR32, MOVZ_I_S, XOR>;
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defm : MovnPats<GPR32, FGR32, MOVN_I_S, XOR>;
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let Predicates = [HasStdEnc, IsGP64bit] in {
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let AdditionalPredicates = [IsGP64bit] in {
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defm : MovzPats0<GPR64, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64,
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SLTiu64>;
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defm : MovzPats1<GPR64, FGR32, MOVZ_I64_S, XOR64>;
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defm : MovnPats<GPR64, FGR32, MOVN_I64_S, XOR64>;
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}
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let Predicates = [HasStdEnc, NotFP64bit] in {
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let AdditionalPredicates = [NotFP64bit] in {
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defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32, XOR>;
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defm : MovnPats<GPR32, AFGR64, MOVN_I_D32, XOR>;
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}
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let Predicates = [HasStdEnc, IsFP64bit] in {
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let AdditionalPredicates = [IsFP64bit] in {
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defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats0<GPR64, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64,
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SLTiu64>;
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@ -100,10 +100,10 @@ class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm,
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multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
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SDPatternOperator OpNode = null_frag> {
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def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>,
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Requires<[HasStdEnc, NotFP64bit]>;
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AdditionalRequires<[NotFP64bit]>;
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def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin,
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IsComm, OpNode>,
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Requires<[HasStdEnc, IsFP64bit]> {
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AdditionalRequires<[IsFP64bit]> {
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string DecoderNamespace = "Mips64";
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}
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}
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@ -117,18 +117,18 @@ class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
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multiclass ABSS_M<string opstr, InstrItinClass Itin,
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SDPatternOperator OpNode= null_frag> {
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def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
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Requires<[HasStdEnc, NotFP64bit]>;
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AdditionalRequires<[NotFP64bit]>;
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def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
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Requires<[HasStdEnc, IsFP64bit]> {
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AdditionalRequires<[IsFP64bit]> {
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string DecoderNamespace = "Mips64";
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}
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}
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multiclass ROUND_M<string opstr, InstrItinClass Itin> {
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def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>,
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Requires<[HasStdEnc, NotFP64bit]>;
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AdditionalRequires<[NotFP64bit]>;
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def _D64 : ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>,
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Requires<[HasStdEnc, IsFP64bit]> {
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AdditionalRequires<[IsFP64bit]> {
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let DecoderNamespace = "Mips64";
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}
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}
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@ -241,10 +241,10 @@ multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt,
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defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>;
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defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>,
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Requires<[HasStdEnc, NotFP64bit]>;
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AdditionalRequires<[NotFP64bit]>;
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let DecoderNamespace = "Mips64" in
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defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>,
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Requires<[HasStdEnc, IsFP64bit]>;
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AdditionalRequires<[IsFP64bit]>;
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//===----------------------------------------------------------------------===//
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// Floating Point Instructions
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@ -266,7 +266,7 @@ defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>;
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defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>;
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defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>;
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let Predicates = [HasStdEnc, IsFP64bit], DecoderNamespace = "Mips64" in {
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let AdditionalPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
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def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>,
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ABSS_FM<0x8, 16>;
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def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>,
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@ -292,7 +292,7 @@ def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
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def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
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ABSS_FM<0x25, 17>;
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let Predicates = [HasStdEnc, NotFP64bit] in {
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let AdditionalPredicates = [NotFP64bit] in {
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def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
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ABSS_FM<0x20, 17>;
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def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
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@ -301,7 +301,7 @@ let Predicates = [HasStdEnc, NotFP64bit] in {
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ABSS_FM<0x21, 16>;
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}
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let Predicates = [HasStdEnc, IsFP64bit], DecoderNamespace = "Mips64" in {
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let AdditionalPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
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def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,
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ABSS_FM<0x20, 17>;
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def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>,
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@ -357,9 +357,9 @@ def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1,
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def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
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ABSS_FM<0x6, 16>;
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def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,
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ABSS_FM<0x6, 17>, Requires<[HasStdEnc, NotFP64bit]>;
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ABSS_FM<0x6, 17>, AdditionalRequires<[NotFP64bit]>;
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def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>,
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ABSS_FM<0x6, 17>, Requires<[HasStdEnc, IsFP64bit]> {
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ABSS_FM<0x6, 17>, AdditionalRequires<[IsFP64bit]> {
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let DecoderNamespace = "Mips64";
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}
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@ -367,12 +367,12 @@ def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>,
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def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM<0x31>;
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def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, LW_FM<0x39>;
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let Predicates = [HasStdEnc, IsFP64bit], DecoderNamespace = "Mips64" in {
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let AdditionalPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
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def LDC164 : LW_FT<"ldc1", FGR64Opnd, II_LDC1, load>, LW_FM<0x35>;
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def SDC164 : SW_FT<"sdc1", FGR64Opnd, II_SDC1, store>, LW_FM<0x3d>;
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}
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let Predicates = [HasStdEnc, NotFP64bit] in {
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let AdditionalPredicates = [NotFP64bit] in {
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def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>;
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def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>;
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}
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@ -386,30 +386,30 @@ def SDC2 : SW_FT<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>;
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// Indexed loads and stores.
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// Base register + offset register addressing mode (indicated by "x" in the
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// instruction mnemonic) is disallowed under NaCl.
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let Predicates = [HasStdEnc, IsNotNaCl, HasFPIdx] in {
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let AdditionalPredicates = [IsNotNaCl, HasFPIdx] in {
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def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>;
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def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>;
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}
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let Predicates = [HasStdEnc, HasFPIdx, NotFP64bit, NotInMicroMips,
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IsNotNaCl] in {
|
||||
let AdditionalPredicates = [HasFPIdx, NotFP64bit, NotInMicroMips,
|
||||
IsNotNaCl] in {
|
||||
def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>;
|
||||
def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>;
|
||||
}
|
||||
|
||||
let Predicates = [HasStdEnc, HasFPIdx, IsFP64bit],
|
||||
let AdditionalPredicates = [HasFPIdx, IsFP64bit],
|
||||
DecoderNamespace="Mips64" in {
|
||||
def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>;
|
||||
def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>;
|
||||
}
|
||||
|
||||
// Load/store doubleword indexed unaligned.
|
||||
let Predicates = [HasStdEnc, NotFP64bit, IsNotNaCl] in {
|
||||
let AdditionalPredicates = [NotFP64bit, IsNotNaCl] in {
|
||||
def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>;
|
||||
def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>;
|
||||
}
|
||||
|
||||
let Predicates = [HasStdEnc, IsFP64bit], DecoderNamespace="Mips64" in {
|
||||
let AdditionalPredicates = [IsFP64bit], DecoderNamespace="Mips64" in {
|
||||
def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>;
|
||||
def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>;
|
||||
}
|
||||
@ -428,42 +428,42 @@ def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
|
||||
ADDS_FM<0x01, 16>;
|
||||
defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>;
|
||||
|
||||
let Predicates = [HasStdEnc, HasMips32r2] in {
|
||||
let AdditionalPredicates = [HasMips32r2] in {
|
||||
def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
|
||||
MADDS_FM<4, 0>;
|
||||
def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
|
||||
MADDS_FM<5, 0>;
|
||||
}
|
||||
|
||||
let Predicates = [HasStdEnc, HasMips32r2, NoNaNsFPMath] in {
|
||||
let AdditionalPredicates = [HasMips32r2, NoNaNsFPMath] in {
|
||||
def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
|
||||
MADDS_FM<6, 0>;
|
||||
def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
|
||||
MADDS_FM<7, 0>;
|
||||
}
|
||||
|
||||
let Predicates = [HasStdEnc, HasMips32r2, NotFP64bit] in {
|
||||
let AdditionalPredicates = [HasMips32r2, NotFP64bit] in {
|
||||
def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
|
||||
MADDS_FM<4, 1>;
|
||||
def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
|
||||
MADDS_FM<5, 1>;
|
||||
}
|
||||
|
||||
let Predicates = [HasStdEnc, HasMips32r2, NotFP64bit, NoNaNsFPMath] in {
|
||||
let AdditionalPredicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath] in {
|
||||
def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
|
||||
MADDS_FM<6, 1>;
|
||||
def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
|
||||
MADDS_FM<7, 1>;
|
||||
}
|
||||
|
||||
let Predicates = [HasStdEnc, HasMips32r2, IsFP64bit], isCodeGenOnly=1 in {
|
||||
let AdditionalPredicates = [HasMips32r2, IsFP64bit], isCodeGenOnly=1 in {
|
||||
def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>,
|
||||
MADDS_FM<4, 1>;
|
||||
def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
|
||||
MADDS_FM<5, 1>;
|
||||
}
|
||||
|
||||
let Predicates = [HasStdEnc, HasMips32r2, IsFP64bit, NoNaNsFPMath],
|
||||
let AdditionalPredicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath],
|
||||
isCodeGenOnly=1 in {
|
||||
def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>,
|
||||
MADDS_FM<6, 1>;
|
||||
@ -509,10 +509,10 @@ def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
|
||||
/// Floating Point Compare
|
||||
def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>;
|
||||
def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
|
||||
Requires<[HasStdEnc, NotFP64bit]>;
|
||||
AdditionalRequires<[NotFP64bit]>;
|
||||
let DecoderNamespace = "Mips64" in
|
||||
def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
|
||||
Requires<[HasStdEnc, IsFP64bit]>;
|
||||
AdditionalRequires<[IsFP64bit]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Floating Point Pseudo-Instructions
|
||||
@ -525,9 +525,9 @@ class BuildPairF64Base<RegisterOperand RO> :
|
||||
[(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))]>;
|
||||
|
||||
def BuildPairF64 : BuildPairF64Base<AFGR64Opnd>,
|
||||
Requires<[HasStdEnc, NotFP64bit]>;
|
||||
AdditionalRequires<[NotFP64bit]>;
|
||||
def BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>,
|
||||
Requires<[HasStdEnc, IsFP64bit]>;
|
||||
AdditionalRequires<[IsFP64bit]>;
|
||||
|
||||
// This pseudo instr gets expanded into 2 mfc1 instrs after register
|
||||
// allocation.
|
||||
@ -538,9 +538,9 @@ class ExtractElementF64Base<RegisterOperand RO> :
|
||||
[(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))]>;
|
||||
|
||||
def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>,
|
||||
Requires<[HasStdEnc, NotFP64bit]>;
|
||||
AdditionalRequires<[NotFP64bit]>;
|
||||
def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>,
|
||||
Requires<[HasStdEnc, IsFP64bit]>;
|
||||
AdditionalRequires<[IsFP64bit]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// InstAliases.
|
||||
@ -559,7 +559,7 @@ def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)),
|
||||
def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
|
||||
(TRUNC_W_S FGR32Opnd:$src)>;
|
||||
|
||||
let Predicates = [HasStdEnc, NotFP64bit] in {
|
||||
let AdditionalPredicates = [NotFP64bit] in {
|
||||
def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
|
||||
(PseudoCVT_D32_W GPR32Opnd:$src)>;
|
||||
def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src),
|
||||
@ -570,7 +570,7 @@ let Predicates = [HasStdEnc, NotFP64bit] in {
|
||||
(CVT_D32_S FGR32Opnd:$src)>;
|
||||
}
|
||||
|
||||
let Predicates = [HasStdEnc, IsFP64bit] in {
|
||||
let AdditionalPredicates = [IsFP64bit] in {
|
||||
def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>;
|
||||
def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>;
|
||||
|
||||
@ -599,12 +599,12 @@ let AddedComplexity = 40 in {
|
||||
def : LoadRegImmPat<LWC1, f32, load>;
|
||||
def : StoreRegImmPat<SWC1, f32>;
|
||||
|
||||
let Predicates = [HasStdEnc, IsFP64bit] in {
|
||||
let AdditionalPredicates = [IsFP64bit] in {
|
||||
def : LoadRegImmPat<LDC164, f64, load>;
|
||||
def : StoreRegImmPat<SDC164, f64>;
|
||||
}
|
||||
|
||||
let Predicates = [HasStdEnc, NotFP64bit] in {
|
||||
let AdditionalPredicates = [NotFP64bit] in {
|
||||
def : LoadRegImmPat<LDC1, f64, load>;
|
||||
def : StoreRegImmPat<SDC1, f64>;
|
||||
}
|
||||
|
||||
@ -93,8 +93,8 @@ class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
|
||||
// Mips32/64 Instruction Format
|
||||
class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
|
||||
InstrItinClass itin, Format f, string opstr = ""> :
|
||||
MipsInst<outs, ins, asmstr, pattern, itin, f> {
|
||||
let Predicates = [HasStdEnc];
|
||||
MipsInst<outs, ins, asmstr, pattern, itin, f>, PredicateControl {
|
||||
let EncodingPredicates = [HasStdEnc];
|
||||
string BaseOpcode = opstr;
|
||||
string Arch;
|
||||
}
|
||||
@ -109,9 +109,9 @@ class MipsPseudo<dag outs, dag ins, list<dag> pattern,
|
||||
|
||||
// Mips32/64 Pseudo Instruction Format
|
||||
class PseudoSE<dag outs, dag ins, list<dag> pattern,
|
||||
InstrItinClass itin = IIPseudo>:
|
||||
MipsPseudo<outs, ins, pattern, itin> {
|
||||
let Predicates = [HasStdEnc];
|
||||
InstrItinClass itin = IIPseudo> :
|
||||
MipsPseudo<outs, ins, pattern, itin>, PredicateControl {
|
||||
let EncodingPredicates = [HasStdEnc];
|
||||
}
|
||||
|
||||
// Pseudo-instructions for alternate assembly syntax (never used by codegen).
|
||||
|
||||
@ -194,8 +194,8 @@ def IsLE : Predicate<"Subtarget.isLittle()">;
|
||||
def IsBE : Predicate<"!Subtarget.isLittle()">;
|
||||
def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
|
||||
|
||||
class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
|
||||
let Predicates = [HasStdEnc];
|
||||
class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
|
||||
let EncodingPredicates = [HasStdEnc];
|
||||
}
|
||||
|
||||
class IsCommutable {
|
||||
@ -601,7 +601,7 @@ class UncondBranch<Instruction BEQInst> :
|
||||
let isTerminator = 1;
|
||||
let isBarrier = 1;
|
||||
let hasDelaySlot = 1;
|
||||
let Predicates = [HasStdEnc, RelocPIC];
|
||||
let AdditionalPredicates = [RelocPIC];
|
||||
let Defs = [AT];
|
||||
}
|
||||
|
||||
@ -791,26 +791,26 @@ class EffectiveAddress<string opstr, RegisterOperand RO> :
|
||||
class CountLeading0<string opstr, RegisterOperand RO>:
|
||||
InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
|
||||
[(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>,
|
||||
Requires<[HasStdEnc, HasBitCount]>;
|
||||
AdditionalRequires<[HasBitCount]>;
|
||||
|
||||
class CountLeading1<string opstr, RegisterOperand RO>:
|
||||
InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
|
||||
[(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>,
|
||||
Requires<[HasStdEnc, HasBitCount]>;
|
||||
AdditionalRequires<[HasBitCount]>;
|
||||
|
||||
// Sign Extend in Register.
|
||||
class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
|
||||
InstrItinClass itin> :
|
||||
InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
|
||||
[(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr> {
|
||||
let Predicates = [HasStdEnc, HasSEInReg];
|
||||
let AdditionalPredicates = [HasSEInReg];
|
||||
}
|
||||
|
||||
// Subword Swap
|
||||
class SubwordSwap<string opstr, RegisterOperand RO>:
|
||||
InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
|
||||
NoItinerary, FrmR, opstr> {
|
||||
let Predicates = [HasStdEnc, HasSwap];
|
||||
let AdditionalPredicates = [HasSwap];
|
||||
let neverHasSideEffects = 1;
|
||||
}
|
||||
|
||||
@ -826,7 +826,7 @@ class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
|
||||
!strconcat(opstr, " $rt, $rs, $pos, $size"),
|
||||
[(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
|
||||
FrmR, opstr> {
|
||||
let Predicates = [HasStdEnc, HasMips32r2];
|
||||
let AdditionalPredicates = [HasMips32r2];
|
||||
}
|
||||
|
||||
class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
|
||||
@ -835,7 +835,7 @@ class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
|
||||
!strconcat(opstr, " $rt, $rs, $pos, $size"),
|
||||
[(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
|
||||
NoItinerary, FrmR, opstr> {
|
||||
let Predicates = [HasStdEnc, HasMips32r2];
|
||||
let AdditionalPredicates = [HasMips32r2];
|
||||
let Constraints = "$src = $rt";
|
||||
}
|
||||
|
||||
@ -1000,7 +1000,7 @@ def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
|
||||
SRLV_FM<7, 0>;
|
||||
|
||||
// Rotate Instructions
|
||||
let Predicates = [HasStdEnc, HasMips32r2] in {
|
||||
let AdditionalPredicates = [HasMips32r2] in {
|
||||
def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
|
||||
immZExt5>, SRA_FM<2, 1>;
|
||||
def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
|
||||
@ -1022,7 +1022,8 @@ def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
|
||||
def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
|
||||
|
||||
/// load/store left/right
|
||||
let Predicates = [NotInMicroMips] in {
|
||||
let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
|
||||
AdditionalPredicates = [NotInMicroMips] in {
|
||||
def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>;
|
||||
def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>;
|
||||
def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>;
|
||||
@ -1054,7 +1055,8 @@ def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>;
|
||||
def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
|
||||
def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
|
||||
|
||||
let Predicates = [NotInMicroMips] in {
|
||||
let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
|
||||
AdditionalPredicates = [NotInMicroMips] in {
|
||||
def WAIT : WAIT_FT<"wait">, WAIT_FM;
|
||||
|
||||
/// Load-linked, Store-conditional
|
||||
@ -1064,7 +1066,7 @@ def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>;
|
||||
|
||||
/// Jump and Branch Instructions
|
||||
def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
|
||||
Requires<[HasStdEnc, RelocStatic]>, IsBranch;
|
||||
AdditionalRequires<[RelocStatic]>, IsBranch;
|
||||
def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
|
||||
def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
|
||||
def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
|
||||
@ -1079,7 +1081,7 @@ def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
|
||||
def B : UncondBranch<BEQ>;
|
||||
|
||||
def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
|
||||
let Predicates = [HasStdEnc, NotInMicroMips] in {
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
|
||||
def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
|
||||
}
|
||||
@ -1125,7 +1127,8 @@ def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
|
||||
|
||||
def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
|
||||
def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
|
||||
let Predicates = [NotInMicroMips] in {
|
||||
let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
|
||||
AdditionalPredicates = [NotInMicroMips] in {
|
||||
def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>;
|
||||
def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
|
||||
}
|
||||
@ -1156,7 +1159,7 @@ def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>;
|
||||
def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>;
|
||||
def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>;
|
||||
|
||||
let Predicates = [HasStdEnc, NotDSP] in {
|
||||
let AdditionalPredicates = [NotDSP] in {
|
||||
def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>;
|
||||
def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>;
|
||||
def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>;
|
||||
@ -1307,7 +1310,7 @@ def : MipsPat<(i32 imm:$imm),
|
||||
// Carry MipsPatterns
|
||||
def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
|
||||
(SUBu GPR32:$lhs, GPR32:$rhs)>;
|
||||
let Predicates = [HasStdEnc, NotDSP] in {
|
||||
let AdditionalPredicates = [NotDSP] in {
|
||||
def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
|
||||
(ADDu GPR32:$lhs, GPR32:$rhs)>;
|
||||
def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
|
||||
|
||||
Loading…
Reference in New Issue
Block a user