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Nuke a few more unused asm strings

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115193 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-09-30 19:53:58 +00:00
parent 2622f4622c
commit a3fbadfcd8
3 changed files with 19 additions and 19 deletions
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14
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -696,7 +696,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
OutStreamer.EmitInstruction(AddInst); OutStreamer.EmitInstruction(AddInst);
return; return;
} }
case ARM::PICADD: { // FIXME: Remove asm string from td file. case ARM::PICADD: {
// This is a pseudo op for a label + instruction sequence, which looks like: // This is a pseudo op for a label + instruction sequence, which looks like:
// LPC0: // LPC0:
// add r0, pc, r0 // add r0, pc, r0
@ -767,7 +767,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
return; return;
} }
case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file. case ARM::CONSTPOOL_ENTRY: {
/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
/// in the function. The first operand is the ID# for this instruction, the /// in the function. The first operand is the ID# for this instruction, the
/// second is the index into the MachineConstantPool that this is, the third /// second is the index into the MachineConstantPool that this is, the third
@ -786,7 +786,8 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
return; return;
} }
case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file. case ARM::MOVi2pieces: {
// FIXME: We'd like to remove the asm string in the .td file, but the
// This is a hack that lowers as a two instruction sequence. // This is a hack that lowers as a two instruction sequence.
unsigned DstReg = MI->getOperand(0).getReg(); unsigned DstReg = MI->getOperand(0).getReg();
unsigned ImmVal = (unsigned)MI->getOperand(1).getImm(); unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
@ -823,7 +824,8 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
} }
return; return;
} }
case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file. case ARM::MOVi32imm: {
// FIXME: We'd like to remove the asm string in the .td file, but the
// This is a hack that lowers as a two instruction sequence. // This is a hack that lowers as a two instruction sequence.
unsigned DstReg = MI->getOperand(0).getReg(); unsigned DstReg = MI->getOperand(0).getReg();
const MachineOperand &MO = MI->getOperand(1); const MachineOperand &MO = MI->getOperand(1);
@ -924,7 +926,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
} }
case ARM::t2Int_eh_sjlj_setjmp: case ARM::t2Int_eh_sjlj_setjmp:
case ARM::t2Int_eh_sjlj_setjmp_nofp: case ARM::t2Int_eh_sjlj_setjmp_nofp:
case ARM::tInt_eh_sjlj_setjmp: { // FIXME: Remove asmstring from td file. case ARM::tInt_eh_sjlj_setjmp: {
// Two incoming args: GPR:$src, GPR:$val // Two incoming args: GPR:$src, GPR:$val
// mov $val, pc // mov $val, pc
// adds $val, #7 // adds $val, #7
@ -1008,7 +1010,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
} }
case ARM::Int_eh_sjlj_setjmp_nofp: case ARM::Int_eh_sjlj_setjmp_nofp:
case ARM::Int_eh_sjlj_setjmp: { // FIXME: Remove asmstring from td file. case ARM::Int_eh_sjlj_setjmp: {
// Two incoming args: GPR:$src, GPR:$val // Two incoming args: GPR:$src, GPR:$val
// add $val, pc, #8 // add $val, pc, #8
// str $val, [$src, #+4] // str $val, [$src, #+4]

21
lib/Target/ARM/ARMInstrInfo.td
View File

@ -688,8 +688,7 @@ multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
let neverHasSideEffects = 1, isNotDuplicable = 1 in let neverHasSideEffects = 1, isNotDuplicable = 1 in
def CONSTPOOL_ENTRY : def CONSTPOOL_ENTRY :
PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
i32imm:$size), NoItinerary, i32imm:$size), NoItinerary, "", []>;
"${instid:label} ${cpidx:cpentry}", []>;
// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
// from removing one half of the matched pairs. That breaks PEI, which assumes // from removing one half of the matched pairs. That breaks PEI, which assumes
@ -845,41 +844,41 @@ def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
// Address computation and loads and stores in PIC mode. // Address computation and loads and stores in PIC mode.
let isNotDuplicable = 1 in { let isNotDuplicable = 1 in {
def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
Pseudo, IIC_iALUr, "\n$cp:\n\tadd$p\t$dst, pc, $a", Pseudo, IIC_iALUr, "",
[(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>; [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
let AddedComplexity = 10 in { let AddedComplexity = 10 in {
def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, IIC_iLoad_r, "\n${addr:label}:\n\tldr$p\t$dst, $addr", Pseudo, IIC_iLoad_r, "",
[(set GPR:$dst, (load addrmodepc:$addr))]>; [(set GPR:$dst, (load addrmodepc:$addr))]>;
def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, IIC_iLoad_bh_r, "\n${addr:label}:\n\tldrh${p}\t$dst, $addr", Pseudo, IIC_iLoad_bh_r, "",
[(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>; [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, IIC_iLoad_bh_r, "\n${addr:label}:\n\tldrb${p}\t$dst, $addr", Pseudo, IIC_iLoad_bh_r, "",
[(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>; [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, IIC_iLoad_bh_r, "\n${addr:label}:\n\tldrsh${p}\t$dst, $addr", Pseudo, IIC_iLoad_bh_r, "",
[(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>; [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, IIC_iLoad_bh_r, "\n${addr:label}:\n\tldrsb${p}\t$dst, $addr", Pseudo, IIC_iLoad_bh_r, "",
[(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>; [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
} }
let AddedComplexity = 10 in { let AddedComplexity = 10 in {
def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
Pseudo, IIC_iStore_r, "\n${addr:label}:\n\tstr$p\t$src, $addr", Pseudo, IIC_iStore_r, "",
[(store GPR:$src, addrmodepc:$addr)]>; [(store GPR:$src, addrmodepc:$addr)]>;
def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
Pseudo, IIC_iStore_bh_r, "\n${addr:label}:\n\tstrh${p}\t$src, $addr", Pseudo, IIC_iStore_bh_r, "",
[(truncstorei16 GPR:$src, addrmodepc:$addr)]>; [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
Pseudo, IIC_iStore_bh_r, "\n${addr:label}:\n\tstrb${p}\t$src, $addr", Pseudo, IIC_iStore_bh_r, "",
[(truncstorei8 GPR:$src, addrmodepc:$addr)]>; [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
} }
} // isNotDuplicable = 1 } // isNotDuplicable = 1

3
lib/Target/ARM/ARMInstrThumb.td
View File

@ -208,8 +208,7 @@ def tCPS : T1I<(outs), (ins cps_opt:$opt), NoItinerary, "cps$opt",
// For both thumb1 and thumb2. // For both thumb1 and thumb2.
let isNotDuplicable = 1 in let isNotDuplicable = 1 in
def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
"\n$cp:\n\tadd\t$dst, pc",
[(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>, [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
T1Special<{0,0,?,?}> { T1Special<{0,0,?,?}> {
let Inst{6-3} = 0b1111; // A8.6.6 Rm = pc let Inst{6-3} = 0b1111; // A8.6.6 Rm = pc